Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C3MOS logic with low power conventional CMOS logic. The combined C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: A latch circuit includes an input part receiving an external input signal; a plurality of CMOS inverter circuits divided into a first group that includes a first CMOS inverter circuit and a second CMOS inverter circuit outputting inverted data with respect to the input signal, and a second group that includes a third CMOS inverter circuit and a fourth CMOS inverter circuit outputting the same data as the input signal; and a feedback path through which the input signal is fed back to the input part via the plurality of CMOS inverter circuits, wherein a second-polarity drain belonging to one of the first CMOS inverter circuit and the second CMOS inverter circuit is arranged between a first-polarity drain belonging to the first CMOS inverter circuit and a first-polarity drain belonging to the second CMOS inverter circuit.

Abstract: A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors for implementing a predetermined logic function. The p-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection. The outer diffusion connection of the p-type transistor network is connected to the first dedicated logic terminal, and the first network gate connection of the p-type transistor network is connected to the first logic input. The second logic block consists of a network of n-type transistors which implements a logic function complementary to the logic function implemented by the first logic block. The n-type transistor network has an outer diffusion connection, a first network gate connection, and an inner diffusion connection.

Abstract: It is intended to provide a semiconductor device which comprises an SGT-based, highly-integrated, high-speed, at least two-stage CMOS inverter cascade circuit configured to allow a pMOS SGT to have a gate width two times greater than that of an nMOS SGT. A semiconductor device of the present invention comprises a CMOS inverter cascade circuit having at least two-stage CMOS inverter, wherein: a first CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 1st column and an intersection of the 2nd row and the 1st column, and an nMOS SGT arranged at an intersection of the 1st row and the 2nd column; and a second CMOS inverter includes two pMOS SGT arranged at respective ones of an intersection of the 1st row and the 3rd column and an intersection of the 2nd row and the 3rd column, and an nMOS SGT arranged at an intersection of the 2nd row and the 2nd column.

Abstract: A circuit for a multiplexer includes a pair of NAND gates with outputs coupled to an OAI gate constructed from a complementary circuit formed from solid state devices. A current flow controller formed from solid state devices is coupled to one of the NAND gates. When activated the controller inhibits the flow of current through the NAND gate and a portion of the OAI gate to which the controller is connected. As a consequence, leakage power is not consumed within the multiplexer. Several of the applications in which the circuit is used are also demonstrated in the specification.

Abstract: Low voltage swing techniques are provided for simultaneously reducing the active and standby mode power consumption and enhancing the noise immunity in domino logic circuits. One or both the upper and lower boundaries of the voltage swing at the dynamic node may be different from the upper and lower boundaries of the voltage swing at the output node. Further, the domino logic circuit may use dual Vt thereby reducing the short-circuit current during operation. Meanwhile, full voltage swing signals may be maintained at the inputs and outputs for high speed operation. The low swing circuit techniques are provided that modify the output voltage swing of a domino gate, thereby reducing the active mode power consumption.

Abstract: A dynamic logic circuit includes a first region including a plurality of PMOS transistors and a second region, adjacent to the first region, including a plurality of NMOS transistors connected with at least one of the plurality of PMOS transistors. Channel sizes of the plurality of NMOS transistors are greater than channel sizes of the plurality of PMOS transistors.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.

Abstract: Disclosed is a logic circuit includes a first NAND gate that receives a first pulse signal and a first selection signal, a first inverter gate that inverts an output signal of the first NAND gate to output a resulting signal, a second NAND gate that receives a second pulse signal and the first selection signal, a second inverter gate that inverts an output signal of the second NAND gate, a first PMOS transistor with a drain terminal connected to an output of the first NAND gate, a gate terminal connected to an output of the second NAND gate and a source terminal connected to a power supply voltage, and a first NMOS transistor with a drain terminal connected to an output of the first inverter gate, a gate terminal connected to an output of the second inverter gate and a source terminal connected to a ground potential.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: Stacked inverter delay chains. In accordance with a first embodiment of the present invention, a series stack of two p-type devices is coupled to a series stack of three n-type devices, forming a stacked inverter comprising desirable delay, die area and power characteristics. Two stacked inverters are coupled together to form a stacked inverter delay chain that is more efficient in terms of die area, active and passive power consumption than conventional delay chains comprising conventional inverters.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A source-follower circuit includes a current source and a source follower output, and the source follower output is coupled to the output node. A second MOS transistor selectively couples the source-follower circuit to a second reference voltage when the output node is to be in the second state.

Abstract: A complementary energy path adiabatic logic (CEPAL) includes an evaluation network and a power clock network. The evaluation network is a logic circuit composed of P-type MOS transistors and N-type MOS transistors. The power clock network includes a P-type and N-type MOS transistors and additional P-type and N-type MOS transistors, with each of the transistors involved in the power clock network acting as an active diode.

Abstract: A process performs multiple evaluations of text simultaneously. There are multiple counters, each with pattern-amount pairs. The pattern-amount pairs are accumulated into a single finite-state machine, with each state having a list of (counter, value) pairs instead of a single value. While the finite-state machine is applied to text, a score for each counter is accumulated by summing values for the counter from value lists of visited states. With one state transition per character, evaluating text using one finite-state machine for multiple counters is more efficient than using separate finite-state machines for counters or patterns.

Abstract: In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a load, a second terminal of the load coupled to a further reference source, the further MuGFET device configured to receive a further input signal at a gate thereof, and wherein the MuGFET device and the further MuGFET device are disposed above a substrate and configured to provide an output signal at the first terminal of the load.

Abstract: A method of designing logic circuit provides a logic circuit which includes a first transistor network and a complementary second transistor network connected at a central node. The central node serves as a first logic output. Each of the transistor networks is also connected to a respective root. A third transistor network is connected between an intermediate node of one of the transistor networks and the network's respective root. The third transistor network has a complementary structure to the transistors between the intermediate node and the central node, and includes a logic output The third transistor network (the graft network) provides a second logic output to the logic circuit.

Abstract: In one embodiment, an integrated device is disclosed. For example, in one embodiment of the present invention, a device comprises a logic control, and a combination differential driver coupled to the logic control, wherein the logic control receives a control signal for configuring the combination differential driver as a Low Voltage Differential Signaling (LVDS) driver or as a Transition Minimized Differential Signaling (TMDS) driver.

Abstract: A complementary signal generating circuit according to an embodiment of the present invention includes: an inverting element inverting a first signal to generate a second signal; a first transistor connecting a first power supply potential and a first output terminal electrically in accordance with the first signal; a second transistor connecting the first output terminal and a second power supply potential electrically in accordance with the second signal; a third transistor connecting the first power supply potential and a second output terminal electrically in accordance with the second signal; and a fourth transistor connecting the second output terminal and the second power supply potential electrically in accordance with the first signal.

Abstract: In a logic circuit, a first switching device is connected between a first voltage and an output terminal through which an output signal is output. The switching device is selectively activated and deactivated based on an input signal. A second switching device is connected to a ground voltage and is selectively activated and deactivated based on the input signal. A control circuit outputs a control signal in response to the input signal. The control signal has a first voltage level during a first time period in which a state of the input signal changes, and has a second voltage level during a second time period in which a state of the input signal is constant. The second voltage level is lower than the first voltage level. A field relaxation circuit is connected between the terminal through which the output signal is output.

Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors. Also, there is provided a design structure embodied in a machine readable medium used in a design process, and which includes such error correcting logic system.

Abstract: A tapered chain of delay elements. The chain of delay elements includes a plurality of delay elements comprising a plurality of smaller sized stacked inverter delay elements each configured to implement a first delay, and a plurality of larger sized stacked inverter delay elements each configured to implement a second delay larger than the first delay. A switch circuit is coupled to the plurality of delay elements and is configured to select at least one of the plurality of delay elements to create a delay signal path having an amount of delay in accordance with a number of delay elements comprising the delay signal path. An input is coupled to a first delay element of the delay signal path to receive an input signal. An output is coupled to the switch circuit, wherein the output is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: The present invention includes a circuit-level system and method for preventing the propagation of soft errors in logic cells. A radiation jammer circuit in accordance with the present invention, including an RC differentiator and a depletion mode MOS circuit, when inserted at the output of a logic cell, significantly reduces the propagation of transient glitches. The radiation jammer circuit is a novel transistor-level optimization technique, which has been used to reduce soft errors in a logic circuit. A method to insert radiation jammer cells on selective nodes in a logic circuit for low overheads in terms of delay, power, and area is also introduced.

Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.

Abstract: A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.

Abstract: A modified high-speed flip-flop including an input circuit, a smart window circuit, a smart keeper circuit, a pre-charge circuit, a discharge circuit, a slave storage circuit, and an output circuit. Additionally, a circuit including the modified high-speed flip-flop, the circuit also including a non-zero operating voltage provided to the flip-flop, a common voltage provided to the flip-flop, a clock signal input to the flip-flop, a data signal input to the flip-flop wherein the data signal has a high state and a low state, and an output signal from the flip-flop wherein the output signal has a high state and a low state.

Abstract: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

Abstract: A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

Abstract: A transmitter provides fast settling times, slew rate control, and power efficiency while reducing the need for large external capacitors. The transmitter typically includes a pre-driver, driver, and replica circuit. The pre-driver can shift the voltage level of an input signal to produce a shifted signal. The pre-driver can shift the voltage level in response to a selectable load resistance circuit and a voltage regulation feedback signal. The driver receives the shifted signal and generates a driver output signal in response to the received shifted signal. The replica circuit can be a scaled replica of the pre-driver and the driver using scaled components from the pre-driver and driver circuits. The scaled components can be used to generate the voltage regulation feedback signal. The generated voltage regulation feedback signal represents, for example, whether the output voltage of the driver output is above a reference voltage.

Abstract: An inverter includes a first PMOS transistor having a gate electrode coupled to a first input port, a first electrode coupled to a first node and a second electrode coupled to the gate electrode or a second power source; a second PMOS transistor having a gate electrode coupled to the first input port, and first and second electrodes coupled respectively to a first power source and an output port; a third PMOS transistor having a gate electrode coupled to the first node, first and second electrodes coupled respectively to the output port and a second input port; and a capacitor coupled between the first node and the output port.

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract: An limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.

Abstract: A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract: A CMOS LSI includes an inverter including first and second MOS transistors, a relatively long metal interconnection connected to an input node of the inverter, first and second diodes releasing charges born by the metal interconnection during a plasma process to first and second wells, and first and second MOS transistors maintaining a voltage between the first and second wells at a level not higher than a prescribed voltage. Therefore, even when an antenna ratio is high, a gate oxide film in the first and second MOS transistors is not damaged during the plasma process.

Abstract: A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

Abstract: A digital circuit comprises: a first arm including a first metal oxide semiconductor field effect transistor (M3) configured to act as a load device; a second arm including a second metal oxide semiconductor field effect transistor (M4) configured to act as a load device; and a switch (M1, M2) for selecting one of the first and second arms. Each of the first and second transistors (M3, M4) has a channel length of 100 nm or below and is biased to operate in the weak inversion regime. In an alternative circuit, each load device (M3, M4) has its bulk connected to its drain and is biased to operate in the weak inversion regime.

Abstract: A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, wherein a resistance of the first converter is variable. A second converter couples to the first converter, the second converter is operable to receive a signal in the second type and convert the signal into the first type, wherein a resistance of the second converter is variable. The driver is operable to scale the resistance of the first and second converters to provide a constant ratio between the resistance of the first and second converters.

Abstract: An inverting cell including a first inverter having first and second inputs; a second inverter having first and second inputs, wherein the second input of the second inverter is connected to the first input of the first inverter and the output of the first and second inverters is connected to the second input of the first inverter; and a third inverter connected between the output of the first and second inverters and the first input of the second inverter.

Abstract: A low-voltage differential signal driver for high-speed digital transmission includes a first converter operable to receive a signal in a first type and convert the signal into a second type, and a cascode current mirror coupled to the first converter. The cascode current mirror provides an impedance level that increases a differential output voltage.

Abstract: A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the precharge node to charge the precharge node and the second switch is responsive to the one of a high or low voltage at the precharge node to control the first switch charging the precharge node. The first switch is preferably a p-channel transistor and the second switch is preferably an n-channel transistor. The circuit also includes an output terminal, an inverter coupled between the precharge node and the output terminal and feedback circuitry coupled between the output terminal and coupled to the second switch to provide the charge state of the precharge node to the second switch. The circuit further includes a pair of transistors having serially connected current paths, the serially connected current paths being coupled between the precharge node and a reference source.

Abstract: An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes building multiple-output static NAND gates that compute the subfunctions of three or more inputs and building multiple-output static NOR gates that compute the subfunctions of two or more inputs. The approach also includes building multiple-output static XOR-XNOR gates that are capable of computing two-input XOR, three-input XOR, two-input XNOR, and three-input XNOR, and building multiple-output static Propagate-Generate (PG) compound gates. The approach further includes building carry propagate adders, priority encoders, binary-to-thermometers, decoders, etc. that are capable of using the multiple-output static gates embodied in the present invention.

Abstract: A logic circuit includes a storage node coupled to a data line and a soft-error protection circuit to change a logical value of the storage node from a first value to a second value when the logical value of the storage node does not correspond a logical value of an output node. The logic circuit may be a set dominant latch and a memory circuit may be formed based on the set dominant latch.

Abstract: A driver circuit is provided herein. In general, the driver circuit includes a driver portion, a common mode feedback portion and a current replication portion. The feedback portion receives a common mode voltage (vcm) from the driver portion and an alternative common mode voltage (vcm_alt) from the current replication portion. The feedback portion selects one of the common mode voltages for comparison with a reference voltage and generates a feedback bias signal (vcmfb) based on a voltage difference there between. When the driver circuit is enabled, the actual common mode voltage (vcm) is used to maintain the output common mode voltage around the reference voltage. When the driver circuit is disabled, the alternative common mode voltage (vcm_alt) is used to keep the bias signal (vcmfb) from drifting away.

Abstract: Disclosed is a logic circuit including first and second input terminals, supplied with respective logic signals, and first and second MOS transistors, having sources respectively connected to associated ones of the first and second input terminals and gates cross-connected to the second and first input terminals. The drains of the first and second MOS transistors are connected in common. The logic circuit also includes a MOS transistor, connected between a first power supply and a common node of the drains of the first and second MOS transistors and having a gate supplied with a reset signal so that the MOS transistor is turned on at the time of resetting. The logic circuit further includes an inverter having an input end connected to the common node.

Abstract: Conditioning logic modifies the electrical characteristics of conventional logic circuits to improve speed, power, and timing margins. This is accomplished by adding circuitry to pre-condition the state of the circuit to optimize any desired transition. Basic functionality of the logic circuit in response to the inputs is unchanged, but output delays, power dissipation, and timing margins can be improved and other characteristics of the circuit can also be controlled by the conditioning circuitry such as voltage levels, leakage current and power dissipation. The effect of the conditioning circuitry on the electrical and timing parameters of the logic function is controlled by binary feedback inputs to the conditioning circuitry. Feedback inputs can be generated from any combination of logic states and clock inputs including clock inputs and logic inputs not used in the logic function receiving the feedback input.

Abstract: A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.

Abstract: A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.