Abstract: A semiconductor integrated circuit connected between a first node and a second node includes first to fourth transistors. When a signal at the second node changes, the fourth transistor is turned on, and a potential obtained by shifting a third potential by the threshold of the fourth transistor is applied to the gate of the second transistor.

Abstract: A semiconductor device that is hardly broken is provided. Alternatively, a semiconductor device having high reliability is provided. The semiconductor device includes a first circuit, a second circuit, a first wiring, a second wiring, and a third wiring. The second circuit has a function of protecting the first circuit. The second circuit includes a first transistor including an oxide semiconductor film. The first wiring is electrically connected to the first circuit through the second circuit. The first wiring is electrically connected to the first circuit through the second circuit. The first wiring has a function of inputting a signal. The second wiring is electrically connected to the first circuit. The second wiring is electrically connected to one of a source electrode and a drain electrode of the first transistor. The third wiring is electrically connected to a gate electrode of the first transistor included in the second circuit.

Abstract: Apparatus and methods facilitate analysis of events associated with network and computer systems. Event data, such as security threats, are comparison matched with event rules of event rule sets associated with each network or computer system to determine whether the items are potentially significant. Additionally, the system-event data may be scored where the score is used for prioritizing system-event data as to their significance. Associated with the comparison matching are various analytics that further analyze event data for measuring and analyzing the system-event data according to various algorithms.

Abstract: Apparatus and methods for reducing noise and distortion in current digital-to-analog converters (IDACs). Compensating capacitors may be connected to current sources in an IDAC. The compensating capacitors may be driven with signals 5 derived from the output of the IDAC to cancel transient current spikes that would otherwise occur on the output of the IDAC.

Abstract: A state-retaining logic cell may include a plurality of inverters, an output node non-volatile (NVM) storage cell, and an input node NVM storage cell. The plurality of inverters may include a feed-forward inverter and a feed-back inverter disposed in a back-to-back arrangement. The output node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an output node of the feed-forward and the feed-back inverters, and the second terminal is connected to a programming rail. The input node NVM storage cell may include first and second terminals, where the first terminal is connected adjacent an input node of the feed-forward and the feed-back inverters, and the second terminal is connected to the programming rail.

Abstract: A semiconductor integrated circuit includes: a first wire through which a signal is transmitted; a second wire that is not used for signal transmission; a switch that creates or breaks an electric connection between the first wire and the second wire; and a control circuit that controls the switch according to an potential of the signal, which is transmitted through the first wire, so that part of charge stored in a first wire capacitor of the first wire moves to a second wire capacitor of the second wire and is stored in the second wire capacitor and the charge stored in the second wire capacitor are drawn to the first wire capacitor to charge the first wire capacitor.

Abstract: A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.

Abstract: An apparatus and a job scheduling method are provided. For example, the apparatus is a multi-core processing apparatus. The apparatus and method minimize performance degradation of a core caused by sharing resources by dynamically managing a maximum number of jobs assigned to each core of the apparatus. The apparatus includes at least one core including an active cycle counting unit configured to store a number of active cycles and a stall cycle counting unit configured to store a number of stall cycles and a job scheduler configured to assign at least one job to each of the at least one core, based on the number of active cycles and the number of stall cycles. When the ratio of the number of stall cycles to a number of active cycles for a core is too great, the job scheduler assigns fewer jobs to that core to improve performance.

Abstract: A power supply circuit includes a control switch, a synchronous switch, an inductor, and a voltage ramping circuit. A common node in the power supply serially connects the control switch to the synchronous switch. The common node is further coupled to the inductor that supplies current to a load based on switching the control switch and the synchronous switch to respective ON/OFF and OFF/ON states. The voltage ramping circuit generates and controls ramping of a gate voltage of the control switch based at least in part on a magnitude of a feedback voltage received on a circuit path from the common node. The multi-stage ramping of a switch control voltage reduces one or more of the following: i) QRR losses, ii) switching losses, and/or iii) a dead time of the power supply.

Abstract: A voltage generating circuit includes a first supply voltage node, a first switching device, a sub voltage generating circuit, and a second switching device. The first supply voltage node is configured to have a first supply voltage value, and is coupled with the first switching device. The sub voltage generating circuit is coupled in between the first switching device and the second switching device. The first switching circuit and the second switching circuit are configured to receive a control signal behaving based on the first supply voltage value and a second supply voltage value different from the first supply voltage value.

Abstract: A data input circuit may include a data latch unit suitable for latching input data as latch data in response to first and second latch signals; a data signal generation unit suitable for outputting first and second data signals corresponding to the latch data; a first drive unit suitable for pulling up or down a first input/output data line of an input/output data line pair in response to the first and second data signals; and a second drive unit suitable for pulling up or down a second input/output data line of the input/output data line pair in response to the first and second data signals, wherein the first and second drive units adjust pull-up levels of the first and second input/output data lines in response to a data input control signal.

Abstract: A semiconductor device has a small area and constitutes a CMOS 3-input NAND circuit by using surrounding gate transistors (SGTs) that are vertical transistors. In a 3-input NAND circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NAND circuit have the following configuration. Planar silicon layers are disposed on a substrate. The drain, gate, and source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planer silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NAND circuit with a small area is provided.

Abstract: Embodiments include an apparatus, system, and method related to a body driven field effect transistor (FET). In embodiments, a body terminal of the FET may be electrically coupled with a source terminal of a second FET, and a drain terminal of the FET may be electrically coupled with a drain terminal of the second FET. Other embodiments may be described.

Abstract: According to one embodiment, a semiconductor integrated device includes a first node that receives a first voltage, a second node that receives a second voltage, and an electrode. A PMOS transistor is coupled between the first node and the electrode. An NMOS transistor is coupled between the second node and the electrode. A control signal at a voltage lower than the second voltage is supplied to a gate electrode of the PMOS transistor. A control signal at a voltage higher than the first voltage is supplied to a gate electrode of the NMOS transistor.

Abstract: A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.

Abstract: A latch circuit includes an input stage, an amplifying stage and a clock gating circuit. The input stage is arranged for receiving at least a clock signal and a data control signal. The amplifying stage is coupled to the input stage and supplied by a supply voltage and a ground voltage, and is arranged for retaining a data value and outputting the data value according to the clock signal and the data control signal. The clock gating circuit is coupled to the amplifying stage, and is arranged for avoiding a short-circuit current between the supply voltage and the ground voltage.

Abstract: A data output circuit includes a first trigger unit and a signal generation unit. The first trigger unit is inputted with first data in a first mode and a second mode, and outputs the first data in response to a first trigger signal. The signal generation unit, in the first mode, outputs the first trigger signal in response to a first clock signal, and, in the second mode, retains the first trigger signal in a first state regardless of the first clock signal.

Abstract: An interface circuit includes a pre-driver coupled convert a single-ended signal to an intermediate differential signal. An output driver is coupled to convert the intermediate differential signal to an output differential signal having a variable output swing responsive to a mode select signal and a second supply voltage. A replica bias circuit is coupled to receive a first supply voltage, the mode select signal, and an open termination enable signal to generate a bias signal. An internal regulator is coupled to receive the bias signal and the first supply voltage to supply the second voltage to the output driver in response to the bias signal. An open termination circuit is coupled to an output of the output driver, and is coupled to receive the open termination enable signal to couple an internal load to the output of the output driver in response to the open termination enable signal.

Abstract: The invention relates to a circuit including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors being a multiple gate transistor having at least a first (G1P, G1N) and a second (G2P, G2N) independent control gates, characterized in that at least one of the transistors is configured for operating in a depletion mode under the action of a second gate signal applied to its second control gate (G2p, G2N).

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract: Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.

Abstract: A power amplifier includes a plurality of power amplification modules, each of which includes an input terminal and an output terminal. Equivalent input impedances seen respectively into the power amplification modules from the input terminals thereof are the same, and equivalent output impedances seen respectively into the power amplification modules from the output terminals thereof are the same. The input terminals of the power amplification modules are coupled together for receiving an input signal. The output terminals of the power amplification modules are coupled together for outputting an output signal. Each of the power amplification modules amplifies a portion of a power of the input signal to obtain a portion of a power of the output signal.

Abstract: A semiconductor device has a small area and constitutes a CMOS 3-input NOR circuit by using surrounding gate transistors (SGTs) which are vertical transistors. In the 3-input NOR circuit including six MOS transistors arranged in a line, the MOS transistors constituting the NOR circuit have the following configuration: Planar silicon layers are disposed on a substrate. The drain, the gate, and the source of the MOS transistors are arranged in a vertical direction, and the gate surrounds a silicon pillar. The planar silicon layers include a first active region having a first conductivity type and a second active region having a second conductivity type. The first and second active regions are connected to each other via a silicide layer disposed on surfaces of the planar silicon layers. In this way, a semiconductor device constituting a NOR circuit with a small area is provided.

Abstract: The embodiments of the present invention provide a driving circuit and a driving method, a GOA unit, a GOA circuit and a display device, to improve the response speed of the circuit and reduce the leakage current. This driving circuit comprises: at least one pull-up/pull-down unit each configured to pull up or pull down a voltage of a controlled node; each pull-up/pull-down unit comprises at least one double-gate transistor, the double-gate transistor is used to accelerate the charge or discharge of the node when being turned on, or is used to reduce the leakage current passing the node when being turned off. The embodiments of the present invention are suitable to be applied to the display production.

Abstract: A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.

Abstract: In accordance with one embodiment, a circuit arrangement is provided including a circuit having a first terminal for a first supply potential and a second terminal for a second supply potential, wherein the first terminal is coupled to the first supply potential; a switch, by means of which the second terminal can be coupled to the second supply potential; a voltage source coupled to the second terminal; and a control device designed to open the switch in reaction to receiving a turn-off signal in an operating mode in which the switch is closed, and subsequently to control the voltage source in such a way that it varies the potential of the second terminal in the direction of the first supply potential.

Abstract: A logic circuit is provided which can hold a switching state of the logic circuit even when a power supply potential is not supplied, has short start-up time of a logic block after the power is supplied, can operate with low power consumption, and can easily switch between a NAND circuit and a NOR circuit. Switching between a NAND circuit and a NOR circuit is achieved by switching a charge holding state at a node through a transistor including an oxide semiconductor. With the use of an oxide semiconductor material which is a wide bandgap semiconductor for the transistor, the off-state current of the transistor can be sufficiently reduced; thus, the state of charge held at the node can be non-volatile.

Abstract: A low-power semiconductor device is provided. A memory device applicable to a multi-context programmable logic device (PLD) includes at least memory cells the number of which is the same as the number of contexts. Output nodes of the memory cells are electrically connected to an output node of a configuration memory through different path transistors. A circuit including a transistor and a capacitor makes a gate potential of the path transistor higher than a high-level potential. This prevents a decrease in the potential of the output node of the configuration memory due to the threshold voltage of the path transistor without an increase in power consumption.

Abstract: Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.

Abstract: A method of measuring a negative voltage using a device including a first transistor and a second transistor is provided. The first transistor is coupled to the second transistor and the negative voltage is supplied to a gate of the second transistor. A plurality of voltages are provided to a source input of the device. For each voltage of the plurality of voltages, whether a first voltage across the first transistor is equivalent to a second voltage across the second transistor is determined, and, when the first voltage across the first transistor is equivalent to the second voltage across the second transistor, the negative voltage is determined by measuring a magnitude of a positive voltage of the device.

Abstract: Embodiments of the invention are generally directed to a configurable single-ended driver. An embodiment of an apparatus includes an interface with a channel; and a single-ended driver to drive a signal on the channel, wherein the driver includes a mechanism to configure a termination resistance of the driver, configure a voltage swing of the driver, and configure a signal response of the driver.

Abstract: A high voltage driver may include: a low side switching unit including first to n-th N-channel metal oxide semiconductor (NMOS) transistors; a high side switching unit including first and second to n-th P-channel MOS (PMOS) transistors; a voltage dividing unit dividing a voltage between the output terminal and the ground; a first constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the first to n-th NMOS transistors; a second constant voltage unit providing a constant voltage and a unidirectional signal path between a source and a gate of each of the first to n-th PMOS transistors; a first charging unit providing a charged voltage to each of the gates of the second to n-th NMOS transistors; and a second charging unit providing a charged voltage to each of the gates of the second to n-th PMOS transistors.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and outputs a signal at a node. The second inverter receives a second input signal and outputs an inverted second input signal at the same node. The current source provides current to the node via a first switch, the first switch receiving an input at a first input where the voltage output swing at the node is larger than a power supply voltage applied to the current source.

Abstract: A method comprises identifying a number of power domains in a device, connecting the power domains to each other by a number of control devices during a wake-up mode of the device, and disconnecting the power domains after the wake-up mode of the device.

Abstract: A Static Sleep Convention Logic (SSCL) circuit. The circuit improves upon Multi-Threshold NULL Convention Logic (MTNCL), disclosed in U.S. Pat. No. 7,977,972, by utilizing the SECRII architecture along with the Bit-Wise MTNCL technique, to produce a new SSCL gate without an nsleep input, which yields a smaller and faster circuit that utilizes less energy per operation than the patented SMTNCL gate design, while only very slightly increasing leakage power during sleep mode.

Abstract: AC powered logic circuits and systems including same are disclosed. According to one aspect, a system including a logic circuit powered using an alternating current (AC) power source includes at least one supply transistor connected to receive voltages of opposite phases from an AC power source such that the at least one supply transistor is strongly on during a first phase of the voltage of the AC power source and is strongly off during a second phase opposite the first phase of the voltage of the AC power source and at least one logic circuit connected to be powered by the AC power source through the at least one supply transistor and producing an output at an output terminal responsive to an input received at an input terminal.

Abstract: A low power inverter circuit includes first and second transistors that receive an input signal at their gate terminals. The first and second transistors are connected by way of their source terminals to third and fourth transistors, respectively. The third and fourth transistors are connected in parallel with fifth and sixth transistors, respectively. The third and fourth transistors are continuously switched on, and the fifth and sixth transistors are controlled in such a way to reduce short circuit current flowing through the first and second transistors when the input signal transitions from one state to another.

Abstract: A digital cell for performing a logic operation on a logic input to produce a logic output, includes an evaluation block and a sense-amplifier block, both configured to receive input signals representative of the logic input, and to detect when the logic input and/or input signals validly encode at least one bit. The digital cell is configured to alternate between an evaluate state and a reset state. Upon the digital cell being in the reset state and the detection, the digital cell is switched from the reset state to the evaluate state in which the evaluation block generates a difference in its output signals, and the sense-amplifier block amplifies the difference so that the output signals encode at least one valid bit. Upon the digital cell being in the evaluate state, the digital cell can be triggered to reset to the reset state.

Abstract: A system includes an inverter element to gate forward current flow from a first signal source, and a reverse current inhibition element to block reverse current flow towards the first signal source from a second signal source.

Abstract: An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level.

Abstract: A fast dynamic register including a data block, a precharge circuit, a transparent latch, and an output logic gate. The precharge circuit precharges first and second precharge nodes and then releases the first precharge node in response to a clock. The data block evaluates data by either pulling the first precharge node low in response to the clock or does not pull it low, in which case the second precharge node is discharged. The transparent latch passes a state of the second precharge node to a store node when transparent, and otherwise latches the store node. The output logic gate drives an output node to a state based on states of the second precharge node and the store node. The transparent latch may be implemented with relatively small devices to reduce size and power consumption to improve efficiency.

Abstract: A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances.

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract: A reversible, switched capacitor voltage conversion apparatus includes a plurality of individual unit cells coupled to one another in stages, with each unit cell comprising multiple sets of inverter devices arranged in a stacked configuration, such that each set of inverter devices operates in separate voltage domains wherein outputs of inverter devices in adjacent voltage domains are capacitively coupled to one another such that a first terminal of a capacitor is coupled to an output of a first inverter device in a first voltage domain, and a second terminal of the capacitor is coupled to an output of a second inverter in a second voltage domain; and wherein, for both the first and second voltage domains, outputs of at least one of the plurality of individual unit cells serve as corresponding inputs for at least another one of the plurality of individual unit cells.

Abstract: An inverter and an antenna circuit. The inverter that receives control signals including a first control signal, a second control signal, and a third control signal, inverts the first control signal, and outputs the inverted first control signal, includes: a first MOS transistor having a gate to which the first control signal is applied and a source that is grounded; a second MOS transistor having a gate to which the third control signal is applied and a source to which the second control signal is applied; and a third MOS transistor having a gate to which the second control signal is applied and a source to which the third control signal is applied, wherein drains of the first MOS transistor, the second MOS transistor, and the third MOS transistor are connected to an output terminal.

Abstract: The present invention provides a data latch circuit which can operate stably with a low-amplitude signal, which consumes less electric power, and which is resistant against the variation in TFTs. When an analog switch is turned on, a data signal is inputted to a gate electrode of an n-channel TFT and, at this time, VDD is supplied to an input terminal of an inverter. When the analog switch in turned off, the n-channel TFT is turned on or off depending on a level of the data signal. When the data signal is at an H level, the n-channel TFT is turned on and VSS is supplied to the input terminal of the inverter. When the data signal is at an L level, VDD is supplied to an input terminal of the inverter. Therefore, only VDD and VSS levels are applied to the input terminal of the inverter.

Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

Abstract: An improved LED provides power efficient lighting while accepting a wide range of input voltages. The improved LED may comprise a controller that may measure a voltage, current, or other characteristics of input power and modify operation of the improved LED accordingly, such as to accept significantly more voltage or significantly less voltage while providing consistent light output. This allows light bulbs or other lighting to be easily manufactured with the improved LED. The improved LED may comprise the controller and one or more LED dies enclosed by a substrate and lens structure. Depending on the configuration of the controller, the improved LED may also provide time, temperature, and other measurement/response functions to help ensure consistent light output.

Abstract: A multi-threshold null convention logic circuit. The circuit includes a first circuit, a first high-threshold transistor coupled to Vcc, and an inverter receiving power from the first high-threshold transistor, driven by the first circuit, and including an output.