Abstract: The present invention includes a driving circuit and method for driving signals. An input signal is received by the driving circuit on an input signal line which is connected to a bias circuit for a common voltage level. Two output lines from the driving circuit are driven to the receiver which is capable of using differential output lines or a selected single ended output line. Furthermore, the output lines may be driven to a high impedance selected by the voltage level of the input signal. The receiver of the output lines may be a SCSI device using multimode terminators which include low voltage differential and a single ended mode.

Abstract: A device for reducing the electromagnetic emission in integrated circuits having driver stages reduces the electromagnetic emission of an integrated circuit without requiring an increase in the blocking capacitance in the process. This is achieved by combining driver stages which do not switch simultaneously to form driver groups, and special wiring of a plurality of blocking capacitors.

Abstract: An input/output (I/O) port designed for electrical interconnection with multiple similar ports includes an input read circuit, an output drive circuit, and a circuit to control the port for input or output mode by electrically disconnecting the output drive circuit from the port. Also included is a back drive current protection circuit placed in series in between an external I/O line and the input read and output drive circuits which blocks backdrive currents from other active processors when the processor that includes the protection circuit is in a powered down state while still allowing full input/output functionality in a powered up state.

Abstract: A gate driver includes an edge detection circuit, an ON pulse generation circuit, first and second OFF pulse generation circuit and a status hold circuit. The first OFF pulse generation circuit generates a first OFF pulse in response to a leading or trailing edge of a control input signal, which is detected by the edge detection circuit. The status hold circuit drives an output element in response to the ON pulse outputted from the ON pulse generation circuit and holds driving status of the output element until a first OFF pulse is outputted from the first OFF pulse generation circuit. The second OFF pulse generation circuit generates a second OFF pulse in response to a protect operation signal and supplies this pulse to the status hold circuit, thereby to stop driving of the output element.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A signal transmission device which transmits n-bit parallel digital signals through an I/O driver to minimize simultaneous switching noise in an integrated circuit chip is proposed. The signal transmission device includes an encoder coupled to the I/O driver which receives the n-bit parallel digital signals and performs an encoding operation to the n-bit parallel digital signals to provide encoded m-bit parallel digital signals for the I/O driver, where m>n and the encoding operation is performed by a rule that the number of logic-1 bits of the encoded m-bit parallel digital signals is maintained at p and the number of logic-0 bits of the encoded m-bit parallel digital signals is maintained at (m−p), where Cpm>2n and m>p>0, and a decoder coupled to the I/O driver which receives the encoded m-bit parallel digital signals and performs a decoding operation to the encoded m-bit parallel digital signals to restore the n-bit parallel digital signals.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: A loss of signal condition is evaluated for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. Two hysteresis modes are used to ensure the hysteresis at low LOS threshold levels is sufficient. The first mode uses hysteresis for the signal strength threshold level that is proportional to the LOS threshold level when the LOS threshold level is above a predetermined level. The second mode employs fixed hysteresis for the signal strength threshold level when the LOS threshold level is below the predetermined level. The hysteresis provides a signal strength threshold level that has a greater magnitude on deassertion of a loss of signal indication than on assertion of the loss of signal indication.

Abstract: An apparatus including first and second devices, at least one connection between an input of the second device and an output of the first device, and at least one resistor in series between the connection and the input of the second device. The series resistor, acting as a type of end termination, positively alters the waveforms of the signals input to the second device. In particular, glitches and ringing after the input pin package or at the input of the second device (at the gate for a CMOS transistor) are reduced. Overshoots and undershoots are also reduced. As a result, the input signals are usable and the interface between the first and second devices operates correctly. Further, the setup procedure of the valid logic level of the input signal can be accomplished much more quickly and is much more stable. The series resistor also consumes very little extra power.

Abstract: As the signal lines, such as the data bus, become longer, signal delay occurs due to the resistance and capacitance components of that bus. In order to minimize the effect due to this delay, the processing module is designed in consideration of the delay time. An interface circuit 13 is provided in the bus to control the signal transfer. Data and so forth sent from the central processing unit is supplied directly to the extended bus without being delayed in the interface circuit. Data signals and so forth transferred to the central processing unit 11 is delayed for a predetermined time in the latch 25 of the interface circuit before being sent to the central processing unit. Because only the data signal to be sent to the central processing unit is latched, the size of the interface circuit can be minimized.

Abstract: In an electronic system having first and second logic devices, a free running on-chip clock signal is generated by the first logic device, where the signal has a frequency that is controlled to match that of a global free-running clock signal received by both devices. The on-chip clock signal is synchronized to a strobe signal received by the first device and that was transmitted in association with a data signal by the second device. A logic function is repeatedly performed as synchronized by the first clock signal, to repeatedly generate one or more bits from the data signal.

Abstract: A circuit for detecting ground bounce and for using the detection information to reduce data error resulting therefrom is described. In one embodiment, an on-chip ground bounce detector circuit detects large ground bounce events caused by the simultaneous switching of I/O buffers of the chip and notifies an on-chip logic circuit of the event. The on-chip logic circuit can be implemented to take a variety of actions upon receipt of notification from the detection circuit that a ground bounce has been detected.

Abstract: A slope control device for an electric data transmission system having a first line and a second line for differentially transmitting binary data pulses in such a manner that a first logic value of the data pulses has a high potential on the first line and a low potential on the second line associated therewith and a second logic value of the data pulses has a low potential on the first line and a high potential on the second line associated therewith, said slope control device being designed such that it regulates the slope steepness of the potential curve of a first one of both lines to a desired value; compares the slope steepness of the potential curve on one line to the slope steepness of the potential curve on the other line; and compares the slope steepness of the potential curve of the second line as a function of the comparison result.

Abstract: In a system, such as an open-drain bus architecture system, a termination impedance can be dynamically coupled or de-coupled from a bus. The termination impedance is coupled to the bus by a dynamic control circuit if a signal is being received from the bus or if a binary 1 is driven on the bus. The termination impedance is de-coupled from the bus by the dynamic control circuit if a binary 0 is driven on the bus. Coupling the termination impedance to the bus improves signal quality by providing a matching impedance. De-coupling the termination impedance reduces power dissipation and improves receiver noise margin.

Abstract: Disclosed is a system for reducing propagation delays caused by capacitive coupling of RC interconnects. The system comprises a first interconnect utilized for propagating signals, a second interconnect also utilized for propagating signals but which propagates signals at a faster rate than the first interconnect, and a charge dumping circuit with an input coupled to a point on the second interconnect and an output coupled to a corresponding point on the first interconnect. The charge dumping circuit includes a pulse generation circuit and a select-signal generation circuit, both of which are utilized to enable charge to be dumped from the second interconnect to the first interconnect to increase switching times of the signals propagating on the first interconnect and improve overall propagation speed.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level.

Abstract: A connection control circuit is provided to guarantee a high quality of port-to-port connection service by enabling to maintain the suspended state even when a disparity exists in the pulse widths of the envelope signals of the tone signals between the sender and receiver, exemplified by a receiver tone pulse width being wider than a sender tone pulse width. Connection control is achieved by providing a signal correction circuit between the receiver circuit of a port that receives incoming signals from an opposing port through a transmission line and a connection state managing machine that manages connection between the ports. The signal correction circuit corrects the tone pulse width of an envelope-signal generated from the incoming tone signal by broadening the pulse width so as to conform to a tone signal having the pulse width specified by own connection state managing machine.

Abstract: In some embodiments, the invention includes a soft error resistant latch circuit. The latch circuit includes a storage node, a feedback node, and an inverter between the storage node and the feedback node. The latch circuit also includes split connection storage node drivers and split connection feedback node drivers each connected to the storage node and the feedback node. In some embodiments, the invention includes a soft error resistant domino circuit a domino node, a keeper node, and a soft error resistant keeper. The soft error resistant keeper includes (a) a FET having a gate connected to the keeper node; (b) a FET having a gate connected to the domino node; and (c) an inverter between the domino and keeper nodes. In some embodiments, the invention includes a soft error resistant domino circuit having a domino node, a keeper node, and an inverter between the domino and keeper nodes. The circuit also includes reverse connection keeper drivers connected between the domino node and the keeper node.

Abstract: A repeater employs multiple threshold detectors to distinguish between signals from external devices and signals generated within the repeater. Signals that are sent from the repeater are configured to be between two threshold levels, so that a detector at one threshold level will detect an active signal, but the detector at the other threshold level will not detect an active signal. When an external signal is received on one side (A) of the repeater, it is propagated to the other side (B) of the repeater, and at the same time, the other side (B) of the repeater is configured to only propagate external signals back to the first side (A). In this manner, the internally generated signal from one side (A) is not propagated back to the same side (A), and a latch-up is avoided. In like manner, when an external signal is received at the other side (B), the first side (A) of the repeater is configured to propagate only externally generated signals.

Abstract: A signal level adjusting circuit includes a first amplifying stage in which output electrodes of output stage transistors are connected to ground through current supplies and are connected with respective output terminals, and a DC voltage at the output terminals has a first voltage value; a second amplifying stage in which control electrodes of input stage transistors are connected with respective input terminals, and a DC voltage at the input terminals has a second voltage value; and a coupling stage, connected between the output terminals and the input terminals, which includes at least one series resistor. The first amplifying stage is incorporated in a bipolar IC, and the second amplifying stage is incorporated in a CMOS IC.

Abstract: A glitch removal circuit is disclosed that removes negative glitches from those signals that are provided to circuit elements that are turned-on by negative glitches (e.g., p-channel transistors), and/or removes positive glitches from those signals that are provided to circuit elements that are turned on by positive glitches (e.g., n-channel transistors). The positive glitches need not be removed from those signals that are provided to the circuit elements that are turned-off by positive glitches (e.g., p-channel transistors), and the negative glitches need not be removed from those signals that are provided to circuit elements that are turned-off by negative glitches (e.g., n-channel transistors). An advantage of the present invention is that both positive and negative glitches can be removed in parallel, rather then serially. This can significantly increase the performance of some circuits, and may reduce the amount of glitch removal circuitry required.

Abstract: A method and apparatus for an impedance control system for a center tapped termination bus. One method of the present invention comprises comparing an output potential of a buffer with a pair of reference potentials. The output impedance of the buffer is adjusted to cause the buffer output voltage swing to match the reference potentials.

Abstract: A method and device to emulate impedances includes a pair of impedances connected in series between a supply voltage and ground, the impedances forming a voltage divider having at its midpoint a reference voltage Vx. An OP AMP includes a positive input connected to the Vx node and the negative input connected to the output thereof in a direct feedback loop. The OP AMP output is also connected to a load impedance that is connected either to the supply voltage or ground. The unity gain OP AMP forces the output voltage thereof to follow the input voltage Vx, whereby the output voltage behaves as if it were created by a virtual impedance. By proper choice of components and values, the virtual impedance may comprise a large capacitor, and the remaining impedances may comprise resistance and small capacitance, both of which, together with the OP AMP, are easily integrated in a small die area.

Abstract: An approach to reduce noise associated with ground bounce in integrated circuits containing CMOS gates and drivers is provided. Typical CMOS gates and drivers consist of complementary pairs of MOS gates. As the CMOS driver input transitions from high to low or low to high, there is a brief period during which both gates of a CMOS are conductive. When both gates are on, voltage and/or current spikes can occur from a variety of sources, including parasitic inductance between the gate and its external power supply. Disruptions, bounces, and sinks in voltage and/or current can create noise which can be propagated throughout a chip, potentially resulting in operational errors. The present invention adds a high and low reference voltage and two or more pairs of CMOS gates to each gate's circuit to dynamically add charge and/or draw charge from the CMOS gate as needed to reduce ground bounce and noise.

Abstract: A signal line drive circuit for a semiconductor device includes a first driver having an input for receiving an input signal and an output, a second driver having an input connected to the output of the first driver and an output connected to a signal line, and a third driver having an input connected to the output of the first driver and an output connected to a point of the signal line. The point of the signal line is spaced from the output of the second driver such that a first load is present between the output of the second driver and the point of the signal line, and such that a second load is present between the point of the signal line and an output of the signal line. The first, second and third drivers each include at least one inverting buffer. The drive circuit reduces a delay time of a signal transmitted through the signal line, and improves the voltage-time slope of the transmitted signal.

Abstract: An apparatus for extending USB linkage between a host computer and a peripheral unit includes a first extender port, a second extender port, a first extender cable connected to transmit signals from the first to the second port, and a second extender cable connected to transmit signals from the second port to the first, such that outgoing USB signals from each port are identical to incoming USB signals into the other port. Each port is formed of a driver circuit connected to one extender cable, a receiver circuit connected to the other cable, and an interface circuit including a USB transceiver connected by USB cable to the transceiver of the host or peripheral. A logic device connected between the circuits selectively effects outgoing signals on a USB or extender cable. The extender cables are bundled in a combined cable that includes a power line and a line for speed signals.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: The present invention relates to an output buffer circuit for transmitting digital signals over a transmission line with pre-emphase. It comprises an output stage and a control circuit. The output stage includes a first impedance circuit connected between an upper power supply potential and an output node. It furthermore includes a second impedance circuit connected between the output node and a power supply node at a lower supply potential. Both impedance circuits receive impedance control signals from the control circuit such that an impedance ratio between the first impedance and the second impedance takes one of at least three different predetermined values in accordance with the present state and the history of a digital data input signal, and such that the sum of the conductance provided by the first impedance circuit and the conductance provided by the second impedance circuit is independent from the generated impedance ratios.

Abstract: A line receiver circuit is provided with a buffer section having an input for connection to a transmission line, and with a termination impedance section comprising a plurality of interconnected termination impedance elements for terminating the characteristic impedance of the transmission line. The circuit is further provided with a twin impedance section which is operable over a specified voltage range and comprises twin impedance elements, each corresponding to one of the termination impedance elements. A control section couples control signals to each of the twin impedance elements in order to maintain linear operation of the termination impedance section, as voltage level varies over the specified voltage range.

Abstract: A circuit arrangement which, in accordance with its mode of control, operates either as input circuit or as output circuit and includes a series connection with an inverter stage, a filter stage, a cross-current avoiding stage, a switching-on voltage reducing stage, a switch stage, an output driver stage, and a Miller feedback stage, which are configured in the mode of operation as an output circuit, and parallel thereto a Schmitt trigger and an analog switch that can become effective in the mode of operation as input circuit.

Abstract: A circuit to reduce erroneous signal glitches in the presence of overshoot and undershoot signals includes an output node and an input node to alternately receive overshoot and undershoot signals. A noise-vulnerable transistor is connected to the input node. An output isolation transistor is connected between the noise-vulnerable transistor and the output node. A pull-up transistor controls the charge state at a control node between the noise-vulnerable transistor and the isolation transistor, such that if the overshoot and undershoot signals cause the noise-vulnerable transistor to turn-on, the pull-up transistor establishes a charge state at the control node that keeps the output isolation transistor off and therefore isolates the output node from erroneous signal glitches.

Abstract: A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. A resynchronization circuit allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation so that each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. Redundant memory modules are included to replace defective memory modules, and replacement can be carried out through commands on the DASS bus.

Abstract: This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks.

Abstract: A low voltage CMOS bus switch (20) adapted to connect to a 5V bus (A,B) in a controlled and power-efficient manner. A voltage reference circuit (30) monitors the state of the power supply (Vcc) and provides three control signals (Dref, Dref2, Dref3) when the supply (Vcc) is powered up or down. These control signals help to keep the switch open when the supply is powered down, and are used in the 5V tolerant circuitry to bias the gates of the pass transistors (MN1,MP1) when the supply is powered up. When the bus voltages are below Vcc, the device operates as a normal low voltage bus switch. As the input voltage increases above Vcc, a P-channel pass transistor (MR1) turns off and a gate voltage of a N-channel pass transistor (MN1) is controlled by the tolerant circuitry. This provides a reliable output signal to either a 3.3V or 5V bus.

Abstract: A logic isolation circuit has a transmitter circuit for receiving a logic input signal and providing a periodic signal to an isolation barrier, and a receiving circuit for receiving the periodic signal from the isolation barrier and for providing an output signal that indicates the transitions in the logical input signal.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A terminator circuit for connection to a network can be fabricated and used within CMOS-SOI (complementary metal oxide semiconductor—silicon on insulator) for carrying small logic level signals for connecting data from a network's first circuit to a network's second circuit in which a network's input terminal connects a terminator circuit to the network's second circuit to act as a terminator on the data line passing data from said first circuit to said second circuit. The terminator circuit has a reference circuit coupled to a terminal circuit. The reference circuit has SOI devices back to back source coupled CMOS-SOI devices to each other for a tuned center reference voltage node, with their bodies connect to upper and lower level power supplies respectively. An upper level power source is connected to one side of the reference voltage node and a lower reference voltage power source is connected to the other side of the reference voltage node.

Abstract: A circuit for bidirectionally exchanging data includes a plurality of entities electrically connected therebetween by a bus, the plurality of entities for sending and receiving data to each other. An at least one swapper circuit is electrically connected to the bus at a connection point between the plurality of entities. The at least one swapper circuit includes means for timing data transfer between a send data mode and a receive data mode and sending and receiving data during the respective modes. The at least one swapper circuit includes a routing means for receiving data simultaneously from the plurality of entities and then sending data simultaneously to the plurality of entities without colliding data.

Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.

Abstract: A data input buffer circuit is disclosed.

Abstract: An input/output buffer capable of supporting multiple transmission logic bus specifications. The input/output buffer has a coordinating controller, a logic control circuit, a first transistor, a second transistor, a first resistor element, and a second resistor element. The logic control circuit picks up a microprocessor-type signal to determine the type of microprocessors used. According to the microprocessor type, conductivity of the first transistor, the second transistor, the first resistor element and the second resistor element are reassigned to fit the particular logic bus specification of the microprocessor. Hence, a single chipset on a main circuit board is able to accommodate various types of microprocessors.

Abstract: A dual mode I/O interface circuit compatible with either GTL logic signals or traditional CMOS logic signals comprises a connection node with a differential sense amplifier having one input coupled to the connection node, and the other input coupled to a reference voltage. Pull-up and pull-down circuits are coupled to the connection node. Logic circuitry is coupled to the gate of the at least one P-type field-effect transistor of the pull-up circuit, and the gate of the at least one N-type field-effect transistor of the pull-down circuit to control the conductivity of the field-effect transistors. In this manner, a first representation of the input signal compatible with GTL logic signals as provided at the connection node when the mode signal is asserted, and a second representation of the input signal compatible with CMOS logic levels as provided at the connection node when the mode signal is deasserted.

Abstract: Transmission between two cards is disabled if power is not supplied to one of the cards. The system includes a first card generating a first power signal based on power applied to the first card. A second card, in communication with the first card, generates a second power signal based on power applied to the second card. A transmitter on the first card transmits to a receiver on the second card. The transmitter is disabled from transmitting based on the second power signal and the receiver is disabled from receiving based on the first power signal.

Abstract: An integrated circuit having an apparatus for automatically adjusting noise immunity is disclosed. The integrated circuit includes multiple functional logic circuits, a clock generator, a group of noise monitor circuits, and a control logic circuit. The clock generator generates a clock signal to all these circuits. The noise monitor circuits are utilized to detect noise occurring in the integrated circuit. In response to any noise detected by the noise monitor circuits, the control logic circuit decreases the speed of the clock signal sent to all the circuits, especially the functional logic circuits, via a slow down signal to the clock generator. Alternatively, the control logic circuit can inform the functional logic circuits via a noise alert signal to increase the noise immunity of certain noise sensitive circuits within the functional logic circuits.

Abstract: A bus circuit of the present invention includes a first circuit connected to a first power supply, a second circuit connected to a second power supply, a transmission line which connects the first and second circuits and a third circuit. The third circuit prevents current from flowing between the first and second power supplies through the transmission line for a predetermined period after the first power supply is applied. Another bus circuit of the present invention includes a transmission line, a first circuit which is connected to a first power supply and outputs a signal to the transmission line, a second circuit which is connected to a second power supply and receives the signal output by the first circuit through the transmission line, and a third circuit which is provided between the transmission line and the first circuit and which prevents the signal from transmitting from the first circuit to the transmission line for a predetermined period after the first power supply is applied.

Abstract: Disclosed is a data output buffer improving the drivability, by increasing the power supply voltage and keeping the power supply voltage constant, without being modification and increase of the manufacturing process of the device. Furthermore, the improvement of the drivability may increase the speed of the data output buffer and decrease the chip area.

Abstract: Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL, and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level.

Abstract: A signal transmitter for transmitting digital logic signals and a complementary receiver, are disclosed. The signal transmitter comprises a plurality of signal drivers and at least one reference driver. The signal drivers transmit digital signals, while the reference driver transmits a constant signal representative of a digital HI or LO. The signal and reference drivers are interconnected so that any noise due to package and power supply interconnection impedances is present in all transmitted signals including any reference signals. At a receiver, the reference signal including noise is used to establish threshold levels for digital HI and LO signals. Because noise is common to all transmitted signals, the receiver is able to reduce the effects of the noise by comparing the plurality of received signals with the reference signal.

Abstract: Offers a circuit that reduces or removes crosstalk with a method that does not exert influence on improvements in miniaturization and the degree of integration. The crosstalk prevention circuit, between at least two signal lines that are formed almost in parallel, for example, a master clock line and a slave clock line 11, 12, makes a third signal line 13 that applies a signal when a signal is not applied to at least one of these two signal lines, for example, a test signal, and becomes in a grounded condition when a signal is applied to the above-mentioned two signal lines. Preferably, a driver circuit is connected to the third signal line, and the ratio of the current drive capabilities of the N channel transistor and the P channel transistor of the output transistors of said driver circuit is made about 2:1.