Signal Sensitivity Or Transmission Integrity Patents (Class 326/21)
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Patent number: 7710187Abstract: A gate drive circuit includes a turn-on side circuit for turning on a gate of a power switching device, the turn-on side circuit including a first turn-on side power supply circuit and a second turn-on side power supply circuit, the first turn-on side power supply circuit including: a first turn-on voltage source for supplying a first turn-on voltage; first turn-on wiring; and a first turn-on switch connected in the first turn-on wiring and controlled by a gate drive signal; and the second turn-on side power supply circuit including: a second turn-on voltage source for supplying a second turn-on voltage applied to the gate of the power switching device to set the power switching device in a steady (on) state; second turn-on wiring; a second turn-on switch connected in the second turn-on wiring; and a turn-on side delay circuit for delaying the gate drive signal and passing it to the second turn-on switch.Type: GrantFiled: February 7, 2008Date of Patent: May 4, 2010Assignee: Mitsubishi Electric CorporationInventor: Kazuaki Hiyama
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Patent number: 7701262Abstract: A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.Type: GrantFiled: July 23, 2007Date of Patent: April 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Chi Won Kim, Ji Young Kim, Myoung Bo Kwak, Jong Shin Shin, Seung Hee Yang, Hyun-Goo Kim, Jae Hyun Park
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Patent number: 7692444Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.Type: GrantFiled: July 6, 2006Date of Patent: April 6, 2010Assignee: Analog Devices, Inc.Inventors: Baoxing Chen, Geoffrey Haigh
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Patent number: 7688104Abstract: An on-die termination (ODT) control in a semiconductor memory device compensates for a change in an external voltage. The on-die termination device includes a voltage comparator that compares an external voltage to a set internal reference voltage. The compared values are sent to a controller that controls an on-die termination impedance value according to the output signal from the voltage comparator. Based on the output of the controller, the present invention spontaneously controls an on-die termination resistance value according to the change in the external voltage without degrading device characteristics during high-speed operation.Type: GrantFiled: July 2, 2008Date of Patent: March 30, 2010Assignee: Hynix Semiconductor Inc.Inventor: Jung Hoon Park
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Patent number: 7688105Abstract: An impedance matching logic generates code values that define pull-up and pull-down transistors to be enabled with output buffers. The output buffers store the code values using a two-stage latch configuration, such that updated code values are always stored within the output buffer, even if the output buffer is driving an output signal when the updated code values are received. The impedance matching logic uses previously determined code values to shorten the time required to calculate updated code values. The impedance matching logic may be operated in response to a clock signal having a frequency lower than the frequency of the output clock signal used to control the output buffers. The impedance matching logic may adjust the code values by certain percentages using a multiplication function, thereby allowing for design fine tuning (e.g., due to layout mismatch).Type: GrantFiled: July 9, 2008Date of Patent: March 30, 2010Assignee: Integrated Device Technology, Inc.Inventor: Tak Kwong Wong
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Patent number: 7683654Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.Type: GrantFiled: December 27, 2007Date of Patent: March 23, 2010Assignee: Analog Devices, Inc.Inventors: Baoxing Chen, Geoffrey Haigh
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Patent number: 7683656Abstract: Predriver equalization is described. A predriver includes a predriver equalizer to provide equalization on outputs of predrivers. The predriver equalization causes the predrivers to drive the output driver and a preemphasis driver with signals equalized to reduce common mode noise on the output signal. The predrivers can be implemented as complementary semi-differential driver circuits or as complementary logic circuits with weak pull-downs. The driver complexity can be reduced to the use of a semi-differential driver with the use of the predriver equalization.Type: GrantFiled: November 17, 2008Date of Patent: March 23, 2010Assignee: Intel CorporationInventor: Yick Yaw Ho
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Patent number: 7683655Abstract: An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potential to the terminal. It is provided according to an embodiment of the invention that the reference potential means is switchable, particularly by an override process.Type: GrantFiled: January 16, 2008Date of Patent: March 23, 2010Assignee: Atmel Automotive GmbHInventor: Anton Koch
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Patent number: 7675326Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.Type: GrantFiled: June 27, 2008Date of Patent: March 9, 2010Assignee: Altera CorporationInventors: Mei Luo, Sergey Shumarayev, Wilson Wong, Chong H. Lee
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Patent number: 7667485Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.Type: GrantFiled: June 5, 2008Date of Patent: February 23, 2010Assignee: Elpida Memory, Inc.Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
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Publication number: 20100033211Abstract: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.Type: ApplicationFiled: October 13, 2009Publication date: February 11, 2010Inventors: Harry Muljono, Stefan Rusu, Yanmei Tian, Mubeen Atha, David J. Ayers
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Patent number: 7656189Abstract: Various approaches for detection of an unwanted function implemented in an integrated circuit (IC) are described. A controller is implemented on the IC, and at a first time while the IC is operating according to a circuit design, the controller reads a first data set from a subset of memory cells. The subset of memory cells stores state information of the circuit design. The controller determines whether the first data set is different from a second data set. In response to the first data set being different from the second data set, the controller outputs a threat signal that indicates the presence of unauthorized logic in the circuit design.Type: GrantFiled: July 31, 2007Date of Patent: February 2, 2010Assignee: XILINX, Inc.Inventor: Stephen M. Trimberger
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Patent number: 7642807Abstract: A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected.Type: GrantFiled: June 26, 2007Date of Patent: January 5, 2010Assignee: Agere Systems Inc.Inventors: Dipankar Bhattacharya, Gregg R. Harleman, Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris
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Patent number: 7639037Abstract: A system that includes a first buffer and a second buffer, wherein the first buffer and the second buffer are connected to the same input, wherein a size of the first buffer is defined by a distance of the first buffer from the input and a transfer rate of data, wherein a size of the second buffer is defined by a distance of the second buffer from the input and the transfer rate of data, and wherein the distance between the first buffer and the input is different from the distance between the second buffer and the input.Type: GrantFiled: June 27, 2008Date of Patent: December 29, 2009Assignee: Sun Microsystems, Inc.Inventors: Hans Eberle, Nils Gura, Wladyslaw Olesinski, Robert J. Drost, Robert David Hopkins
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Patent number: 7626425Abstract: High performance clock-powered logic runs at below supply levels and reduces the need for faster digital logic circuitry. In a preferred embodiment, a clocked buffer is used to drive the signal line. The receiving end of the line is connected to a jam latch, preferably followed by an n-latch, followed by the digital logic, and followed by a second n-latch. The first n-latch is eliminated in an alternate embodiment, preferably one that uses complementary data signals.Type: GrantFiled: January 13, 2006Date of Patent: December 1, 2009Assignee: University of Southern CaliforniaInventors: William C. Athas, Nestor Tzartzanis, Weihua Mao, Lena Peterson
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Patent number: 7622955Abstract: An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.Type: GrantFiled: April 17, 2008Date of Patent: November 24, 2009Assignee: Texas Instruments IncorporatedInventors: Ramaprasath Vilangudipitchai, Sumanth Katte Gururajarao, Hugh T. Mair, Alice Wang, Uming U. Ko, Sushma Honnavara-Prasad
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Patent number: 7622945Abstract: A method for a mix mode driver to accommodate traces of different lengths includes sequentially shifting values of a data signal to a number of stages and sequentially amplifying the values of the data signal at least one stage. Depending on the length of trace for the data signal, the method further includes providing at least one amplifying coefficient to at least one stage and coupling a subset of the stages to an adder. The method finally includes outputting the data signal from the adder to the trace.Type: GrantFiled: December 20, 2006Date of Patent: November 24, 2009Assignee: 3PAR, Inc.Inventors: Christopher Cheng, David Chu
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Patent number: 7616926Abstract: An integrated circuit containing a communication channel is described. This communication channel includes: a transmit circuit configured to transmit signals; a link coupled to an output of the transmit circuit; a receive circuit coupled to the link; and a clamping circuit coupled to the link. Note that the transmit circuit is capacitively coupled to the receive circuit via the link. Furthermore, the clamping circuit is configured to compensate for leakage current on the link by maintaining a voltage on the link corresponding to a logical “1” or a logical “0.” This voltage is based on a history of the transmitted signals.Type: GrantFiled: December 27, 2006Date of Patent: November 10, 2009Assignee: Sun Microsystems, Inc.Inventor: Robert J. Drost
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Patent number: 7612578Abstract: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.Type: GrantFiled: October 24, 2006Date of Patent: November 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Uk Chang, Dong-Ho Hyun, Seok-Won Hwang
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Publication number: 20090267638Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Applicant: Texas Instruments IncorporatedInventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
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Patent number: 7609091Abstract: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.Type: GrantFiled: September 29, 2005Date of Patent: October 27, 2009Assignee: Intel CorporationInventors: Harry Muljono, Stefan Rusu, Yanmei Tian, Mubeen Atha, David J. Ayers
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Patent number: 7605601Abstract: A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the semiconductor integrated circuit device further comprising a first transistor of a second conductivity type and a second transistor of the second conductivity type, the transistors being connected in series between the second power supply line and a second substrate well provided on the semiconductor substrate.Type: GrantFiled: April 18, 2008Date of Patent: October 20, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Fumihiko Tachibana, Takahiro Yamashita
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Patent number: 7602169Abstract: A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths.Type: GrantFiled: April 24, 2008Date of Patent: October 13, 2009Assignee: Analog Devices, Inc.Inventors: William George John Schofield, Lawrence A. Singer
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Publication number: 20090243649Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: ApplicationFiled: June 8, 2009Publication date: October 1, 2009Inventors: George E. Pax, Roy E. Greeff
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Publication number: 20090237107Abstract: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.Type: ApplicationFiled: March 12, 2009Publication date: September 24, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Bong-Hyun Lee, Jung-Yun Choi, Jae-Han Jeon, Kyung-Tae Do
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Patent number: 7592837Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 19, 2008Date of Patent: September 22, 2009Assignee: MOSAID Technologies CorporationInventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
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Patent number: 7590392Abstract: In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.Type: GrantFiled: October 31, 2005Date of Patent: September 15, 2009Assignee: Intel CorporationInventors: Navindra Navaratnam, Aninda K. Roy
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Patent number: 7579867Abstract: Some embodiments provide a method that outputs from a configurable IC a first set of data bits from a trace buffer. Each bit of the first set of data bits is simultaneously generated in the configurable circuits and, in some embodiments, multiple data bits of the first set of data bits do not reach the traced buffer simultaneously. The method also determines a set of relative delays for the first set of data bits and arranges the first set of data bits into a second set of data bits by compensating for the relative delays.Type: GrantFiled: June 27, 2007Date of Patent: August 25, 2009Assignee: Tabula Inc.Inventors: Brad Hutchings, Steven Teig, Amit Gupta
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Patent number: 7576619Abstract: An integrated circuit arrangement is disclosed. In one embodiment, the integrated circuit arrangement includes an output circuit having at least one first output connection which can provide a data signal, at least one first data output connection; and at least one first inductance connected between the at least one first output connection and the at least one data output connection.Type: GrantFiled: July 11, 2003Date of Patent: August 18, 2009Assignee: Infineon Technologies AGInventors: Daniel Kehrer, Herbert Knapp
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Publication number: 20090201045Abstract: A control signal input circuit for supplying control signals to a plurality of controlled circuits comprises N pieces of control signal preservation/output circuits provided one by one corresponding to plural-bit signals for delivering input data as it is when a trigger signal is at a first level, and holding previously delivered output data when the trigger signal is at a second level, and a controlled circuit selector circuit for setting the trigger signal for S pieces of the control signal preservation/output circuits to the first level, and setting the trigger signal for the rest of the control signal preservation/output circuits to the second level.Type: ApplicationFiled: January 26, 2007Publication date: August 13, 2009Applicant: NEC CORPORATIONInventors: Koichi Nose, Masayuki Mizuno
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Patent number: 7573290Abstract: A data input/output driver for use in a semiconductor memory device includes a data transmitting block for transmitting a data between an inside and an outside of the semiconductor memory device and generating a data driving signal in order to indicate a timing of outputting the data. A reference data generating block generates a reference data. A switching block outputs the reference data in response to the data driving signal. The data and the reference data are combined as an output signal.Type: GrantFiled: February 11, 2005Date of Patent: August 11, 2009Assignee: Hynix Semiconductor Inc.Inventors: Hee-Bok Kang, Jin-Hong Ahn
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Patent number: 7560957Abstract: A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.Type: GrantFiled: June 1, 2006Date of Patent: July 14, 2009Assignee: Agere Systems Inc.Inventors: Jinghong Chen, Gregory W. Sheets, Lane A. Smith
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Patent number: 7560956Abstract: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device.Type: GrantFiled: August 3, 2005Date of Patent: July 14, 2009Assignee: Micron Technology, Inc.Inventor: William C. Waldrop
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Patent number: 7557601Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.Type: GrantFiled: October 9, 2007Date of Patent: July 7, 2009Assignee: Micron Technology, Inc.Inventors: George E. Pax, Roy E. Greeff
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Publication number: 20090153183Abstract: A noise filter circuit includes a first inverter circuit that receives a signal based on an input signal, a second inverter circuit that receives a signal based on the input signal, and a latch circuit that receives signals based on a signal output from the first inverter circuit and a signal based on a signal output from the second inverter circuit as a set signal and a reset signal. Each of the first inverter circuit and the second inverter circuit includes a first-conductivity-type transistor and a second-conductivity-type transistor, the capability of one of the first-conductivity-type transistor and the second-conductivity-type transistor being lower than the capability of the other of the first-conductivity-type transistor and the second-conductivity-type transistor.Type: ApplicationFiled: December 15, 2008Publication date: June 18, 2009Applicant: SEIKO EPSON CORPORATIONInventor: Tadamori SAITO
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Patent number: 7538582Abstract: A test apparatus for testing a device under test is provided. The test apparatus includes a test signal generating section for generating a test signal to be provided to the device under test, a driver circuit for providing the test signal to the device under test and a determination section for determining whether is good or bad of the device under test based on the output signal outputted by the device under test according to the test signal. The driver circuit includes a main driver and a sub-driver for outputting drive signals according to the test signal, respectively, a differentiating circuit for outputting a differentiated signal obtained by differentiating the drive signal outputted by the sub-driver and an adding section for providing a signal having the waveform according to the test signal which is obtained by adding the differentiated signal to the drive signal outputted by the main driver to the device under test.Type: GrantFiled: October 28, 2005Date of Patent: May 26, 2009Assignee: Advantest CorporationInventors: Naoki Matsumoto, Takashi Sekino, Toshiaki Awaji
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Patent number: 7535261Abstract: A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I0+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.Type: GrantFiled: July 26, 2006Date of Patent: May 19, 2009Assignee: Hitachi, Ltd.Inventors: Fumio Yuuki, Hiroki Yamashita
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Patent number: 7535251Abstract: There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.Type: GrantFiled: September 7, 2007Date of Patent: May 19, 2009Assignee: Renesas Technology Corp.Inventors: Chikayoshi Morishima, Tokuya Osawa, Masaru Haraguchi, Yoshihiro Yamashita
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Patent number: 7525339Abstract: A semiconductor memory device for testing whether an ODT circuit is on or off during a data read mode includes an on-die termination (ODT) circuit and an ODT state information output unit. The ODT circuit includes at least one ODT resistor. The ODT state information output unit outputs an ODT state information signal indicating whether the ODT circuit is on or off, in response to an ODT control signal during a data read mode when data is output from memory cells. With a semiconductor memory device and method capable of testing whether an ODT resistor is on or off during a data read mode, it is possible to test whether an ODT circuit is on or off during reading of data.Type: GrantFiled: March 14, 2007Date of Patent: April 28, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hyong-yong Lee
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Publication number: 20090106708Abstract: A design structure for noise suppression. A design structure has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.Type: ApplicationFiled: May 29, 2008Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rafik F. Dagher, Christopher M. Durham, Peter J. Klim
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Publication number: 20090102509Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.Type: ApplicationFiled: October 23, 2007Publication date: April 23, 2009Inventors: Rafik Dagher, Christopher M. Durham, Peter J. Klim
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Patent number: 7514952Abstract: Methods and circuitry for reducing ground bounce and VCC sag effects in integrated circuit (“IC”) devices is provided. In particular, a via-programmable design for I/O circuitry in IC devices is provided. The via-programmable I/O circuitry is used to disconnect I/O pin driver circuitry from and create a substantially direct connection between unused I/O pins and the ground and/or VCC signals of an IC device to reduce ground bounce and VCC sag, respectively.Type: GrantFiled: June 29, 2005Date of Patent: April 7, 2009Assignee: Altera CorporationInventors: Eng H Lee, Kok W Loo
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Publication number: 20090079465Abstract: The present invention aims to make each power shutdown area appropriate. Cell areas each comprising a plurality of core cells arranged therein, and power switches disposed corresponding to the respective cell areas are provided. A plurality of power shutdown areas are respectively formed in units of the core cells. In each power shutdown area, power shutdown is enabled by the power switches corresponding to the power shutdown areas. Thus, the power shutdown areas can be set finely in the core cell units, and the appropriateness of each power shutdown area is achieved. With its appropriateness, a reduction in current consumption at standby is achieved.Type: ApplicationFiled: April 21, 2005Publication date: March 26, 2009Inventors: Toshio Sasaki, Yoshihiko Yasu, Ryo Mori, Koichiro Ishibashi, Yusuke Kanno
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Patent number: 7495465Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.Type: GrantFiled: July 20, 2006Date of Patent: February 24, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Qadeer A. Khan, Sanjay K Wadhwa, Divya Tripathi, Siddhartha Gk, Kulbhushan Misri
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Publication number: 20090045834Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.Type: ApplicationFiled: August 17, 2007Publication date: February 19, 2009Inventor: William D. Farwell
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Patent number: 7479800Abstract: A variable impedance sense (VIS) circuit (600) can detect and store an input offset value inherent in a sensing loop (620 and/or 622). According to a detected input offset polarity, a resulting impedance matching binary code can be adjusted to compensate for error that can be introduced by the input offset. The binary code can also be adjusted to compensate for additional error that can be introduced by dropping a least significant bit (LSB) of the code to reduce noise effects caused by the switching of the LSB.Type: GrantFiled: September 28, 2006Date of Patent: January 20, 2009Assignee: Cypress Semiconductor CorporationInventors: Kalyana C. Vullaganti, Jeffery Scott Hunt
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Publication number: 20090002017Abstract: A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected.Type: ApplicationFiled: June 26, 2007Publication date: January 1, 2009Inventors: Dipankar Bhattacharya, Gregg R. Harleman, Makeshwar Kothandaraman, John C. Kriz, Bernard L. Morris
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Publication number: 20080310246Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.Type: ApplicationFiled: June 12, 2007Publication date: December 18, 2008Inventors: Rajiv V. Joshi, Robert Maurice Houle, Kevin A. Batson
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Publication number: 20080309369Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.Type: ApplicationFiled: June 5, 2008Publication date: December 18, 2008Inventors: Takeshi SAKATA, Kiyoo ITOH, Masashi HORIGUCHI
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Patent number: 7466723Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.Type: GrantFiled: June 29, 2004Date of Patent: December 16, 2008Assignee: Intel CorporationInventors: Kersi H. Vakil, Adarsh Panikkar