With Field-effect Transistor Patents (Class 326/27)
  • Patent number: 12130319
    Abstract: A device that provides high impedance contact pads for an electrostatic charge sensor. The contact pads are shared between the electrostatic charge sensor and drivers. The contact pads are set to a high impedance state by reducing current leakage through the drivers. Compared to electrostatic charge sensor with low impedance contact pads, the electrostatic charge sensor disclosed herein has high sensitivity, and is able to detect weak electrostatic fields.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: October 29, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Massimo Orio
  • Patent number: 12081205
    Abstract: Stabiliser circuits and methods are disclosed, for stabilizing a voltage at a gate driver terminal of a gate-driver for a driven transistor to a one of a high voltage and a low voltage, the stabilizer circuit comprising: a first transistor and a second transistor having respective first and second main terminals and connected in series between the gate voltage terminal and a first reference voltage terminal; and a low-pass filter connected between a control terminal of the first transistor and the gate driver terminal; wherein the first transistor is configured to have a threshold voltage which is less that a threshold voltage of the driven transistor; and the second transistor has a control terminal which is configured to be connected to a voltage which is an oppositive of the voltage at the gate driver terminal.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: September 3, 2024
    Assignee: NXP USA, INC.
    Inventors: Pascal Kamel Abouda, Badr Guendouz, Nicolas Roger Michel Claude Baptistat
  • Patent number: 11888477
    Abstract: An example apparatus includes: an output terminal, pull-down circuitry coupled to the output terminal, the pull-down circuitry including: a resistor with a first resistor terminal and a second resistor terminal, the first resistor terminal coupled to the output terminal, a capacitor with a first capacitor terminal and a second capacitor terminal, the first capacitor terminal coupled to the output terminal, a first transistor coupled to the second resistor terminal, a second transistor coupled to the first transistor and the second resistor terminal, and a third transistor coupled to the second transistor.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ankur Kumar Singh, Kanteti Amar, Rashmi Shahu
  • Patent number: 11816412
    Abstract: A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kumar Lalgudi, Ranjith Kumar, Mohammed Rabiul Islam, Jianyang Xu
  • Patent number: 11742850
    Abstract: According to one embodiment, a data transmission device includes a buffer circuit configured to set a voltage level of a data signal to high or low, a power supply line for supplying a power supply voltage to the buffer circuit, a buffer control circuit configured to control a switching operation of the buffer circuit, a current circuit configured to make a dummy current flow to the power supply line, and a current control circuit configured to control the dummy current based on one of the set voltage level and a transmission timing of the data signal.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventor: Toshihiro Yagi
  • Patent number: 11716084
    Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 1, 2023
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11716085
    Abstract: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: August 1, 2023
    Assignee: Kepler Computing, Inc.
    Inventors: Sasikanth Manipatruni, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Amrita Mathuriya
  • Patent number: 11618672
    Abstract: Devices, systems, and methods for limiting a slew rate of a driven device. In some embodiments, the device for limiting a slew rate of the driven device includes one or more slew rate limiting field-effect transistors (FETS) connected between a first circuit node and a node of the driven device, and a first control circuit. In some embodiments, the one or more first slew rate limiting FETs and the first control circuit are configured to set a rate at which the driven device is charged or discharged. In some embodiments, the first control circuit is within a voltage divider and the current flowing through the voltage divider is proportionally mirrored to the one or more first slew rate limiting FETs wherein the current mirror ratio is selected to ensure that a rate at which a capacitance of the driven device changes over time is below a specified limit.
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: April 4, 2023
    Assignee: AAC Technologies Pte. Ltd.
    Inventors: David Zimlich, Arthur S. Morris, III
  • Patent number: 11606030
    Abstract: There is presented a driver and a corresponding method for driving a p-type power switch. The driver includes a capacitor coupled to a control terminal of the power switch. The driver is configured to apply a control voltage to the control terminal and to connect the control terminal to ground to reduce the control voltage down to a target value to switch the power switch on. When identifying that the control voltage has reached the target value, the driver disconnects the control terminal from ground. The driver may be used in various circuits including switching power converters, audio amplifiers and charge-pump circuits.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: March 14, 2023
    Assignee: Dialog Semiconductor B.V.
    Inventor: Marinus Wilhelmus Kruiskamp
  • Patent number: 11563439
    Abstract: Digital to analog converter generates an analog output corresponding to a digital input by controlling DAC cells using bits of the digital input. The DAC cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the DAC cells may have duty cycle error or mismatches. To compensate for the duty cycle error of a DAC cell, a small amount of charge is injected into a low-impedance node of a DAC cell when the data signal driving the DAC cell transitions, or changes state. The small amount of charge is generated using a capacitive T-network, and the polarity of the charge injected is opposite of the error charge caused by duty cycle error. The opposite amount of charge thus compensates or cancels out the duty cycle error, and duty cycle error present at the output of the DAC cell is reduced.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: January 24, 2023
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Jialin Zhao, Gil Engel, Yunzhi Dong
  • Patent number: 11552626
    Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Junki Taniguchi
  • Patent number: 11531363
    Abstract: Various implementations described herein are related to a device having an output pad that is configured to supply an output pad voltage. The device may include tracking circuitry that is configured to receive a first voltage, receive a second voltage that is different than the first voltage, receive the output pad voltage as a feedback voltage, and provide a first tracking voltage and a second tracking voltage based on the first voltage, the second voltage and the feedback voltage. The device may include output circuitry that is configured to receive the first tracking voltage and the second tracking voltage from the tracking circuitry and provide the output pad voltage to the output pad based on the first tracking voltage and the second tracking voltage.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 20, 2022
    Assignee: Arm Limited
    Inventors: Seshagiri Rao Bogi, Kundan Srivastava
  • Patent number: 11456737
    Abstract: A gate-driving circuit for turning on and off a switch device including a gate terminal coupled to a driving node, a drain terminal coupled to a power node, and a source terminal is provided. The gate-driving circuit includes a driving switch and a voltage control circuit. The driving switch includes a gate terminal coupled to a control node, a drain terminal coupled to the power node, and a source terminal coupled to the driving node. The voltage control circuit is coupled between the control node and the driving node. When a positive pulse is generated at the control node, the voltage control circuit provides the positive pulse to the driving node with a time delay.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: September 27, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Po-Chin Chuang
  • Patent number: 11444445
    Abstract: Analog Front End (AFE) driver or transmitter is used for ESD protection of an input-output (IO) pin, thus reducing ESD diode count and subsequently lowering the pad capacitance to achieve high performance in IO circuits like double data rate (DDR) IO, PCI Express (Peripheral Component Interconnect Express), etc. The channel of active devices that constitute AFE driver are used to connect an IO pad to discharge the ESD current to ground, thus providing an alternative path to ESD current and subsequently reducing the ESD diode count. An additional p-type device (Driver Path Enabler (DPE)) is coupled between the IO pad and a gate terminal of the AFE driver. This additional p-type device triggers the channel of the AFE driver. This p-type device is controlled by an RC based structure which cuts the p-type device off during regular operations when power is ramped-up.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Raj Singh Dua, Sanjay Joshi, Harry Muljono, Balkaran Gill
  • Patent number: 11355165
    Abstract: Methods, systems, and devices are described for adjusting parameters of channel drivers based on temperature when a calibration component is unavailable. A memory device may determine whether a calibration component is available for use by the memory device. If not, the memory device may select an impedance setting for the driver that is based on an operating temperature of the memory device. A device or system may identify a temperature of a memory device, identify that a calibration component is unavailable to adjust a parameter of a driver of a data channel, select a value of the parameter based on the temperature and on identifying that the calibration component is unavailable, adjust the parameter of the driver of the data channel to the selected value, and transmit, by the driver operating using the selected value of the parameter, a signal over the channel.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John David Porter, Suryanarayana B. Tatapudi
  • Patent number: 11336313
    Abstract: A data transmission circuit which is improved to be capable of supporting a data transmission mode appropriate for an interface or an application depending on the selection of an option. The data transmission circuit includes a pre-driver configured to output a first differential driving signal, a second differential driving signal and pre-emphasis control signals by using a first differential data signal, a second differential data signal and option signals; a main driver configured to output a first differential transmission signal and a second differential transmission signal by using the first differential driving signal and the second differential driving signal; and a pre-emphasis driver configured to perform pre-emphasis on the first differential transmission signal and the second differential transmission signal to different amplification degrees in a first mode and a second mode by the pre-emphasis control signals.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 17, 2022
    Assignee: Silicon Works Co., Ltd
    Inventors: Sang Hoon Paik, Jeong Hoon Nam, Yong Hwan Moon
  • Patent number: 11282550
    Abstract: Examples described herein can be used to calibrate resistances provided by pull-up and pull-down circuits in an output driver circuit. A first reference voltage can be determined and applied to set a resistance level of a pull-up circuit to a desired level. A code for activating one or more transistor in the pull-up circuit can be determined against the first reference voltage. For a pull-down circuit, a second reference voltage can be set a resistance level of the pull-down circuit to a desired level. The resistance level of the pull-down circuit can be set to equal to the resistance level of the pull-up circuit. A second code can be set for activating one or more transistor in the pull-down circuit. The first and second reference voltages can be represented by index values. The code and second code can be stored for use by the pull-up circuit and pull-down circuit. Re-calibration of the pull-up and pull-down circuits can be performed to determine codes using the first and second reference voltages.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Luigi Pilolli, Agatino Massimo Maccarrone, Jiawei Chen, Qiang Tang
  • Patent number: 11271557
    Abstract: An adaptive gate driver for a driving a power MOSFET to switch is disclosed. The adaptive gate driver includes a load sense circuit to sense a current through the power MOSFET. A controller coupled to the load sense circuit compares the sensed current to a threshold to determine if the load on the power MOSFET is a normal load or a heavy load. Based on the comparison, the controller controls the gate driver to drive the power MOSFET with a first strength level when a normal load determined and at second strength level when a heavy load is determined. The driving strength in the heavy-load condition is lower than the normal-load condition and by lowering the driving strength of the gate driver during the heavy-load condition a voltage across the power MOSFET may be prevented from exceeding a threshold related to a breakdown condition during a switching period.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 8, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zhiwei Liu, Marc Dagan, Xudong Huang
  • Patent number: 11223350
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsin Yu, Nick Pai, Bo-Ting Chen
  • Patent number: 11171643
    Abstract: A switching circuit can help reduce electrical feedback ringing at a gate terminal of a transistor. The switching circuit can include a transistor circuit to switch an electrical signal and a control circuit to provide an actuation signal to the gate terminal of the transistor device. The switching circuit can also include a booster circuit that is disposed between the control circuit and the gate terminal of the transistor device. The booster circuit can be configured to detect a signal from the control circuit to turn off the transistor device and, responsive to the detected signal, drive a current into the gate terminal of the transistor device for a specified span of time before the transistor device turns off.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 9, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: Martin Murnane
  • Patent number: 11169107
    Abstract: An electronic impedance measurement device: a branch, called measurement branch, including an impedance to be measured (Zm), and; at least one branch, called reference branch, including an impedance (Zr), called reference impedance; electronics, called detection electronics, configured to provide an error signal (Vs) dependent on an algebraic sum of a current (Ir) flowing in the at least one reference branch (104) and of a current (Im) flowing in the measurement branch; and at least one adjustment structure, changing the current (Ir) in at least one of said reference branches in a manner inversely proportional to a control variable (k).
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 9, 2021
    Assignee: FOGALE NANOTECH
    Inventor: Christian Neel
  • Patent number: 11153515
    Abstract: A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 19, 2021
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Shunji Maeda, Junichi Ishibashi, Motoshige Okada
  • Patent number: 11128283
    Abstract: A transmitter may include an emphasis circuit suitable for generating a first pull-down driving signal in response to first data and delayed second data, and generating a first pull-up driving signal in response to second data and delayed first data, wherein the first and second data are a differential pair; a phase skew compensation circuit suitable for compensating for a phase skew between the first pull-up driving signal and the first pull-down driving signal to generate a second pull-up driving signal and a second pull-down driving signal; a pull-up driver suitable for pull-up driving an output node in response to the second pull-up driving signal; and a pull-down driver suitable for pull-down driving the output node in response to the second pull-down driving signal.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11054938
    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner includes a programmable baseline resistor, and a buffer with an input coupled to the programmable baseline resistor and an output coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a touch object proximate to the element.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 6, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Denis Ellis, Kaveh Hosseini, Timothy John Williams, Gabriel Rowe, Roman Ogirko, Brendan Lawton
  • Patent number: 11041910
    Abstract: An electronic device includes a battery for supplying electrical power for operation of the electronic device, an acquisition unit configured to connect to a measuring instrument and acquire measurement data from the measuring instrument, a temperature sensor configured to measure a reference temperature, and a controller configured to correct the measurement data on the basis of the reference temperature. The controller acquires the terminal voltage of the battery and sets a lifespan voltage on the basis of the reference temperature. The lifespan voltage is used as a standard for outputting an alarm encouraging replacement of the battery before the terminal voltage of the battery falls below the voltage necessary for the electronic device to operate. The controller outputs the alarm when the terminal voltage is less than the lifespan voltage.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 22, 2021
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Masayuki Uchida, Ken Kaku
  • Patent number: 11042176
    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-An Chang, Chia-Fu Lee, Yu-Der Chih, Yi-Chun Shih
  • Patent number: 11018664
    Abstract: An integrated circuit that may be employed as a smart switch. The integrated circuit includes a first part of a semiconductor switch coupled between a supply node and an output node and configured to provide a first current path in accordance with a first drive signal. The integrated circuit further includes a second part of the semiconductor switch coupled between the supply node and the output node and configured to provide a second current path in accordance with a second drive signal. The integrated circuit includes a drive circuit configured to generate, in response to a switch-on command, the first drive signal and the second drive signal such that the first part of the semiconductor switch and the second part of the semiconductor switch are alternatingly switched on and off. During an overlap period, both the first and the second part of the semiconductor switch are in an on-state.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Mirko Bernardoni, Christian Djelassi-Tscheck
  • Patent number: 10958271
    Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10931278
    Abstract: The present invention provides a driving circuit of a switching transistor, the driving circuit capable of suppressing an output voltage from changing sharply. A driver circuit includes a first transistor to a fourth transistor and a pre-driver. The pre-driver (i) provides a first gate signal having a negative edge slope smaller than a positive edge slope to the gate of the first transistor, (ii) provides a second gate signal having a positive edge slope smaller than a negative edge slope to the gate of the second transistor, (iii) provides a third gate signal having a positive edge slope smaller than the positive edge slope of the first gate signal to the gate of the third transistor, and (iv) provides a fourth gate signal having a negative edge slope smaller than the negative edge slope of the second gate signal to the gate of the fourth transistor.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 23, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Takafumi Morinaka
  • Patent number: 10911269
    Abstract: An apparatus is described. The apparatus includes a decision feedback equalizer circuit having a summation circuit. The summation circuit has a differential pair that includes first and second transistors coupled to a current source. The current source is to draw a current through the first and second transistors. The decision feedback circuit also includes a circuit to adjust the current to compensate for a change in electron mobility of at least one transistor of the current source.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Anup J. Deka, Kambiz R. Munshi
  • Patent number: 10879883
    Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Jikai Chen, Yanli Fan, Md Anwar Sadat
  • Patent number: 10879899
    Abstract: An apparatus includes: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the first inverter connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the second inverter connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively; a first resistor connected to a first DC (direct-current) voltage to the first source node; and a second resistor connected to a second DC voltage to the second source node.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 29, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10873716
    Abstract: A pixel cell and row select and row driver circuits include two column bias circuits and row driver circuits, one placed at the right and one placed at the left side of the array of pixel cells. The digital control signals for the two sets of bias and row driver circuits enter at the center top or bottom of the array of pixel cells and drive the circuits symmetrically. The combination of two-sided row driver and column bias helps eliminate any signal delay and bias difference between the left and right side of the pixel cell array. More significantly this circuit construction can minimize horizontal shading in the resulting image.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: December 22, 2020
    Assignee: SmartSens Technology (HK) Co., Ltd.
    Inventors: Chen Xu, Yaowu Mo, Zexu Shao, Weijian Ma
  • Patent number: 10873323
    Abstract: A low-power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, which includes an up-cell having a first resistor and a first transistor, and a down-cell having a second resistor, a second transistor, and a third transistor. A calibration circuit drives a replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the up-cell and adjusting a second gate voltage applied to the third transistor of the replica of the down-cell. The calibrated first gate voltage is applied to the first transistor and to the second transistor of each of the plurality of driver slices and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 22, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Fei Guo, Yihui Li, Hong Xue, Xin Ma, Hui Wang
  • Patent number: 10848155
    Abstract: A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a high-swing mode, a low-swing mode with equalization, and a low-swing mode without equalization. Transmitter circuitry provided in this way removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth, flexibility, and scalability demands.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventor: Chee Seng Leong
  • Patent number: 10840907
    Abstract: A source-coupled logic (SCL) gate configured to reduce power supply noise generation and reduce DC power consumption by adjusting a bias current to deliver only the performance level required for a given application. The SCL gate circuit arrangement includes a current mirror circuit with transistors configured as pull-up transistors. The pull-up transistors set the logical HIGH voltage level. The SCL gate circuit may also include voltage limiting devices configured to set the logical LOW voltage level. The current mirror circuit and the voltage limiting devices allow the SCL gate to receive a bias current supplied a bias circuit that is less complex than bias circuitry used by other examples of SCL circuitry. Adjusting the bias current delivers the desired performance with the commensurate reduction in power consumption.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Honeywell International Inc.
    Inventor: Paul M. Werking
  • Patent number: 10833589
    Abstract: A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 10, 2020
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Thomas Ribarich, Victor Sinow, Daniel Marvin Kinzer
  • Patent number: 10825506
    Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that may couple to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks to a controller. The semiconductor device may also include a plurality of switches that may couple a voltage source to the output buffer, a first pull-down switch that may drive the output buffer to a low voltage reference level to correct its drive strength. The device also includes a second pull-down switch that may couple the output buffer to the low voltage reference level. The plurality of switches, the first pull-down switch, and the second pull-down switch may each provide the data voltage signal to the output buffer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael V. Ho
  • Patent number: 10819352
    Abstract: An output circuit comprises an output terminal (11), a first current mirror (12), a first pass transistor (13) and a first delivering terminal (14) coupled via the first current mirror (12) and the first pass transistor (13) to the output terminal (11).
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 27, 2020
    Assignee: ams AG
    Inventors: Thomas Schrei, Vida Uhde-Djefroudi
  • Patent number: 10812074
    Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 20, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Yongjie Cheng, Lei Zhu, Kyehyung Lee
  • Patent number: 10775820
    Abstract: A voltage regulator includes an error amplifier configured to amplify a difference between a feedback voltage and a reference voltage. The regulator also includes an N-type metal-oxide-semiconductor (NMOS) driver circuit. The driver circuit includes an n-type field effect transistor. The driver circuit is communicatively coupled to output of the error amplifier. The regulator further includes a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the error amplifier to provide the feedback voltage.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 15, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Raghuveer Murukumpet, James Bartling
  • Patent number: 10756709
    Abstract: A system may include a driver for driving an output signal to a load, a pre-driver for driving a pre-driver signal to the driver, the pre-driver having a variable drive strength, and a controller configured to control the variable drive strength based on at least one measured physical quantity to compensate for variation of an output signal edge rate due to variations in the at least one measured physical quantity.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 25, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Mengde Wang, Akhilesh Persha, Eric B. Smith, Vamsikrishna Parupalli
  • Patent number: 10756731
    Abstract: A power source multiplexer includes a first switch circuit connected between a first input voltage source node and an output voltage node. A second switch circuit is connected between a second input voltage source node and the output voltage node. A driver circuit is configured to provide a steady-state current to drive one of the first or second switch circuits to electrically connect the respective input voltage source node to the output voltage node. A boost circuit is configured to boost the steady-state current for a switching time interval when switching from one of the input voltage source nodes being connected to the output node to the other of the input voltage source nodes being connected to the output voltage node.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Turkson, Sungho Beck, Jae Won Choi, Johnny Klarenbeek
  • Patent number: 10747693
    Abstract: A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Ravi Kiran Kandikonda
  • Patent number: 10686438
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsin Yu, Nick Pai, Bo-Ting Chen
  • Patent number: 10680634
    Abstract: Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 9, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Kiarash Gharibdoust, Armin Tajalli, Pavan Kumar Jampani, Ali Hormati
  • Patent number: 10679684
    Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Keun Seon Ahn, Yo Han Jeong, Jin Ha Hwang
  • Patent number: 10671112
    Abstract: A gate driving circuit includes a pull-up control part for applying a first previous carry signal to a first node in response to the first previous carry signal, a first pull-up part outputting a clock signal as an N-th gate output signal in response to a signal applied to the first node, a second pull-up part outputting the clock signal as the N-th gate output signal in response to the signal applied to the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal applied to the first node, a first pull-down part pulling down the signal at the first node to a second off voltage, and a second pull-down part pulling down the N-th gate output signal to a first off voltage, wherein one of the first pull-up part and the second pull-up part is selectively activated.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Whee-Won Lee, Ji Young Eom
  • Patent number: 10606294
    Abstract: A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.
    Type: Grant
    Filed: January 6, 2019
    Date of Patent: March 31, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Liang-Ting Kuo, Mu-Jung Chen, Chi-Chun Liao
  • Patent number: 10540944
    Abstract: A small semiconductor device is provided. The semiconductor device includes a register, switches, a memory circuit, a controller, and a display. An output terminal of the register is electrically connected to two or more of the switches. The switches are electrically connected to the memory circuit. The register has a function of retaining data corresponding to a parameter used when the controller operates. The switches have a function of selecting the memory circuit to which the data retained in the register is to be output. The memory circuit has a function of retaining the data output from the register. The controller has a function of reading the data retained in the memory circuit to control operation of the display.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Munehiro Kozuma