With Field-effect Transistor Patents (Class 326/27)
  • Patent number: 11282550
    Abstract: Examples described herein can be used to calibrate resistances provided by pull-up and pull-down circuits in an output driver circuit. A first reference voltage can be determined and applied to set a resistance level of a pull-up circuit to a desired level. A code for activating one or more transistor in the pull-up circuit can be determined against the first reference voltage. For a pull-down circuit, a second reference voltage can be set a resistance level of the pull-down circuit to a desired level. The resistance level of the pull-down circuit can be set to equal to the resistance level of the pull-up circuit. A second code can be set for activating one or more transistor in the pull-down circuit. The first and second reference voltages can be represented by index values. The code and second code can be stored for use by the pull-up circuit and pull-down circuit. Re-calibration of the pull-up and pull-down circuits can be performed to determine codes using the first and second reference voltages.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Luigi Pilolli, Agatino Massimo Maccarrone, Jiawei Chen, Qiang Tang
  • Patent number: 11271557
    Abstract: An adaptive gate driver for a driving a power MOSFET to switch is disclosed. The adaptive gate driver includes a load sense circuit to sense a current through the power MOSFET. A controller coupled to the load sense circuit compares the sensed current to a threshold to determine if the load on the power MOSFET is a normal load or a heavy load. Based on the comparison, the controller controls the gate driver to drive the power MOSFET with a first strength level when a normal load determined and at second strength level when a heavy load is determined. The driving strength in the heavy-load condition is lower than the normal-load condition and by lowering the driving strength of the gate driver during the heavy-load condition a voltage across the power MOSFET may be prevented from exceeding a threshold related to a breakdown condition during a switching period.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 8, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Zhiwei Liu, Marc Dagan, Xudong Huang
  • Patent number: 11223350
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsin Yu, Nick Pai, Bo-Ting Chen
  • Patent number: 11169107
    Abstract: An electronic impedance measurement device: a branch, called measurement branch, including an impedance to be measured (Zm), and; at least one branch, called reference branch, including an impedance (Zr), called reference impedance; electronics, called detection electronics, configured to provide an error signal (Vs) dependent on an algebraic sum of a current (Ir) flowing in the at least one reference branch (104) and of a current (Im) flowing in the measurement branch; and at least one adjustment structure, changing the current (Ir) in at least one of said reference branches in a manner inversely proportional to a control variable (k).
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: November 9, 2021
    Assignee: FOGALE NANOTECH
    Inventor: Christian Neel
  • Patent number: 11171643
    Abstract: A switching circuit can help reduce electrical feedback ringing at a gate terminal of a transistor. The switching circuit can include a transistor circuit to switch an electrical signal and a control circuit to provide an actuation signal to the gate terminal of the transistor device. The switching circuit can also include a booster circuit that is disposed between the control circuit and the gate terminal of the transistor device. The booster circuit can be configured to detect a signal from the control circuit to turn off the transistor device and, responsive to the detected signal, drive a current into the gate terminal of the transistor device for a specified span of time before the transistor device turns off.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 9, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventor: Martin Murnane
  • Patent number: 11153515
    Abstract: A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 19, 2021
    Assignee: Sony Corporation
    Inventors: Shunichi Sukegawa, Shunji Maeda, Junichi Ishibashi, Motoshige Okada
  • Patent number: 11128283
    Abstract: A transmitter may include an emphasis circuit suitable for generating a first pull-down driving signal in response to first data and delayed second data, and generating a first pull-up driving signal in response to second data and delayed first data, wherein the first and second data are a differential pair; a phase skew compensation circuit suitable for compensating for a phase skew between the first pull-up driving signal and the first pull-down driving signal to generate a second pull-up driving signal and a second pull-down driving signal; a pull-up driver suitable for pull-up driving an output node in response to the second pull-up driving signal; and a pull-down driver suitable for pull-down driving the output node in response to the second pull-down driving signal.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Ji Hyo Kang
  • Patent number: 11054938
    Abstract: A capacitance-sensing circuit may include a channel input associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a capacitive hardware baseliner that is coupled to the channel input. The capacitive hardware baseliner includes a programmable baseline resistor, and a buffer with an input coupled to the programmable baseline resistor and an output coupled to the channel input. The capacitive hardware baseliner generates a baseline current based on a time constant of the channel input associated with the measuring of the capacitance of the element of the capacitive sense array using the programmable baseline resistor. The capacitive hardware baseliner provides the baseline current at the channel input to provide a charge for a sense capacitor. A change in the charge of the sense capacitor is provided by the baseline current indicating a presence of a touch object proximate to the element.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 6, 2021
    Assignee: Cypress Semiconductor Corporation
    Inventors: Denis Ellis, Kaveh Hosseini, Timothy John Williams, Gabriel Rowe, Roman Ogirko, Brendan Lawton
  • Patent number: 11042176
    Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-An Chang, Chia-Fu Lee, Yu-Der Chih, Yi-Chun Shih
  • Patent number: 11041910
    Abstract: An electronic device includes a battery for supplying electrical power for operation of the electronic device, an acquisition unit configured to connect to a measuring instrument and acquire measurement data from the measuring instrument, a temperature sensor configured to measure a reference temperature, and a controller configured to correct the measurement data on the basis of the reference temperature. The controller acquires the terminal voltage of the battery and sets a lifespan voltage on the basis of the reference temperature. The lifespan voltage is used as a standard for outputting an alarm encouraging replacement of the battery before the terminal voltage of the battery falls below the voltage necessary for the electronic device to operate. The controller outputs the alarm when the terminal voltage is less than the lifespan voltage.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: June 22, 2021
    Assignee: YOKOGAWA ELECTRIC CORPORATION
    Inventors: Masayuki Uchida, Ken Kaku
  • Patent number: 11018664
    Abstract: An integrated circuit that may be employed as a smart switch. The integrated circuit includes a first part of a semiconductor switch coupled between a supply node and an output node and configured to provide a first current path in accordance with a first drive signal. The integrated circuit further includes a second part of the semiconductor switch coupled between the supply node and the output node and configured to provide a second current path in accordance with a second drive signal. The integrated circuit includes a drive circuit configured to generate, in response to a switch-on command, the first drive signal and the second drive signal such that the first part of the semiconductor switch and the second part of the semiconductor switch are alternatingly switched on and off. During an overlap period, both the first and the second part of the semiconductor switch are in an on-state.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Mirko Bernardoni, Christian Djelassi-Tscheck
  • Patent number: 10958271
    Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10931278
    Abstract: The present invention provides a driving circuit of a switching transistor, the driving circuit capable of suppressing an output voltage from changing sharply. A driver circuit includes a first transistor to a fourth transistor and a pre-driver. The pre-driver (i) provides a first gate signal having a negative edge slope smaller than a positive edge slope to the gate of the first transistor, (ii) provides a second gate signal having a positive edge slope smaller than a negative edge slope to the gate of the second transistor, (iii) provides a third gate signal having a positive edge slope smaller than the positive edge slope of the first gate signal to the gate of the third transistor, and (iv) provides a fourth gate signal having a negative edge slope smaller than the negative edge slope of the second gate signal to the gate of the fourth transistor.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: February 23, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Takafumi Morinaka
  • Patent number: 10911269
    Abstract: An apparatus is described. The apparatus includes a decision feedback equalizer circuit having a summation circuit. The summation circuit has a differential pair that includes first and second transistors coupled to a current source. The current source is to draw a current through the first and second transistors. The decision feedback circuit also includes a circuit to adjust the current to compensate for a change in electron mobility of at least one transistor of the current source.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Anup J. Deka, Kambiz R. Munshi
  • Patent number: 10879899
    Abstract: An apparatus includes: a first inverter configured to receive a first clock signal and output a second clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the first inverter connect to the first clock signal, the second clock signal, a first source node, and a second source node, respectively; a second inverter configured to receive the second clock signal and output a third clock signal, wherein an input pin, an output pin, a power pin, and a ground pin of the second inverter connect to the second clock signal, the third clock signal, the first source node, and the second source node, respectively; a first resistor connected to a first DC (direct-current) voltage to the first source node; and a second resistor connected to a second DC voltage to the second source node.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: December 29, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventor: Chia-Liang (Leon) Lin
  • Patent number: 10879883
    Abstract: In examples, an integrated circuit package comprises a pin exposed externally to the package; at least one resistor coupled to the pin at a first end of the resistor; a first transistor coupled to the at least one resistor at a second end of the resistor and coupled to a voltage source; a second transistor coupled to the at least one resistor at the second end of the resistor and coupled to a ground connection, the at least one resistor and the first and second transistors couple at a first node, the first and second transistors are of different types; and multiple comparators, each of the multiple comparators coupled to a voltage divider network and to the pin.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Huanzhang Huang, Jikai Chen, Yanli Fan, Md Anwar Sadat
  • Patent number: 10873323
    Abstract: A low-power transmitter for transmitting digital signals from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver comprised of a plurality of driver slices, which includes an up-cell having a first resistor and a first transistor, and a down-cell having a second resistor, a second transistor, and a third transistor. A calibration circuit drives a replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the up-cell and adjusting a second gate voltage applied to the third transistor of the replica of the down-cell. The calibrated first gate voltage is applied to the first transistor and to the second transistor of each of the plurality of driver slices and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 22, 2020
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Fei Guo, Yihui Li, Hong Xue, Xin Ma, Hui Wang
  • Patent number: 10873716
    Abstract: A pixel cell and row select and row driver circuits include two column bias circuits and row driver circuits, one placed at the right and one placed at the left side of the array of pixel cells. The digital control signals for the two sets of bias and row driver circuits enter at the center top or bottom of the array of pixel cells and drive the circuits symmetrically. The combination of two-sided row driver and column bias helps eliminate any signal delay and bias difference between the left and right side of the pixel cell array. More significantly this circuit construction can minimize horizontal shading in the resulting image.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: December 22, 2020
    Assignee: SmartSens Technology (HK) Co., Ltd.
    Inventors: Chen Xu, Yaowu Mo, Zexu Shao, Weijian Ma
  • Patent number: 10848155
    Abstract: A multichip package may include a transmitter die and a receiver mounted on a substrate. The transmitter die may be coupled to the receiver die through die-to-die connections such as microbumps and conductive paths in the substrate. The transmitter die may include flexible transmitter circuitry having transceiver logic and driver circuitry. The driver circuitry may include a high-swing driver and a low-swing driver optionally equalization circuitry. The driver circuitry may operable in a high-swing mode, a low-swing mode with equalization, and a low-swing mode without equalization. Transmitter circuitry provided in this way removes undesirable DC voltage paths to ground present in other driving schemes to reduce power consumption while still meeting bandwidth, flexibility, and scalability demands.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventor: Chee Seng Leong
  • Patent number: 10840907
    Abstract: A source-coupled logic (SCL) gate configured to reduce power supply noise generation and reduce DC power consumption by adjusting a bias current to deliver only the performance level required for a given application. The SCL gate circuit arrangement includes a current mirror circuit with transistors configured as pull-up transistors. The pull-up transistors set the logical HIGH voltage level. The SCL gate circuit may also include voltage limiting devices configured to set the logical LOW voltage level. The current mirror circuit and the voltage limiting devices allow the SCL gate to receive a bias current supplied a bias circuit that is less complex than bias circuitry used by other examples of SCL circuitry. Adjusting the bias current delivers the desired performance with the commensurate reduction in power consumption.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Honeywell International Inc.
    Inventor: Paul M. Werking
  • Patent number: 10833589
    Abstract: A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: November 10, 2020
    Assignee: NAVITAS SEMICONDUCTOR LIMITED
    Inventors: Santosh Sharma, Thomas Ribarich, Victor Sinow, Daniel Marvin Kinzer
  • Patent number: 10825506
    Abstract: A semiconductor device may include a plurality of memory banks and an output buffer that may couple to the plurality of memory banks. The output buffer may produce a data voltage signal representative of data to be read from at least one of the plurality of memory banks to a controller. The semiconductor device may also include a plurality of switches that may couple a voltage source to the output buffer, a first pull-down switch that may drive the output buffer to a low voltage reference level to correct its drive strength. The device also includes a second pull-down switch that may couple the output buffer to the low voltage reference level. The plurality of switches, the first pull-down switch, and the second pull-down switch may each provide the data voltage signal to the output buffer.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael V. Ho
  • Patent number: 10819352
    Abstract: An output circuit comprises an output terminal (11), a first current mirror (12), a first pass transistor (13) and a first delivering terminal (14) coupled via the first current mirror (12) and the first pass transistor (13) to the output terminal (11).
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: October 27, 2020
    Assignee: ams AG
    Inventors: Thomas Schrei, Vida Uhde-Djefroudi
  • Patent number: 10812074
    Abstract: In accordance with embodiments of the present disclosure, a system may include a buffer and a switch coupled between the buffer and a voltage supply such that the switch controls a varying voltage at a varying voltage node coupled to the buffer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: October 20, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Yongjie Cheng, Lei Zhu, Kyehyung Lee
  • Patent number: 10775820
    Abstract: A voltage regulator includes an error amplifier configured to amplify a difference between a feedback voltage and a reference voltage. The regulator also includes an N-type metal-oxide-semiconductor (NMOS) driver circuit. The driver circuit includes an n-type field effect transistor. The driver circuit is communicatively coupled to output of the error amplifier. The regulator further includes a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the error amplifier to provide the feedback voltage.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: September 15, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Raghuveer Murukumpet, James Bartling
  • Patent number: 10756709
    Abstract: A system may include a driver for driving an output signal to a load, a pre-driver for driving a pre-driver signal to the driver, the pre-driver having a variable drive strength, and a controller configured to control the variable drive strength based on at least one measured physical quantity to compensate for variation of an output signal edge rate due to variations in the at least one measured physical quantity.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 25, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Mengde Wang, Akhilesh Persha, Eric B. Smith, Vamsikrishna Parupalli
  • Patent number: 10756731
    Abstract: A power source multiplexer includes a first switch circuit connected between a first input voltage source node and an output voltage node. A second switch circuit is connected between a second input voltage source node and the output voltage node. A driver circuit is configured to provide a steady-state current to drive one of the first or second switch circuits to electrically connect the respective input voltage source node to the output voltage node. A boost circuit is configured to boost the steady-state current for a switching time interval when switching from one of the input voltage source nodes being connected to the output node to the other of the input voltage source nodes being connected to the output voltage node.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Richard Turkson, Sungho Beck, Jae Won Choi, Johnny Klarenbeek
  • Patent number: 10747693
    Abstract: A memory device includes a first set of data input/output (I/O) devices configured to communicate a first portion of a data unit to or from an external controller; a second set of data I/O devices configured to communicate a second portion of the data unit to or from the external controller; a data control circuit can share the internal global data lines by multiplexing the timings of the first and second sets of data I/O devices, the data control circuit configured to route the data unit according to a data operation corresponding to the data unit; and a shared data bus coupling both the first set of data I/O devices and the second set of data I/O devices to the data control circuit, the shared data bus configured to relay both the first portion and the second portion of the data unit.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Michael V. Ho, Ravi Kiran Kandikonda
  • Patent number: 10686438
    Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter, and configured for driving the input/output pad to a voltage level based on the data signal and the output enable signal.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Hsin Yu, Nick Pai, Bo-Ting Chen
  • Patent number: 10680634
    Abstract: Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: June 9, 2020
    Assignee: KANDOU LABS, S.A.
    Inventors: Kiarash Gharibdoust, Armin Tajalli, Pavan Kumar Jampani, Ali Hormati
  • Patent number: 10679684
    Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Keun Seon Ahn, Yo Han Jeong, Jin Ha Hwang
  • Patent number: 10671112
    Abstract: A gate driving circuit includes a pull-up control part for applying a first previous carry signal to a first node in response to the first previous carry signal, a first pull-up part outputting a clock signal as an N-th gate output signal in response to a signal applied to the first node, a second pull-up part outputting the clock signal as the N-th gate output signal in response to the signal applied to the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal applied to the first node, a first pull-down part pulling down the signal at the first node to a second off voltage, and a second pull-down part pulling down the N-th gate output signal to a first off voltage, wherein one of the first pull-up part and the second pull-up part is selectively activated.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Whee-Won Lee, Ji Young Eom
  • Patent number: 10606294
    Abstract: A low dropout voltage regulator, coupled to a load circuit receiving a clock signal, includes an amplifier; a power transistor comprising a control terminal, coupled to an output terminal of the amplifier; and a first terminal, coupled to a positive input terminal of the amplifier and the load circuit; and a control circuit, configured to control a current flowing through the power transistor in response to the clock signal.
    Type: Grant
    Filed: January 6, 2019
    Date of Patent: March 31, 2020
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Liang-Ting Kuo, Mu-Jung Chen, Chi-Chun Liao
  • Patent number: 10540944
    Abstract: A small semiconductor device is provided. The semiconductor device includes a register, switches, a memory circuit, a controller, and a display. An output terminal of the register is electrically connected to two or more of the switches. The switches are electrically connected to the memory circuit. The register has a function of retaining data corresponding to a parameter used when the controller operates. The switches have a function of selecting the memory circuit to which the data retained in the register is to be output. The memory circuit has a function of retaining the data output from the register. The controller has a function of reading the data retained in the memory circuit to control operation of the display.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: January 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Munehiro Kozuma
  • Patent number: 10520971
    Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: December 31, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sri Navaneethakrishnan Easwaran, Vijayalakshmi Devarajan, Timothy Paul Duryea, Shanmuganand Chellamuthu
  • Patent number: 10511306
    Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: December 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Tetsuya Arai, Shuichi Tsukada, Junki Taniguchi
  • Patent number: 10498324
    Abstract: A waveform conversion circuit for turning a switch device on and off by applying a control signal from a controller to a gate terminal of the switch device is provided. The switch device has the gate terminal, a drain terminal, and a source terminal. The waveform conversion circuit includes a parallel circuit of a first capacitor and a first resistor and a voltage clamp unit. The parallel circuit is coupled between the controller and the gate terminal. The voltage clamp unit is coupled between the gate terminal and the source terminal and configured to clamp a voltage across the gate terminal to the source terminal at a first voltage in an OFF pulse of the control signal and at a second voltage in an ON pulse of the control signal.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 3, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventor: Po-Chin Chuang
  • Patent number: 10496230
    Abstract: The present disclosure relates to a touch circuit, a touch sensing device, and a touch sensing method. According to the present disclosure, it is possible to obtain an accurate touch sensing result (the presence or absence of a touch and/or a touch position) by compensating for the unintentional change in the quantity of the charge corresponding to a signal obtained by driving a touch screen panel, so as to obtain sensing data in which the influence of the parasitic capacitance generated inside or outside the touch screen panel is reduced or eliminated, thereby improving capacitance-based touch sensing performance.
    Type: Grant
    Filed: December 16, 2017
    Date of Patent: December 3, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: HongJu Lee, HyeongWon Kang, Youngwoo Jo
  • Patent number: 10498385
    Abstract: A transceiver circuit may include: a first NMOS transistor suitable for pulling up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 3, 2019
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Deog-Kyoon Jeong, Han-Gon Ko
  • Patent number: 10488682
    Abstract: Disclosed are structures and methods for CMOS drivers that drive silicon optical push-pull Mach-Zehnder modulators (MZMs) with twice the drive voltage per interferometer arm as with prior art designs.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: November 26, 2019
    Assignee: Acacia Communications, Inc.
    Inventor: Christopher Doerr
  • Patent number: 10461749
    Abstract: Techniques are described for ground-intermediating buffering that can effectively use the reference grounds of the circuit domains on either side of a buffer stage to generate one or more intermediated grounds for one or more signal buffers. For example, one of the reference grounds has a first amount of ground noise, the other of the reference grounds has a second amount of ground noise that is greater than or less than the first amount, and the intermediated grounds are generated to have respective amounts of ground noise that are between the first and second amounts. The ground intermediating buffer can perform signal buffering with respect to the intermediated ground(s), thereby reducing ground noise coupling across the circuit domains through both the signal and ground paths of the buffer stage.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: October 29, 2019
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Kaveh Moazzami, Faisal Hussein, Ahmed Emira
  • Patent number: 10429998
    Abstract: A capacitance-sensing circuit may include a plurality of channel inputs associated with measuring a capacitance of a unit cell of a capacitive sense array. The capacitance-sensing circuit may also include a baseliner component that is coupled to the plurality of channel inputs. The baseliner component may generate a baseline compensation signal using a capacitive circuit and may provide the baseline compensation signal to each of the plurality of channel inputs of the capacitive sense array.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 1, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Roman Ogirko, Denis Ellis, Kaveh Hosseini, Brendan Lawton
  • Patent number: 10431266
    Abstract: A semiconductor storage device includes: a first terminal, a plurality of first and second output buffers, a register, a plurality of first pre-drivers including a plurality of first transistors operating according to a first signal, and a plurality of second pre-drivers including a plurality of second transistors operating according to a second signal. A first output control circuit selects the first pre-drivers in accordance with a third signal obtained by conversion of the second signal. A second output control circuit selects the second pre-drivers in accordance with a fourth signal obtained by conversion the first signal. A third output circuit transmits an output signal to the first and second output circuits.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuyoshi Muraoka, Masami Masuda, Junya Matsuno, Masatoshi Kohno, Yuui Shimizu
  • Patent number: 10424358
    Abstract: Disclosed is a device including a selected distributed driver, a first feedback control circuit, and a second feedback control circuit. The first feedback control circuit is coupled to the selected distributed driver. The first feedback control circuit is configured to maintain an output of the selected distributed driver within a first predetermined range. The second feedback control circuit is selectively coupled to the selected distributed driver and is configured to maintain the output of the selected distributed driver to be within a second predetermined range. The second predetermined range is within the first predetermined range.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 24, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Supraja Sundaresan, Sung-en Wang, Khin Htoo, Primit Modi
  • Patent number: 10409311
    Abstract: Apparatus embodiments of the invention are disclosed for requesting power via a wired interface. In example embodiments, a pull-down circuit in the apparatus acting as a power consumer when there is no energy in the apparatus, is connected via a configuration line over a cable to a power provider device. The apparatus may be in a power down mode, it may have an empty battery, or it may have no battery. The pull-down circuit is configured to use energy from the configuration line to pull down a voltage on the configuration line, to signal the power provider device to provide power over another line of the cable to the apparatus.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 10, 2019
    Assignee: Nokia Technologies Oy
    Inventors: Pekka Leinonen, Kai Inha, Pekka Talmola, Timo Toivola, Teemu Helenius, Seppo Jarvensivu, Kristian Vaajala, Tino Hellberg
  • Patent number: 10361669
    Abstract: An output circuit includes a first transistor, a second transistor, an operational amplifier that outputs a control voltage, and a switch circuit that controls voltage output in accordance with a control signal. When the control signal is in a first state, the switch circuit supplies the control voltage to the gate of the first transistor to turn on the first transistor and electrically connects the drain of first transistor to the operational amplifier so that a first output voltage is output from the drain of the first transistor. When the control signal is in a second state, the switch circuit supplies the control voltage to the gate of the second transistor to turn on the second transistor and electrically connects the drain of the second transistor to the operational amplifier so that a second output voltage is output from the drain of the second transistor.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: July 23, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yusuke Shimamune
  • Patent number: 10338619
    Abstract: A digitally-assisted voltage regulator includes a gate driver circuit and a compensation circuit. The voltage regulator digitizes the load profile, and uses the digital information to compensate for process and temperature variations. The voltage regulator outputs a regulated voltage signal and one or more control signals based on a supply voltage and a reference voltage. The gate driver circuit receives the regulated voltage signal and generates a gate driver signal. The compensation circuit receives the control signal and generates first and second compensation signals. The voltage regulator regulates a voltage level of the regulated voltage signal using the regulator compensation signal, and controls a ramp-rate of the gate driver signal using the second compensation signal.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 2, 2019
    Assignee: NXP B.V.
    Inventors: Shishir Goyal, Arvind Sherigar
  • Patent number: 10340918
    Abstract: A level shift includes a bias voltage providing circuit, a level shifting circuit and an output switching circuit. The level shifting circuit includes a high level shifting unit and a low level shifting unit. When the high level shifting unit is in a cut-off state, the high level shifting unit further receives a first bias voltage such that the high level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the high level shifting unit. When the low level shifting unit is in a cut-off state, the low level shifting unit further receives a second bias voltage such that the low level shifting unit is in a partially cut-off state, accordingly increasing a response speed of the low level shifting unit. The level shifter of the present application provides a higher response speed.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: July 2, 2019
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: Jun Wu
  • Patent number: 10302880
    Abstract: A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 28, 2019
    Assignee: Luxtera, Inc.
    Inventors: Daniel Kucharski, John Andrew Guckenberger, Thierry Pinguet, Sherif Abdalla
  • Patent number: 10270441
    Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 23, 2019
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Vijay Gadde, Benedict Lau