Abstract: The compensation circuit comprises an oscillator, a first variable delay line, a second variable delay line, a phase detector and a controller. The oscillator generates an oscillation signal to input into a first transmission line and a second transmission line. The first variable delay line receives the oscillation signal transmitted through the first transmission line. The second variable delay line receives the oscillation signal transmitted through the second transmission line. The phase detector compares the phases of the two oscillation signals from the variable delay lines to generate a phase difference signal. The controller adjusts the variable delay lines to compensate for asynchronous signal transmission of the transmission lines according to the phase difference signal.

Abstract: Noise reduction among conductors, the conductors disposed adjacent to one another, the conductors characterized as two or more aggressor conductors and one or more victim conductors, a least two of the aggressor conductors driven with at least two signals that induce unwanted crosstalk upon at least one of the victim conductors, a programmable delay device disposed in a signal path of each of the at least two signals that induce unwanted crosstalk, including programming a delay period into each programmable delay device; receiving, simultaneously at the programmable delay devices, the at least two signals that induce unwanted crosstalk; and transmitting, on two aggressor conductors, the at least two signals that induce unwanted crosstalk, with the at least two signals separated in time by the delay period.

Abstract: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.

Abstract: Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: A circuit for removing noise from an input signal includes a falling edge signal delaying circuit configured to output a first delay output signal generated by delaying a falling edge of a first output signal for a preset time; a falling edge sensing circuit configured to sense the falling edge of the first output signal, and generate a pulse signal in accordance with the sense; a flip-flop configured to output the first delay output signal in accordance with an input clock signal; and a first logic operation circuit configured to perform a logic operation on an output signal of the flip-flop and the first output signal delayed for the preset time, thereby generating a second output signal.

Abstract: In some embodiments, a chip includes first and second nodes, a variable voltage source, and transmitter and control circuitry. The transmitter includes a driver coupled to the first and second nodes, and first and second resistive structures coupled between the first and second nodes, respectively, and the variable voltage source. The control circuitry selects an impedance level for the first and second resistive structures, and detect coupling of a remote receiver to the transmitter through interconnects and detect decoupling of the remote receiver from the transmitter. Other embodiments are described and claimed.

Abstract: Systems and methods for Current Management of Digital Logic Devices are provided. In one embodiment a method for calibrating a digital logic circuit current management system is provided. The method comprises activating one or more synchronous logic paths of a plurality of synchronous logic paths within the digital logic integrated circuit; sampling a voltage powering the digital logic integrated circuit while activating the one or more synchronous logic paths; storing one or more data samples representative of the sampled voltage; and calculating a bypass current setpoint based on the one or more data samples, wherein the bypass current setpoint specifies one or more bypass current characteristic to prevent the voltage powering the digital logic integrated circuit from dropping below a reference voltage.

Abstract: A bus structure of a mobile communication terminal for reducing digital noise is disclosed. The bus structure comprises a bus switch controller, a first element having a first bus, a second element having a second bus, and a common bus for connecting the first bus and the second bus. A bus switch positioned between the first element and the second element for disconnecting at least one of the first bus and the second bus from the common bus in response to a control signal from the bus switch controller for reducing digital noise of the common bus.

Abstract: The invention relates to an electronic module having two or more organic circuit elements connected together to give a logic circuit, said organic circuit elements being made up of organic components, in particular organic field effect transistors. The logic circuit comprises at least one filter module (5), which has an input (53) connected to one of the organic logic circuit elements, and an output (55), and is designed to filter out from the signals present at the input (53) the spurious signals generated by different signal propagation times in the organic components of the logic circuit elements, and to provide a regenerated binary signal at the output (55).

Abstract: A data bus circuit connects a south bridge driven by a first voltage and a bay driven by a second voltage. The first voltage and the second voltage are different. The data bus circuit includes a data bus that electrically connects the south bridge and the bay, and a Thevenin termination circuit that is arranged on the data bus at a point. The Thevenin termination circuit maintains a voltage at the point substantially equal to the first voltage.

Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: A logic signal isolator comprising a transformer having a primary winding and a secondary winding; a transmitter circuit which drives said primary winding in response to a received logic signal, such that in response to a first type of edge in the logic signal, a signal of a first predetermined type is supplied to the primary winding and in response to a second type of edge in the logic signal, a signal of a second predetermined type is supplied to said primary winding, the primary winding and the transmitter being referenced to a first ground; and the secondary winding being referenced to a second ground which is galvanically isolated from the first ground and said secondary winding supplying to a receiver circuit signals received in correspondence to the signals provided to the primary winding, the receiver reconstructing the received logic signal from the received signals.

Abstract: Integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC systems architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-clip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributers; the noise event arbiter determining when each noise contributer may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributer as to when permission is granted to execute its operations.

Abstract: Systems and methods are provided using dynamically adjustable differential output drivers. Integrated circuits such as programmable logic devices may be provided with adjustable differential output drivers for transmitting high-speed data to other integrated circuits. The peak-to-peak output voltage and common-mode voltage of the output drivers may be adjusted. Dynamic control circuitry may be used to control the settings of current sources, programmable resistors, and voltage source circuitry in the adjustable differential output driver automatically in real time. The adjustable components in the differential output driver may be adjusted by the dynamic control circuitry based on feedback information received from the integrated circuit to which the data is transmitted.

Abstract: A system may include detection of a low signal received from a transmission line, and uncoupling of a termination circuit from the transmission line in response to the detected low signal. In some aspects, a transition of a strobe signal is then detected, and the termination circuit is coupled to the transmission line in response to the detected transition.

Abstract: A semiconductor integrated circuit with an operating voltage having an absolute value is 2.5 V or below includes circuit blocks to which operation voltage is supplied by first and second power lines and a first switching element for each circuit block. Each circuit block includes a first MOS transistor in which a leakage current flows even under a condition that a gate voltage is equal to a source voltage. Each of the first switching elements controls the leakage current flowing through a corresponding first MOS transistor of each circuit block. Also, while one of the first switching elements is controlled to reduce the leakage current flowing through the circuit block relating to one of the first switching elements, another one of the first switching elements is controlled to allow current to flow through the circuit block relating to another one of the first switching elements.

Abstract: A logic signal isolator including a micro-transformer with a primary winding and a secondary winding. A transmitter circuit drives the primary winding in response to a received input logic signal such that, in response to a first type of edge in the logic signal, at least a first amplitude signal is supplied to the primary winding and, in response to a second type of edge in the logic signal, a second different amplitude signal is supplied to the primary winding. A receiver circuit receives corresponding first amplitude and second amplitude signals from the secondary winding and reconstructs the received logic input signal from the received signals.

Abstract: A semiconductor integrated circuit for matching the resistance of a variable resistor, which is used as a terminating resistor or a reference of said terminating resistor, to the characteristic impedance of a transmission line, has a terminating resistor adjusting circuit that has a current circuit connected to a power supply, said variable resistor that is connected between said current circuit and the ground and receives a main current output from said current circuit, a comparator circuit that compares the potential of the variable resistor with a first reference potential and outputs a signal, and a control circuit that controls the resistance of said variable resistor based on the output signal of said comparator circuit; and an additional current adjusting circuit that is connected between said power supply and said variable resistor and outputs an additional current to said variable resistor according to an external signal determined by the resistance of an external parasitic resistor between said term

Abstract: A plurality of transistor pairs of Pch and Nch transistors are connected in series between VDD and GND. An I/O terminal is connected to each connection point of the transistor pairs. Two transistor pairs constitute one transistor set, in which each of two Pch transistors and two Nch transistors have the same on-resistance. In input mode, one of the two transistor pairs in a first set is turned on, and a transistor pair of a second or later set is selectively turned on. In output mode, two Pch transistors or two Nch transistors of the first set are turned on, and a transistor of the second or later set is selectively turned on.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

Abstract: A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver and an input of the output generator. In addition, the slew rate control circuit includes a voltage clamp for clamping a voltage on the electrical interconnection between two known voltage reference levels. The voltage clamp may include a first current source for providing driving capacity to a driver circuit to prevent the voltage on the electrical interconnection from falling below one known voltage reference level. The voltage clamp may also include a second current source and a third current source for providing sinking capacity to the driver circuit to prevent the voltage on the electrical interconnection from rising above the other known voltage reference level.

Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

Abstract: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit's input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Abstract: In a gate driving circuit and a display apparatus having the same, a ripple preventing part is connected to a pull-up part and a control terminal (Q-node) to reset the Q-node. The ripple preventing part includes a first ripple preventing device that resets the Q-node during a high period of the first clock within a (n?1)H period, and a second ripple preventing device that resets the Q-node during a high period of a second clock within the (n?1)H period. A back-flow preventing device is connected between a previous carry node and the second ripple preventing device to prevent an electric charge of the Q-node from flowing back to the previous carry node.

Abstract: A noise canceller circuit capable of suppressing power supply noise, produced by transition of a data signal, even in case a data signal is increased in speed. The noise canceller circuit includes an output buffer 20 for outputting a first binary signal that may undergo transition at a timing synchronized with clock signals, and a second output buffer 21 for outputting a second binary signal which has undergone transition in case the first binary signal does not undergo transition at the above timing and for outputting the second binary signal without transition in case the first binary signal has undergone transition at the above timing. The respective output circuits of the output buffers 20, 21 are the same and are constructed so that the respective power supply sources VDD and the ground GND are common to the buffer circuits. A capacitor 24 for absorbing the noise is provided across the power supply and the ground.

Abstract: A circuit device and method for designing a serial link receiver, which accommodates a wide input voltage range and provides tolerance to high termination voltages. The receiver is designed with a pair of RC networks connected inline between the input and the preamplifier and a common mode feedback loop, which monitors shifts in the common mode voltage and adjusts the inputs provided to the preamplifier. The circuit device maintains a flat bandwidth to accommodate all signaling rates.

Abstract: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

Abstract: A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

Abstract: A peripheral device includes a data port having high and low impedance terminations, a transmitter having a data signal generator and a receiver detector. The data signal generator is electrically coupled to the low impedance termination of the data port when in a low impedance operating mode, and to the high impedance termination when in a high impedance operating mode. The receiver detector includes a noise detector adapted to detect a presence or an absence of rail-to-rail noise at the data port when the transmitter is in the high impedance operating mode.

Abstract: An impedance adjustment circuit for controlling an impedance of a variable impedance circuit includes a calibration circuit including a replica of the variable impedance circuit and configured to generate an impedance control signal for the variable impedance circuit based on a voltage generated at the replica of the variable impedance circuit in response to a reference current. The calibration circuit may be configured to generate the reference current based on a reference resistor coupled thereto. In particular, the calibration circuit may be configured to match a current in the replica of the variable impedance circuit and a current in the reference resistor to generate the voltage at the replica of the variable impedance circuit.

Abstract: An H-bridge LVDS driver circuit includes a means to calibrate the output impedance of the switches of an LVDS driver to any desired value.

Abstract: A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register.

Abstract: The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire. The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.

Abstract: Equalization circuitry includes additional components to boost the performance of the circuitry to a higher-order response. The additional components are preferably controllably variable so that the response can be adjusted to perform a wide range of equalization tasks. For example, the equalization circuitry can be used on signals received from connections having a wide range of signal propagation characteristics and/or on signals having a wide range of data rates, including data rates that can be very high.

Abstract: Disclosed is a semiconductor integrated circuit device that includes an output circuit with power thereof supplied from one power supply system, an input circuit with an input terminal thereof connected to an output terminal of the output circuit through a signal line and with power thereof supplied from other power supply system different from the one power supply system, and a circuit that restrains a current flowing from the output circuit into the signal line when an ESD stress is applied from the output circuit to a signal transmitting/receiving portion of the input circuit.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A data input buffer for use in a semiconductor device, including: a detection unit for receiving a reference voltage signal and an input data signal through a first input terminal and a second input terminal respectively in order to detect a voltage level of the input data signal based on a result of comparing the input data signal with the reference voltage in response to a clock enable signal inputted through a third input terminal; and a noise elimination unit connected between the first input terminal and the third input terminal for eliminating a noise of the reference voltage signal.

Abstract: In one embodiment, a decision feedback equalizer helps mitigate intersymbol interference in a bi-directional signaling environment. In the particular embodiment, the decision feedback equalizer includes a voltage-to-current converter to source a received differential current to first and second node, a latch to provide logic signal when comparing currents sourced to the first and second nodes, a memory unit to store the logic signals, and a mapping circuit to source first and second feedback currents to the first and second nodes. This embodiment further includes a transmitter to transmit data over a transmission line during receiving, and a digital-to-analog converter to provide a differential current to the first and second nodes to substantially cancel that part of the received differential currents contributed by the transmitter.

Abstract: Systems and methods for reducing variations in the timing of signal transitions which may result from interference with neighboring signal lines by adjusting the drivability of in-line buffers based upon the hostile/friendly condition of the neighboring lines. In one embodiment, a first inverter includes selectable current paths between the buffer output and Vdd/ground. A higher current is selected for one path and a lower current is selected for the other path so that the buffer output will be pulled more strongly in the direction (Vdd/ground) to which the neighboring signals may be hostile. In one embodiment, each selectable current path includes a plurality of parallel transistors, one of which is always switched on and the others of which are switched on or off according to the friendly/hostile states of the neighboring signals.

Abstract: An isolation cell provided between a first module (which can operate in either a power-up mode or a power down mode) and a second module. According to an aspect of the present invention, the isolation cell can be located to operate drawing power from either the first module or the second module without a floating node in the power-down mode of the first module. Due to the absence of the floating nodes, unneeded power drain is reduced/avoided. In one embodiment, a switch operates to connect power to a series of pair of inverters (propagating the signal from the first module to the second module) when the first module is in power-up mode and disconnects the power in the power-down mode.

Abstract: The invention relates to circuit elements and computing networks for resolving logical entanglement, in which the allowed logical value of a variable in a set of variables depends on the logical values of the other variables in the set. A circuit element according to the invention comprises two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are a logical true state, a logical false state, and an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source. An entanglement logic resolves the logical state of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals.

Abstract: One disclosed method comprises drawing current from a termination voltage supply and through a termination voltage delivery network by termination circuitry in response to a first signal on one or more lines terminated by the termination circuitry, shunting current from the termination voltage supply and through the termination voltage delivery network in response to a second signal on one or more terminated lines, and helping to reduce the shunted current for extended shunting.

Abstract: According to one example embodiment, a buffer, e.g., in a clock/signal distribution apparatus is provided that substantially reduces jitter due to power supply noise. Decoupler and input stage isolates load from the top rail power supply (VDD). In a more particular embodiment, jitter contributions from the bottom rail power supply (VSS) can be minimized by cross-coupled load devices within load. Substantial independence from process and temperature is facilitated through the use of current bias, such as Proportional to Absolute Temperature (PTAT) current bias.

Abstract: The present invention is a device and method to change the reflection time of a bidirectional signal so as to cause a false data value to be correctly seen as the proper data value when the bidirectional signal travels between a first semiconductor chip and a second semiconductor chip, through a transmission line between the two semiconductor chips. The reflection time is adjusted by coupling an electrical network to the transmission line to cause an early electrical reflection. In one embodiment, the network is coupled to establish an impedance discontinuity between the board trace and the package trace.

Abstract: The CPU of an electronic device generates a parameter for determining the amplitude of a serial data signal when it is output from an output device to a serial ATA bus. The parameter indicates a value that is needed to make the amplitude of the received serial data signal fall within a range, stipulated in serial ATA interface standards, when another electronic device receives the serial data signal. The parameter is generated in accordance with the cable length of the serial ATA bus designated by a cable length designation unit. The other electronic device is connected to the serial ATA bus.

Abstract: The strength of the output buffer is changed gradually when there is a transition in the output (or input) value. Due to the gradual change, switching noise is avoided in several contexts (e.g., when driving a transmission line, which causes reflections). In an embodiment, the gradual change is implemented using a combination of a current source and a capacitor. The capacitor is provided at an input of the gate terminal of a drive transistor, and a current source is used to control the rate at which the capacitor discharges. As a result, the drive strength of a buffer is controlled.

Abstract: A method and apparatus for redriving a data signal adjusts a sampling clock signal responsive to the data signal. An embodiment of an I/O cell may include a receiver to receive and redrive a data signal responsive to a sampling clock signal, and a sampling clock generator coupled to the receiver to generate the sampling clock signal, wherein the sampling clock generator is capable of adjusting the sampling clock signal responsive to the data signal.