Abstract: The slew rate enhancement circuit includes: a first transistor located between a first power source and an eleventh node, the first transistor having a gate electrode coupled to the eleventh node, the first transistor being coupled as a current mirror to the first current source; a third current source having the other side coupled to a second power source lower than the first power source; a second transistor coupled between the first power source and the eleventh node; a third transistor coupled between the eleventh node and one side of the third current source; a fourth transistor coupled between the first power source and a twelfth node; and a fifth transistor coupled between the twelfth node and the one side of the third current source.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch, a high side power switch, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a receiver input reset circuit configured to simultaneously receive first and second signals, wherein the first signal corresponds with the high side power switch being turned on, wherein the first signal corresponds with the high side power switch controller turning on the high side power switch, wherein the second signal corresponds with the high side power switch controller turning off the high side power switch, and wherein the receiver input reset circuit is further configured, in response to the first and second signals, to prevent the high side power switch from becoming non-conductive.

Abstract: Systems and methods for operating a bus interface unit include queues for receiving and storing one or more words from one or more agents for transmission on to a data bus. From at least a subset of the one or more words, a next word which will cause the least switching power among the subset of the one or more words when transmitted on to the data bus is determined and the next word is selected for transmission on to the data bus, to reduce dynamic power consumption of the data bus. The next word may be selected as a word among the subset of the one or more words with a least Hamming distance from a current word scheduled for transmission on to the data bus.

Abstract: A transmit driver is configured to operate under distinct supply voltage provided at output differential terminals. The transmit driver includes differential input transistors, first and second pairs of over-voltage protection differential transistors, and a current source coupled in series between the output terminals and a lower voltage rail. The transmit driver includes a first bias voltage generator configured to generate a first bias voltage based on the supply voltage across the output differential terminals. The first bias voltage is applied to the control terminals of the first pair of over-voltage protection transistors. The transmit driver includes a second bias generator for generating a second (substantially fixed) bias voltage for the control terminals of the second pair of over-voltage protection transistors. The transmit driver may be configured to operate based on a 3.3V supply voltage provided by an HDMI sink, or based on a 1.8V supply voltage provided by a bridge chip.

Abstract: A node that stores a charge is discharged in two phases, starting with a current controlled phase where a current mirror sink controls the current sunk from the node, and then moving to a second phase where a resistive discharge is provided. A pull down device such as a transistor switches from its saturation mode in the first phase to its linear mode in the second phase. a discharge circuit implementing this method provides optimized area and control for the discharge process as compared with approaches that rely solely on current mirroring or resistive discharging.

Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch, a high side power switch, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a receiver input reset circuit configured to simultaneously receive first and second signals, wherein the first signal corresponds with the high side power switch being turned on, wherein the first signal corresponds with the high side power switch controller turning on the high side power switch, wherein the second signal corresponds with the high side power switch controller turning off the high side power switch, and wherein the receiver input reset circuit is further configured, in response to the first and second signals, to prevent the high side power switch from becoming non-conductive.

Abstract: An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.

Abstract: A technique validates results from a circuit simulation estimation program. The technique determines whether the estimated results satisfy Kirchhoff's current law (KCL), Kirchhoff's voltage laws (KVL), and power conservation for the original circuit. A reporting tool shows the validation results and may be customized by the user. The tool can show in the original circuitry where the estimated results may be inaccurate.

Abstract: A transmitter (TX) circuit harvesting power from a power supply of a receiver (RX) circuit is disclosed herein. The TX circuit for data transmission over a differential channel comprises a driver circuit coupled with the differential channel across a first pair of resistors. One terminal of each resistor of the first pair coupled together at a common mode voltage node. The differential channel is series terminated at the RX circuit by a second pair of resistors to a power supply node of the RX circuit. The driver circuit includes a differential pair and a current source drawing current from the power supply node of the RX circuit. A pre-driver circuit coupled with the driver circuit provides an output of the pre-driver circuit as an input to the driver circuit. At least the pre-driver circuit is powered from the common mode voltage node of the driver circuit.

Abstract: A gate driving and modulating circuit, for reduced flicker on a display, includes a first discharge circuit and a plurality of interconnected gate drivers. The plurality of gate drivers is electrically coupled to ground through the first discharge circuit. Each of the plurality of gate drivers includes a second discharge circuit. The gate driving circuit performs a chamfering of a gate signal by being simultaneously discharged through the first discharge circuit and the second discharge circuit.

Abstract: A circuit arrangement for controlling power transistors of a power converter includes a logic circuit configured to generate a pulse-width modulation (PWM) signal and a clock generator configured to generate a clock signal. A first and a second isolator are configured to galvanically isolate transmission of the PWM signal and the clock signal into a high-voltage portion of the power converter so as to produce a galvanically isolated PWM signal and a galvanically isolated clock signal. The first isolator for the PWM signal is configured transmit both DC voltage signals and AC voltage signals. A correction circuit is configured to correct jitter of the galvanically isolated PWM signal based on the galvanically isolated clock signal. The second isolator for the clock signal exhibits a jitter lower than that of the first isolator by a factor of at least two.

Abstract: A system includes a voltage surge protection circuit that receives a source voltage from a source. The voltage surge protection circuit includes a reference circuit to generate a reference voltage based on the source voltage when the source voltage exceeds a clamping voltage and a feedback control circuit to receive the reference voltage and clamp an output voltage to the clamping voltage when the voltage from the source exceeds the clamping voltage. A dynamic resistance of the feedback control circuit is substantially zero.

Abstract: One example discloses an apparatus for power management, including: a circuit having a first power-domain and a second power-domain; wherein the first and second power-domains include a set of operating parameter values; a circuit controller configured to incrementally sweep at least one of the operating parameter values of the first power-domain; a circuit profiler configured to derive a total power consumption profile of the circuit based on the circuit's response to the swept operating parameter value; wherein the circuit controller sets the operating parameter values for the first and second power-domains based on the total power consumption profile of the circuit.

Abstract: A bidirectional integrated CMOS switch is provided which is capable of switching voltages beyond the range of the supply and ground potentials. The switch is composed of NMOS and PMOS transistors as the switch conductor path, a diode bridge, and control circuitry to turn the switch on and off by means of low voltage logic, regardless of the voltages on the switch terminals. The device and method of the invention enables the switching of high voltage loads operating at arbitrary or floating voltages relative to the low voltage power supply and ground, and provides on/off control of the switch with ordinary low voltage logic levels. The invention provides bidirectional switching without conducting through the parasitic body diodes of the CMOS devices.

Abstract: Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.

Abstract: An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit.

Abstract: An illustrative driver embodiment supplies an electrical transmit signal to an emitter module in response to an input bit stream. The illustrative driver embodiment includes: a voltage supply node which may be powered via a parasitic series inductance; a transmit signal buffer that drives the electrical transmit signal with current from the voltage supply node, the electrical transmit signal including transitions at bit intervals as dictated by the input bit stream; and an auxiliary signal buffer that supplies an auxiliary signal with current from the voltage supply node to an auxiliary module having an input impedance matched to an input impedance of the emitter module, the auxiliary signal having a transition at every bit interval where the electrical transmit signal lacks a transition.

Abstract: The present disclosure provides a shift register unit, its driving method, a gate driver circuit and a display device. The shift register unit includes a pull-up circuit configured to pull up a potential at the pull-up node PU in accordance with a starting signal from a starting signal input end, a pull-down circuit configured to pull down the potential at the pull-up node in accordance with a resetting signal from a resetting signal input end, a first capacitor configured to bootstrap the potential at the pull-up node at a pull-up stage, a first noise reduction circuit configured to perform noise reduction on a signal from the output end of the shift register unit at a pull-down stage and a compensation circuit configured to compensate for the potential at the pull-up node at a touch stage in accordance with a touch switch signal from a touch switch end.

Abstract: A transmission driver impedance calibration circuit and method. A circuit is disclosed that includes: a controller for controlling a set of switches; a comparator having an output that is coupled to the controller; and a first comparator input coupled to: a first selectable node coupled between a first p-type adjustable resistor segment (PSEG) and an external resistor; and a second selectable node coupled between a pair of internal resistors; and a second comparator input coupled to: a third selectable node coupled between a second PSEG and a tcoil resistor, the tcoil resistor being further coupled in series to a n-type adjustable resistor segment (NSEG); and a fourth selectable node coupled between the tcoil resistor and the NSEG.

Abstract: A multi-chip package may include a plurality of semiconductor chips integrated in a single package and sharing one or more command pins. Each of the semiconductor chips may include: a command decoder suitable for decoding a command to generate a buffer enable signal, a mode enable signal, and a mode signal; a data input buffer suitable for buffering data to output internal data, in response to the buffer enable signal and a common test mode signal; a command controller suitable for receiving the mode enable signal to output a test mode enable signal by selectively blocking the mode enable signal based on the internal data and the common test mode signal; and a test controller suitable for generating the common test mode signal and a test mode signal, based on the test mode enable signal and the mode signal.

Abstract: When an input signal maintains a first level throughout a predetermined judgment time, a noise removal circuit asserts an output signal. When the input signal transits from the second level to the first level, a first timer starts time measurement. When the input signal transits to the second level after time measurement by the first timer, a second timer measures time during which the input signal continues at the second level. A judgment unit is configured such that (i) it holds the measurement time obtained by the first timer when the input signal transits to the second level, (ii) when the measurement time obtained by the second timer and the measurement time of the first timer thus held satisfy a predetermined relation, the first timer is reset, and (iii) when the measurement time obtained by the first timer exceeds the judgment time, the output signal is asserted.

Abstract: An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

Abstract: Various implementations described herein are directed to circuit. The circuit may include a first input stage having first devices and a first path for slow slew input detection. The circuit may include a second input stage having second devices and a second path for fast slew input detection. The circuit may include a separation stage that couples the second input stage to the first input stage during a first mode of operation so as to reduce power consumption of the circuit during slow slew input detection.

Abstract: A current mirror circuit that amplifies a reference current generated by a current source at a first magnification to supply a mirror current to a load circuit. The current mirror circuit includes a first transistor and a second transistor that share a power supply, and a drain potential mirror unit that amplifies the reference current at a second magnification to generate a first current, that amplifies a generated first current at a third magnification to generate a second current, and that supplies a predetermined potential determined based on the second current to a drain of the second transistor. The mirror current is supplied from the second transistor to the load circuit based on a potential of a gate of the first transistor determined based on the reference current.

Abstract: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

Abstract: An interface device may include a first transistor, a pull-up unit, a pull-down unit, a first power supply terminal, a ground terminal, an output signal terminal, and a bias unit. A first gate terminal of the pull-up unit is electrically connected to a source terminal of the first transistor. A drain terminal of the pull-down unit is electrically connected to a drain terminal of the first transistor. The first power supply terminal is electrically connected to a source terminal of the pull-up unit. The ground terminal is electrically connected to a source terminal of the pull-down unit. The output signal terminal is electrically connected to each of a drain terminal of the pull-up unit and the drain terminal of the pull-down unit. An output terminal of the bias unit is electrically connected, without any intervening transistor, to a gate terminal of the first transistor.

Abstract: Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.

Abstract: Systems and methods are described for a contention-free single-wire latch controller that includes first and second bidirectional signal pins (e.g., the L and R pins in the FIGS), a latch enable output pin (or signal), E, and a decision element (such as a NAND or a NOR gate). A first driving transistor may be coupled between the first bidirectional signal pin and a power rail. A second driving transistor may be coupled between the second bidirectional signal pin and the power rail. A first half-latch may be coupled to the first bidirectional signal pin. A second half-latch may be coupled to the second bidirectional signal pin.

Abstract: A voltage controller is provided that is connected to a voltage inducing circuit which is connected to a static random-access memory (SRAM) cell. The voltage controller comprises a voltage clamping circuit and a pull up circuit. The voltage clamping circuit comprises one or more transistors. The voltage clamping circuit is configured to inhibit a second voltage of a second signal at a second node of the voltage inducing circuit from exceeding a first specified voltage threshold so that a fifth voltage of a fifth signal at a fifth node of the voltage inducing circuit is inhibited from exceeding a second specified voltage threshold. The pull up circuit is configured to maintain the second voltage substantially equal to a specified pull up voltage. The fifth node is connected to the SRAM cell, and a voltage to which the SRAM cell is exposed is thereby controlled.

Abstract: A switching circuit is provided by using an FET with a low gate-source breakdown voltage. The switching circuit includes a PLDMOS with a gate-source breakdown voltage that is lower than a gate-drain breakdown voltage and an impedance converting circuit coupled to the source of the PLDMOS and configured to output substantially the same voltage as an input voltage from the source of the PLDMOS. An input impedance of the converting circuit is higher than an output impedance thereof. The switching circuit further includes a gate voltage generating circuit configured to switch voltage applied to the gate of the PLDMOS between a first voltage and a second voltage, wherein the first voltage is substantially the same as an input voltage from the converting circuit, and wherein a difference between the first voltage and the second voltage is lower than the gate-source breakdown voltage of the PLDMOS.

Abstract: Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed.

Abstract: Control logic for producing a digital input to a digital-to-analog converter (DAC) in a power converter system. The control logic selects from among a plurality of slew rates during a transition of an output voltage in response to a change in the desired setpoint, so that the output voltage transition follows a desired nominal slew rate. In an initial interval of the transition, a steeper slew rate than the nominal slew rate is selected by the control logic for the digital input to the DAC, until the digital input to the DAC exceeds the nominal slew rate by a first parameter value. At that point, a slew clamp is applied to advance the digital input at the nominal slew rate. Upon the digital input approaching the setpoint value to within a second parameter value, a flatter slew rate than nominal is applied.

Abstract: A signal transmission device of aspects of the invention can include a master circuit connected to the primary sides of first and second transformers and a slave circuit connected to the secondary sides of the first and second transformers. The master circuit sets one of first and second transmitting/receiving circuits for transmitting operation and the other for receiving operation according to a control signal, and detecting a leading edge and a falling edge of the control signal, transmits a pulse signal with the pulse interval changing after a predetermined period of time. The slave circuit detects the change of the pulse interval of the signal received through third and fourth transmitting/receiving circuits and according to the detection result, sets one of the third and fourth transmitting/receiving circuits for receiving operation and the other for transmitting operation.

Abstract: Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed.

Abstract: According to one embodiment, a semiconductor memory device includes a memory including a memory cell array, and an input/output pin configured to transfer data, a command, and an address from an external to the memory. The memory includes a termination circuit provided between the input/output pin and the memory cell array, and configured to supply a first voltage having a first amplitude in a first transfer mode and supply a second voltage having a second amplitude in a second transfer mode, a first intermediate value of the first amplitude being different from a second intermediate value of the second amplitude.

Abstract: A non-volatile storage system includes an impedance code calibration circuit. The device has a first variable impedance circuit and a second variable impedance circuit coupled to a calibration node. The device has a control circuit configured to access a previous impedance code for a previous impedance calibration and to divide the previous impedance code into a main impedance code and a remainder impedance code. The control circuit is configured to perform a search for a new impedance code starting with the main impedance code applied to the first variable impedance circuit while maintaining the remainder impedance code to the second variable impedance circuit. The control circuit is configured to add the final impedance code for the first variable impedance circuit with the remainder impedance code to produce a new impedance code for the impedance calibration.

Abstract: A gate driver on array circuit and a liquid crystal display device are disclosed. The Nth-level GOA unit comprises: a pull-down unit; the pull-down unit comprises a first thin film transistor (TFT) which is connected to the input end of the (n+2)th-level high-frequency clock signal and a pull-down control unit respectively; the first TFT, a pull-up unit and a pull-up control unit are commonly connected to the pull-down point so as to pull-down the electrical potential of the pull-down point, wherein N is a positive integer greater than 3; n is positive integer.

Abstract: System and methods are provided for integrated circuit design. An initial layout including first circuit units is generated, at least part of the first circuit units obtaining power from a first power supply structure. Second circuit units that obtain power from a second power supply structure are determined, the second circuit units being included in the first circuit units. The second circuit units are grouped. The grouped second circuit units are connected to form one or more grids. The one or more grids are connected to the second power supply structure.

Abstract: A semiconductor device is provided which has a driving circuit operable to drive a circuit that has a delay, the semiconductor device including: an auxiliary driving circuit operable to accelerate drive of the driving circuit, which receives a drive signal of the driving circuit as an input signal.

Abstract: A system including a driver circuit. The driver circuit is configured to provide first output signals in a first mode for electrical signaling and second output signals in a second mode for optical signaling. The driver circuit is configured to provide the first output signals in the first mode with at least one of a lower frequency and higher power and the second output signals in the second mode with at least one of a higher frequency and lower power.

Abstract: Disclosed are a USB peripheral apparatus capable of reducing transmission power of a transmission terminal circuit by significantly increasing resistance values of terminations provided at the transmission terminal circuit and a reception terminal circuit as compared with a specific impedance value of a transmission line, and a transmission power reduction method thereof.

Abstract: The present invention discloses a gate driver which employs gate pulse modulation technology for improving an image quality, a driving method thereof, and a control circuit of a flat panel display device employing the gate driver. The gate driver is configured to modulate a gate pulse therein, and output the modulated gate pulse.

Abstract: An anti process variation self-adjustable on-chip oscillator has been disclosed according to the present invention. The on-chip oscillator includes the following components integrated on a same chip: a reference oscillation unit for producing reference pulse; an oscillation unit to be adjusted for producing output pulse; and a self-adjustable logic control unit for receiving the reference pulse and output pulse, and for transmitting a corresponding adjustment signal to the oscillation unit to be adjusted based on the received reference pulse and output pulse to control the oscillation unit to be adjusted to perform the frequency adjustment to the output pulse. The reference pulse required for adjusting the frequency can be generated by the reference oscillation unit integrated on-chip, so that self-adjustment can be achieved on-chip, decrease the cost of the chip compared with off-chip adjustment.

Abstract: A method of programming a storage device includes determining, at a controller of the storage device, that a first program mode of a plurality of program modes is to be entered in response to first information, wherein the first information includes a parameter associated with temperature, power consumption or input/output workload, and changing, using the controller, a program ratio of a first programming and a second programming of the storage device in the first program mode.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, and circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, memory devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: An integrated circuit is disclosed. The integrated circuit includes an input-output (IO) buffer circuit. The IO buffer circuit further includes first and second transistors coupled in series. The first transistor receives an input signal and the second transistor receives a pulsed voltage signal. Furthermore, a method to operate the IO buffer circuit is also disclosed.

Abstract: A semiconductor device includes a plurality of chips; a first through-chip via vertically passing through the chips, a power-saving unit suitable for being precharged to a precharge voltage during a precharge period; and a driving unit suitable for driving data using the precharge voltage outputted from the power-saving unit, during a driving period.

Abstract: An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.