Signal Sensitivity Or Transmission Integrity Patents (Class 326/21)
  • Patent number: 8314632
    Abstract: A core logic portion of a clocked digital circuit is switched to be powered by a standby mode power voltage lower than a normal mode power voltage when the circuit is switched into a low power standby mode (LPSM). The standby mode power voltage is too low relative to normal ground to deterministically drive a transition logic portion of the circuit. However, a special ground bus (GNDx) is provided in the transition logic portion and that special ground bus (GNDx) is pulled down to a negative voltage below normal ground when the circuit is switched into the low power standby mode (LPSM).
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: November 20, 2012
    Assignee: Lattice Semiconductor Corporation
    Inventor: Mitch Liu
  • Patent number: 8305871
    Abstract: Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted “aggressor” data to misalign transmitted signals from the perspective of “victim” channels. This misalignment moves the noise artifacts cross coupled to the victim channel away from sensitive sample times in the victim data, and consequently reduces the net effects of aggressor crosstalk on neighboring victim channels. Some embodiments reduce the effects of crosstalk by introducing static timing offsets to one or a plurality of aggressor transmitters, one or a plurality of victim transmitters, or some combination of aggressor and victim transmitters. Other embodiments dynamically alter the relative timing of aggressor and victim transmitters.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: November 6, 2012
    Assignee: Rambus Inc.
    Inventor: Jared L. Zerbe
  • Patent number: 8299821
    Abstract: An integrated gate driver circuit includes an output drive circuit and a voltage stabilizing circuit. The voltage stabilizing circuit is configured to stabilize an output voltage outputted by the output drive circuit thereby reducing the ripple of the output voltage.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: October 30, 2012
    Assignee: Hannstar Display Corp.
    Inventors: Yan Jou Chen, Hsien Cheng Chang
  • Patent number: 8289045
    Abstract: According to one general aspect, an apparatus may include a clock channel, a shielding tunnel, and clock repeaters. In various embodiments, the clock channel may be configured to carry the clock signal, and may include a portion of a metal layer of an integrated circuit. In some embodiments, the shielding tunnel may be configured to shield, in at least four directions, the clock channel from other signals, and may include portions of a at least three metal layers of the integrated circuit. The shielding tunnel may be connected to the positive and negative supplies in order to provide the required power for the clock repeaters.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: October 16, 2012
    Assignee: Broadcom Corporation
    Inventor: Afshin Momtaz
  • Patent number: 8283946
    Abstract: Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: October 9, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Seong-Hoon Lee
  • Patent number: 8269521
    Abstract: A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a first ID code and a second seed code according to a first seed code, and an ith ID code generator connected to the (i?1)th ID code generator generates an ith ID code and an (i+1)th seed code according to the ith seed code. The ID codes generated by the ID code generators are different to each other. Each of the activation logic units has an activation code. The ith activation logic unit receives the ith ID code from the ith ID code generator. The ith activation logic unit activates the ith chip when the ith ID code is complied with the activation code of the ith activation logic unit.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: September 18, 2012
    Assignee: Industrial Technology Research Institute
    Inventor: Ming-Hsueh Wu
  • Patent number: 8264252
    Abstract: The termination circuit includes first and second resistance circuits and is connected to a transmission line. The first resistance circuit is disposed on at least one of a pull-up side, which is between the transmission line and a power source, and a pull-down side, which is between the transmission line and ground, and has a negative property, by which an increase in an applied voltage decreases a resistance value of the first resistance circuit. The second resistance circuit is connected in parallel to the first resistance circuit. The second resistance circuit has a positive property, by which an increase in the applied voltage increases a resistance value of the second resistance circuit.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: September 11, 2012
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Maruyama
  • Patent number: 8253437
    Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: August 28, 2012
    Assignee: STMicroelectronics International N.V.
    Inventors: Paras Garg, Saiyid Mohammad Irshad Rizvi
  • Patent number: 8253436
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including a data transmitting circuit and a data receiving circuit that receives data transmitted from the data transmitting circuit. The data transmitting circuit includes a data output circuit that outputs the data or sets an output to a high impedance state, and a control circuit that outputs a control signal to the data output circuit so that the data output circuit outputs the data when the data transmitting circuit transmits the data, and the data output circuit keeps outputting data last output in the previous data transmission, during a predetermined period after the previous data transmission when the data transmitting circuit further transmits another data after transmitting the data.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: August 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Publication number: 20120206164
    Abstract: A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems.
    Type: Application
    Filed: March 22, 2012
    Publication date: August 16, 2012
    Applicant: ANALOG DEVICES, INC.
    Inventors: Eric GAALAAS, Mark CANTRELL
  • Patent number: 8228091
    Abstract: Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: July 24, 2012
    Assignee: Broadcom Corporation
    Inventors: Ark-Chew Wong, Joseph Aziz, Derek Tam, Kevin Chan
  • Publication number: 20120182043
    Abstract: Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 19, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Harry H. Dang, Vannam Dang
  • Patent number: 8222919
    Abstract: The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention comprises signal terminals and a common terminal. A receiving circuit delivers, when the receiving circuit is in the activated state, “output signals of the receiving circuit” determined each by a linear combination of the voltages between one of the signal terminals and the common terminal, to the destination. A termination circuit is such that, when it is in the activated state, it is approximately equivalent, for the signal terminals and the common terminal, to a (m+1)-terminal network such that, for small signals, the impedance matrix, with respect to the common terminal, of the (m+1)-terminal network is equal to a wanted non-diagonal matrix of size m×m.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: July 17, 2012
    Assignee: Excem
    Inventors: Frederic Broyde, Evelyne Clavelier
  • Patent number: 8213894
    Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: July 3, 2012
    Assignee: Intel Corporation
    Inventors: Frank O'Mahony, Bryan Casper, James Jaussi, Matthew B. Haycock, Joseph Kennedy, Mozhgan Mansuri, Stephen R. Mooney
  • Patent number: 8203377
    Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: June 19, 2012
    Assignee: SS SC IP, LLC
    Inventors: Robin Lynn Kelley, Fenton Rees
  • Patent number: 8203357
    Abstract: An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: June 19, 2012
    Assignee: Analog Devices, Inc.
    Inventors: Yoshinori Kusuda, Michael Coln, Gary Carreau
  • Patent number: 8199849
    Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: June 12, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Myeong Hoon Oh, Chi Hoon Shin, Young Woo Kim, Sung Nam Kim, Seong Woon Kim, Han Namgoong
  • Patent number: 8193828
    Abstract: A buffer apparatus for a communications bus comprises a driver circuit having an output. An amplifier circuit having an input is coupled to the output of the driver circuit. The driver circuit is arranged to generate, when in use, a drive signal having a waveform that comprises a step therein so as to substantially suppress generation by the amplifier circuit of a portion of an oscillation of an output signal.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: June 5, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thierry Cassagnes, Valerie Bernon-Enjalbert, Philippe Lance, Matthijs Pardoen
  • Patent number: 8195855
    Abstract: A bus system includes a plurality of stubs; a plurality of connectors, each of which is serially coupled between a corresponding one of the stubs and a corresponding one of memory modules; a plurality of first serial loads, each of which is serially coupled to a corresponding one of the connectors; and a plurality of second serial loads, each of which is serially coupled to characteristic impedance of a transmission line of a corresponding one of the stubs, wherein the first and the second serial loads are determined to be impedance matched at each transmission line terminal of the stubs.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: June 5, 2012
    Assignees: Hynix Semiconductor Inc., Seoul National University Industry Foundation
    Inventors: Deog-Kyoon Jeong, Suhwan Kim, Woo-Yeol Shin, Dong-Hyuk Lim, Ic-Su Oh
  • Patent number: 8191021
    Abstract: A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. Provision is made for applying the method to logic designs implemented in programmable logic integrated circuit devices.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: May 29, 2012
    Assignee: Actel Corporation
    Inventor: Sana Rezgui
  • Patent number: 8188766
    Abstract: The present systems and methods extend the frequency range of a clock signal generated with a phase-locked loop (PLL). The PLL receives a reference signal from a reference signal divider and a feedback signal from a feedback signal divider. The PLL generates an output signal that is forwarded to a programmable divider. The programmable divider includes control logic, core logic, and post-processing logic. The control logic synchronizes signals distributed throughout the system to prevent metastability. The core logic generates a divide-by-N waveform that is forwarded to the post-processing logic. The post-processing logic generates a half duty cycle clock signal responsive to the divide-by-N waveform.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: May 29, 2012
    Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.
    Inventors: Kok Leong Christopher Cheah, Cheng Huat Tan, Kim Yong Lee
  • Publication number: 20120126848
    Abstract: A multi-chip stacked system and a chip select apparatus are provided. The chip select apparatus includes n ID code generators and n activation logic units. The first ID code generator generates a first ID code and a second seed code according to a first seed code, and an ith ID code generator connected to the (i?1)th ID code generator generates an ith ID code and an (i+1)th seed code according to the ith seed code. The ID codes generated by the ID code generators are different to each other. Each of the activation logic units has an activation code. The ith activation logic unit receives the ith ID code from the ith ID code generator. The ith activation logic unit activates the ith chip when the ith ID code is complied with the activation code of the ith activation logic unit.
    Type: Application
    Filed: January 31, 2011
    Publication date: May 24, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventor: Ming-Hsueh Wu
  • Patent number: 8183887
    Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 22, 2012
    Assignee: Rambus Inc.
    Inventors: Vladimir M. Stojanovic, Andrew C. C. Ho, Anthony Bessios, Fred F. Chen, Elad Alon, Mark A. Horowitz
  • Patent number: 8183886
    Abstract: A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: May 22, 2012
    Assignee: Atmel Rousset S.A.S.
    Inventors: Eric Payrat, Majid Kaabouch
  • Patent number: 8170167
    Abstract: A communication system including a plurality of communication devices configured to operate according to a plurality of communication clock signals, respectively, wherein the plurality of communication clock signals are based on a common reference clock signal. The communication system further includes a phase-locked loop configured to generate an output signal in response to the common reference clock signal, wherein the output signal is in phase lock with the common reference clock signal; a signal division controller configured to generate a divider reset signal in response to a binary select signal; and a divider configured to generate one of the plurality of communication clock signals by performing frequency division of the output signal, wherein the divider reset signal controls a start time of the frequency division.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: May 1, 2012
    Assignee: Marvell International Ltd
    Inventor: Pierte Roo
  • Publication number: 20120086469
    Abstract: Skew is reduced by extracting the AC component of an input signal and superimposing it on a common reference voltage to produce a resulting voltage. The resulting voltage is provided as an input to a comparator, which compares it to the reference voltage to provide a final output. Thus, all signals fed to a system, in accordance with an embodiment, are referenced at the same DC level and hence, skew is reduced.
    Type: Application
    Filed: May 13, 2011
    Publication date: April 12, 2012
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Paras Garg, Saiyid Mohammed Irshad Rizvi
  • Patent number: 8149025
    Abstract: An exemplary gate driving circuit is adapted for receiving an external gate power supply voltage and an external control signal, sequentially generating multiple internal shift data signal groups and thereby sequentially outputting multiple gate signals. Each of the internal shift data signal groups includes multiple sequentially-generated internal shift data signals. The gate driving circuit includes multiple gate signal generating modules. Each of the gate signal generating modules includes a voltage modulation circuit and a gate output buffer circuit. The voltage modulation circuit modulates the external gate power supply voltage according to a corresponding one of the internal shift data signal groups and the external control signal, and thereby a modulated voltage signal is obtained. The gate output buffer circuit includes a plurality of parallel-coupled output stages. The output stages output the modulated voltage signal as a part of the gate signals during the output stages being sequentially enabled.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 3, 2012
    Assignee: AU Optronics Corp.
    Inventors: Wen-Chiang Huang, Chih-Sung Wang, Yu-Hsi Ho
  • Publication number: 20120074982
    Abstract: A digital electronic circuit includes: a plurality of sequential elements; at least one data-conducting path connecting an input sequential element to a destination sequential element; a clock outputting a clock signal on a clock tree for setting the speed of the sequential elements; a monitoring device receiving, as an input, at least one data signal traveling on a conducting path and arriving at a destination sequential element, the monitoring device including: a module for defining at least one detection window according to the clock tree; and a detector for detecting a transition of each data signal received during a detection window; and wherein each detection window is defined so as to enable the detection or anticipation of a fault corresponding to a violation of the rise time or the maintenance time of a data signal relative to a clock signal edge received by the destination sequential element receiving the data signal.
    Type: Application
    Filed: April 20, 2010
    Publication date: March 29, 2012
    Applicant: Commissariat à l'énergie atomique et aux energies
    Inventors: Bettina Rebaud, Marc Belleville, Philippe Lionel Maurine
  • Patent number: 8143911
    Abstract: In general, in one aspect, the disclosure describes an apparatus having an averager to receive differential output voltages of a transmitter and generate an average transmitter output voltage. A comparator is to compare the average transmitter output voltage to a reference voltage and generate a difference therebetween. An integrator is to integrate the difference between the average transmitter output voltage and the reference voltage over time. The integrated difference is fed back to the transmitter to bias the transmitter.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 27, 2012
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Feng Chen, Sanjay Dabral
  • Patent number: 8125240
    Abstract: The invention relates to an interfacing device for transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention comprises signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source and delivers, when the transmitting circuit is in the activated state, currents to the signal terminals, each of the currents being mainly determined by one or more of the input signals of the transmitting circuit, one or more of the currents being not mainly determined by only one of the input signals of the transmitting circuit. The balancing circuit is such that, when the transmitting circuit is in the activated state, the current flowing out of the common terminal approximates the opposite of the sum of the currents flowing out of the signal terminals.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: February 28, 2012
    Assignee: Excem
    Inventors: Frederic Broyde, Evelyne Clavelier
  • Patent number: 8115508
    Abstract: A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to control the slew rate of the output signal. A delay circuit is coupled to an output of the driver circuit, where the delay circuit has a delay proportional to a desired target slew rate of the driver output signal. A first comparator for detecting when the driver output signal rises through a specified level, and a second comparator for detecting when the driver output falls through a second specified level are included.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventors: William L. Bucossi, Albert A. DeBrita
  • Patent number: 8115509
    Abstract: A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is stored in a memory. The adjustment coefficient is used for reducing an occurrence amount of crosstalk arising between the specific signal wire and the two adjacent signal wires. An adjustment quantity calculation portion calculates an adjustment quantity representing a degree of decrease of a slew rate of the specific signal, based on the adjustment coefficient, the specific signal and the two adjacent signals. A driver adjusts the slew rate of the specific signal based on the adjustment quantity and to transmit one of the output signals corresponding to the specific signal.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: February 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shuichi Takada
  • Patent number: 8106685
    Abstract: A signal receiver includes a first input terminal, a second input terminal, a first transistor, a second transistor and a variable load. The first and the second transistors each include a gate electrode, a first electrode and a second electrode. The gate electrode of the first transistor is coupled to the first input signal terminal, the gate electrode of the second transistor is coupled to the second input signal terminal, and the variable load is coupled to the first electrode of the first transistor, where a resistance of the first variable load is adjusted to make a DC level at an output node of the signal receiver keep a constant value.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: January 31, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Wen-Chang Cheng
  • Patent number: 8106678
    Abstract: A semiconductor device including first and second power lines, and first and second circuit blocks coupled between the power lines. A first switching element is inserted between the first circuit block and at least one of the power lines and a second switching element is inserted between the second circuit block and at least one of the power lines. The first switching element is rendered conductive to allow the first circuit block to receive the power voltage through the first and second power lines while the second switching element is rendered nonconductive to prevent the second circuit block from receiving the power voltage through the first and second power lines, so that a leakage current flowing through the second circuit is suppressed.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 31, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi
  • Patent number: 8098079
    Abstract: Embodiments of a circuit for use with an inter-chip connection that has a variable complex impedance (which can be conductive, capacitive or both), a system that includes the circuit, and a communication technique are described. This inter-chip connection may be formed between a microspring or an anisotropic film and a metal connector on or proximate to a surface of a chip. Moreover, the circuit may mitigate signal distortion associated with the variable complex impedance. For example, the circuit may include an internal impedance that is electrically coupled in series with the metal connector, and that has an impedance which dominates the variable complex impedance over a range of operating frequencies. Separately or additionally, the circuit may be adapted to correct for the signal distortion.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: January 17, 2012
    Assignee: Oracle America, Inc.
    Inventors: Robert J. Drost, Robert D. Hopkins, Alex Chow
  • Patent number: 8093925
    Abstract: An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Sri N. Easwaran, Michael Wendt
  • Publication number: 20110291697
    Abstract: A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic circuit rails, wherein each of the logic circuit rails is electrically connected to the voltage rail and the ground rail. The logic circuit rail includes a logic unit and an auxiliary unit electrically connected to the voltage rail and the ground rail. The logic unit includes a logic voltage end electrically connected to the voltage rail and a logic ground end electrically connected to the ground rail. The auxiliary unit includes an auxiliary voltage end electrically connected to the voltage rail and an auxiliary ground end electrically connected to the ground rail. At least one of the width ratio between the auxiliary voltage end and the logic voltage end and the width ratio between the auxiliary ground end and the logic ground end is greater than 1.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 1, 2011
    Inventors: Ching-Jung YANG, Tsung-Ju Yu
  • Patent number: 8067955
    Abstract: This invention is a method of operating a system having multiple finite state machines where each finite state machine generating a ready signal when its operation is complete. This invention senses the multiple ready signals and waits until all the finite state machines generate the ready signal. This waiting can be accomplished with a precharge-conditional discharge circuit used for voting.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: November 29, 2011
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 8060771
    Abstract: Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 15, 2011
    Assignee: Dialog Semiconductor GmbH
    Inventor: Julian Tyrrell
  • Publication number: 20110267097
    Abstract: A semiconductor device whose operational state is switched between a test state and a normal operational state according to a logical value of a signal input from the outside is provided. The semiconductor device includes a first power line, a second power line, a switch that is controlled by a signal line to couple/isolate the first power line to/from the second power line, a control circuit that outputs a control signal, and a state switching circuit that drives the signal line to couple/isolate the first power line to/from the second power line according to a logical value of the control signal when the input signal is one of logical values, whereas the state switching circuit drives the signal line to couple the first power line to the second power line when the first signal is the other logical value.
    Type: Application
    Filed: July 15, 2011
    Publication date: November 3, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Kenichi KAWASAKI
  • Patent number: 8051313
    Abstract: An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch.
    Type: Grant
    Filed: April 28, 2008
    Date of Patent: November 1, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Bixia Li, Hugh Mair, Minh Chau, Alice Wang, Uming Ko
  • Patent number: 8049533
    Abstract: A receiver and a method for dynamically adjusting sensitivity of the receiver are provided. The receiver includes a detection unit and a receiving unit. The detection unit detects an input signal group, and outputs a detection result. The receiving unit receives the input signal group according to a sensitivity. Wherein, the receiving unit dynamically adjusts the sensitivity used for receiving the input signal group according to the detection result of the detection unit.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: November 1, 2011
    Assignee: Himax Technologies Limited
    Inventor: Shih-Chun Lin
  • Patent number: 8045410
    Abstract: A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, the current-limiting device is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: October 25, 2011
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ravindra M. Kapre, Shahin Sharifzadeh
  • Patent number: 8040813
    Abstract: An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.
    Type: Grant
    Filed: June 2, 2005
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Karl D. Selander, Michael A. Sorna, Daniel W. Storaska
  • Patent number: 8040155
    Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: October 18, 2011
    Assignee: East-West Innovation Corporation
    Inventors: Deanne Tran Vo, Thomas Jeffrey Bingel
  • Patent number: 8035419
    Abstract: A system comprises signal paths. There are first through n signal paths, n being a positive integer. A critical one of the first through n signal paths is based on being a respective one of the first through n signal paths having a slowest signal propagation and/or a path in which a signal propagates slower than a clock cycle. The critical one of the first through n signal paths comprises a first size of a standard cell including corresponding logic devices. The non-critical ones of the first through n signal paths comprise a second size of a standard cell including corresponding logic devices, the second size being smaller than the first size.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: October 11, 2011
    Assignee: Broadcom Corporation
    Inventor: Paul Penzes
  • Patent number: 8031733
    Abstract: A high-speed electrical data transmission system (10) includes a signal mixer (13) for receiving high-speed data from external network transceiver (12). The signal mixer (13) converts the data into an electrical current-fluctuating data signal. A signal processor (17) is located remotely of the signal mixer (13) and is connected electrically thereto by a simple/inexpensive cable (15) having only two operative conductors and receives the current-fluctuating data signal via the cable (15). The signal processor (17) converts the current-fluctuating data signal into a voltage-fluctuating data signal for distribution to a local area network.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: October 4, 2011
    Inventor: John Kam Ho Lee
  • Patent number: 8013628
    Abstract: A circuit having an active clock shielding structure includes a logic circuit that receives a clock signal and performs a logic operation based on the clock signal, a power gating circuit that switches a mode of the logic circuit between an active mode and an sleep mode based on a power gating signal, a clock signal transmission line that transmits the clock signal to the logic circuit, and at least one power gating signal transmission line that transmits the power gating signal to the power gating circuit and functions as a shielding line pair with the clock signal transmission line.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Hyun Lee, Jung-Yun Choi, Jae-Han Jeon, Kyung-Tae Do
  • Patent number: 8008927
    Abstract: A method and apparatus for ground bounce and power supply bounce detection in devices have been disclosed. In one case one input to a differential amplifier is coupled to a reference voltage and another input to the differential amplifier is coupled to a measurement point and the output of the differential amplifier is coupled to a flip flop. The flip flop has an output indicating when a bounce threshold is exceeded.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: August 30, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventor: Stanley Hronik
  • Patent number: RE43514
    Abstract: The invention relates to circuit elements and computing networks for resolving logical entanglement, in which the allowed logical value of a variable in a set of variables depends on the logical values of the other variables in the set. A circuit element according to the invention comprises two or more logically entangled bi-directional terminals, wherein each bi-directional terminal can assume any one of three logical states, which are a logical true state, a logical false state, and an indefinite state, in which state the bi-directional terminal accepts one of the logical true and logical false states as an external input from an external source. An entanglement logic resolves the logical state of the bi-directional terminals according to a predetermined set of logical entanglement rules between the bi-directional terminals.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: July 17, 2012
    Assignee: Intellectual Ventures I LLC
    Inventor: Pentti Haikonen