Abstract: One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed.

Abstract: A system includes analog supply circuitry providing first and second analog potentials. A switch module assumes first or second states to enable and inhibit transfer of an analog electrical signal from a source module to a user module based upon a driving electrical signal. A driving device drives, based upon the driving electrical signal, a control terminal of the switch module, allowing the switch module to assume the first or second state. The driving device allows the switch module to make a first driving transition from the first state to the second state, and a second driving transition from the second state to the first state. The driving device alternately connects the control terminal to a first reference potential, during the first state, and to a second reference potential, during the second state.

Abstract: A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.

Abstract: A system according to one embodiment includes input stage circuitry configured to receive input data; output stage circuitry configured to generate buffered output data based on said received input data, said output stage circuitry comprising a first switch and a second switch, wherein said first switch comprises a first gate configured to control said first switch through an inverted gate signal and said second switch comprises a second gate configured to control said second switch through a non-inverted gate signal; first feedback inverter circuitry configured to enable pull-up of said second gate based on an input to said first gate, said first feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-up enable; and second feedback inverter circuitry configured to enable pull-down of said first gate based on an input to said second gate, said second feedback inverter circuitry is further configured to provide an adjustable transition thresho

Abstract: Disclosed herein is a device that includes a replica buffer circuit that drives a calibration terminal, a reference-potential generating circuit that generates a reference potential, a comparison circuit that compares a potential appearing at the calibration terminal with the reference potential, and a control circuit that changes an output impedance of the replica buffer circuit based on a result of a comparison by the comparison circuit. The reference-potential generating circuit includes a first potential generating unit activated in response to an enable signal and a second potential generating unit activated regardless of the enable signal, and an output node of the first potential generating unit and an output node of the second potential generating unit are commonly connected to the comparison circuit.

Abstract: Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.

Abstract: A system is provided with a digital complementary-metal-oxide-semiconductor (CMOS) device and a noise cancellation circuit. The CMOS device has a first interface to accept a binary logic input signal, a second interface to accept a source current, a third interface to supply a binary logic output signal, and a fourth interface connected to a first dc voltage (e.g., ground) to sink current. A first resistor is interposed between a second dc voltage (e.g., Vdd), with a potential higher than the first dc voltage, and the second interface of the CMOS device. The noise cancellation circuit has a first interface connected to the second dc voltage. The noise cancellation circuit high pass filters ac noise on the second dc voltage, amplifies the filtered noise, and supplies the amplified noise at a second interface connected to the second interface of the CMOS device.

Abstract: A power gating circuit responds to a power enable signal to apply and withhold power to a MMIC. The gating circuit includes an OR gate and an AND gate, each coupled to the gate of a FET for controlling its conduction. One of the two FETs sources current to a load, and the other discharges the load. The gates are coupled so that the sourcing and discharge FETS are never turned ON simultaneously.

Abstract: The present invention relates to an integrated electronic circuit including elements enabling to implement a logic function and means for attenuating the sensitivity of said elements to external disturbances, said attenuation means being disconnectable during phases of intentional modification of the state of said elements.

Abstract: A terminal resistor apparatus includes an input-side switch, an input-side terminal resistor, an output-side switch, and an output-side terminal resistor. When a plurality of the terminal resistor apparatus are connected, the input-side switch of the first terminal resistor apparatus will be conducted so that the input-side terminal resistor will be connected, but the output-side switch will not be conducted so that the output-side terminal resistor will not be connected. The input-side switch of the last terminal resistor apparatus will not be conducted so that the input-side terminal resistor will not be connected, but the output-side switch will be conducted so that the output-side terminal resistor will be connected. The input-side switches of the other terminal resistor apparatus will not be conducted so that the input-side terminal resistors will not be connected, and the output-side switches will not be conducted so that the output-side terminal resistors will not be connected.

Abstract: A repeater circuit is disclosed. The repeater circuit includes an input circuit coupled to receive a data input signal and a clock signal, and an output circuit configured to, when activated, drive an output signal on an output node. The input circuit is further configured to activate the output circuit in order to initiate a logical transition of the data output signal. A deactivation circuit is configured to deactivate the output circuit at a delay subsequent to activation. A latch is coupled to the output circuit and it is configured to change a latch output state responsive to activation of the output circuit. The latch is configured to hold a state of the output node subsequent to deactivation of the output circuit. The input circuit is configured to activate the output circuit dependent on the clock signal. The deactivation circuit is configured to deactivate the output circuit independent of the clock signal.

Abstract: A data output apparatus includes a driver driving unit configured to generate driving signals by using input data when a data output enable signal is enabled, a data driver unit configured to drive an output terminal to a level corresponding to the input data in response to the driving signals to generate output data, and an output data level control unit configured to open a current path to control a level of the output data, wherein the current path is different from a current path for driving the output terminal to a level corresponding to the input data.

Abstract: An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.

Abstract: A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal.

Abstract: Switching circuits, latches and methods are provided, such as those that may respond to an input signal that transitions from a first binary level to a second binary level. One such switching circuit may have a metastable state that is closer to a first voltage corresponding to the first binary level than it is to a second voltage corresponding to the second binary level. In other embodiments, the metastable state may be dynamically adjustable so that it is at one voltage before the circuit switches and at a different voltage after the circuit switches. As a result, the switching circuit may respond relatively quickly to the input signal transitioning from the first binary level to the second binary level.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: The termination circuit includes first and second resistance circuits and is connected to a transmission line. The first resistance circuit is disposed on at least one of a pull-up side, which is between the transmission line and a power source, and a pull-down side, which is between the transmission line and ground, and has a negative property, by which an increase in an applied voltage decreases a resistance value of the first resistance circuit. The second resistance circuit is connected in parallel to the first resistance circuit. The second resistance circuit has a positive property, by which an increase in the applied voltage increases a resistance value of the second resistance circuit.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: A method and apparatus for dynamically adjusting power of a transmitter is herein described. A transmitter transmits a pattern to a receiver at a differential voltage. The length of the pattern, in one embodiment, is selected to be a reasonable length training pattern, as not to incur an extremely long training phase. If errors are detected at the receiver in the pattern, the transmitter steps the differential voltage until errors are not detected in the pattern at the receiver. The differential voltage, where no errors are detected, is scaled by a proportion of a target confidence level to a measured confidence level associated with the reasonable length training pattern. As a result, a training phase is potentially reduced and power is saved while not sacrificing confidence levels in error rates in the data exchange between the transmitter and receiver.

Abstract: A leakage current reduction circuit comprising a transmission gate, a feedback channel and a controller is placed between a first device supplied with a first voltage potential and a second device supplied with a second voltage potential. The voltage potential mismatch between the first device and the second device may cause a leakage current flowing through the input stage of the second device. By employing the low leakage power detection circuit, a logic high state generated from the first device can be converted into a logic high state having an amplitude approximately equal to the second voltage potential.

Abstract: A Multi-Threshold CMOS NULL Convention Logic asynchronous circuit (MTNCL). The MTNCL circuit provides delay-insensitive logic operation with significant leakage power and active energy reduction. The MTNCL circuit is also capable of functioning properly under extreme supply voltage scaling down to the sub-threshold region for further power reduction. Four MTNCL architectures and four MTNCL threshold gate designs offer an asynchronous logic design methodology for glitch-free, ultra-low power, and faster circuits without area overhead.

Abstract: A semiconductor integrated circuit capable of reducing unnecessary current consumption includes a plurality of bus drive circuits for receiving data input, a common bus coupled to the bus drive circuits, and a bus holder coupled to the common bus. One of the bus drive circuits is selected as the selected bus drive circuit. When a logical value corresponding to the data input to be output is the same as a logical value that has been held by the bus holder and output to the common bus, the selected bus drive circuit stops outputting the logical value corresponding to the data input to the common bus. With this configuration, it is possible to eliminate the unnecessary output of the selected bus drive circuit, and to reduce unnecessary current consumption compared to the conventional semiconductor integrated circuit.

Abstract: Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed.

Abstract: A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level.

Abstract: A signal transceiver apparatus suitable for a wired signal transceiver system includes a differential signal transmitter, an impendence matching control module and a signal receiver. The signal transmitter has an output terminal which is connected to a transceiver wire. The signal transmitter includes a first impendence tuner and is used to receive a control signal so as to tune impendence of the first impendence tuner according to the control signal. Moreover, the impendence matching control module generates the control signal according to a compare signal and a lock signal. Besides, the signal receiver generates the lock signal and the compare signal according to a compare result between a current flowing through the first impendence tuner and a reference current.

Abstract: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

Abstract: An impedance adjustment circuit for adjusting a terminal resistance includes a resistance evaluation unit and a terminal resistor unit. The resistance evaluation unit is utilized for evaluating a ratio of an off-chip resistor and a basic resistor to generate a control signal by a successive approximation method. The terminal resistor unit is coupled to the resistance evaluation unit, and is utilized for deciding a number of shunt basic resistors to provide a matched terminal resistance according to the control signal.

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: An impedance adjusting device includes a calibration unit configured to generate an impedance code for adjusting a termination impedance value, a plurality of termination units configured to be enabled by resistance selection information and terminate an interface node in response to the impedance code, a resistance providing unit coupled in parallel to the plurality of termination units and configured to provide a resistance in response to the resistance selection information, and a selection signal generation unit configured to generate the resistance selection information according to a target impedance value.

Abstract: A chip is provided with a specific signal wire and two adjacent signal wires. Output signals based on a specific signal and two adjacent signals are transmitted to the specific signal wire and the two adjacent signal wires respectively. An adjustment coefficient is stored in a memory. The adjustment coefficient is used for reducing an occurrence amount of crosstalk arising between the specific signal wire and the two adjacent signal wires. An adjustment quantity calculation portion calculates an adjustment quantity representing a degree of decrease of a slew rate of the specific signal, based on the adjustment coefficient, the specific signal and the two adjacent signals. A driver adjusts the slew rate of the specific signal based on the adjustment quantity and to transmit one of the output signals corresponding to the specific signal.

Abstract: A design structure and more particularly to a design structure to minimize driver output slew rate variation. The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to control the slew rate of the output signal. A delay circuit is coupled to an output of the driver circuit, where the delay circuit has a delay proportional to a desired target slew rate of the driver output signal. A first comparator for detecting when the driver output signal rises through a specified level, and a second comparator for detecting when the driver output falls through a second specified level are included.

Abstract: A semiconductor device includes a slew rate controller configured to receive a mode register set signal and data and to activate a driving strength control signal for controlling the driving strength of a driving unit using the data in response to a code value of the mode register set signal. The driving unit is configured to pull a data output terminal up and down in response to the driving strength control signal.

Abstract: A semiconductor integrated circuit includes a macro connected between a first power supply line and a second power supply line to drive a load, and a power-supply-noise cancelling circuit connected between an input and an output of the macro to generate a current for canceling one of a current flowing from the first power supply line to the output of the macro and a current flowing from the output of the macro to the second power supply line, on the basis of a potential difference between the input and the output of the macro. The macro and the power-supply-noise cancelling circuit are mounted in a same chip.

Abstract: An output buffer circuit has a variable output drive strength, depending on a buffer enable signal. Multiple output buffer circuits have a variable combined output drive strength, depending on a set of buffer enable signals.

Abstract: A method for converting a repeater circuit from a dynamic repeater circuit to a static repeater circuit. The method includes disconnecting a feedback path coupled to a first stage of the dynamic repeater circuit and electrically shorting gate terminals of first and second transistors of a second stage to each other, wherein the transistors of the second stage are configured to drive an output signal on an output node. Disconnecting the feedback path and electrically shorting the gate terminals is performed by reconfiguring a plurality of selection devices in the repeater circuit from a first configuration to a second configuration. The repeater circuit includes at least one keeper configured to provide an output signal on the output node.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

Abstract: A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals.

Abstract: A device includes a first circuit and an adjustment circuit. The adjustment circuit performs an adjustment on impedance of the first circuit. The adjustment circuit discontinues the adjustment on impedance while the first circuit is in an activated state.

Abstract: Circuit with enhanced mode and normal mode is provided and described. In one embodiment, switches are set to a first switch position to operate the circuit in the enhanced mode. In another embodiment, switches are set to a second switch position to operate the circuit in the normal mode.

Abstract: Disclosed are a method, system and apparatus for an improved fail safe I/O driver with pad feedback slew rate control are disclosed. In one embodiment, a pad driver circuit includes a pad node, an NMOS component, a feedback capacitor between the pad node and a gate of the NMOS component to control slew rate across a range of capacitor loads, a switch circuit between the pad node and the feedback capacitor, and a signal generator to generate a signal to control the switch circuit. The switch circuit to maintain a main driver circuit and a pre-driver circuit of the pad driver circuit in a fail safe state when an integrated circuit that includes the pad driver circuit is in the fail safe state. The pad driver circuit may include a PMOS component.

Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: Capacitive node isolation circuitry in an integrated circuit eliminates the creation of hot spots (stored charge) on high capacitive nodes during a test of electrostatic discharge (ESD) protection circuitry of the integrated circuit or during any ESD event occurring while the integrated circuit is in a standby mode. The isolation circuitry includes a standby mode logic circuit responsive to a standby mode signal received at one of its inputs and provides an output signal to a gate of an active switching device located in a path between an external pin of the integrated circuit and the internal high capacitive node. The output signal keeps the active switching device turned off for the duration of the ESD test or ESD event. The standby mode logic circuit transparently passes an input logic signal to the active switching device whenever the integrated circuit is in a normal operating mode.

Abstract: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.

Abstract: A semiconductor integrated circuit includes a pre driver unit configured to receive a pre drive signal and a driving force control signal and output a main drive signal; a main driver unit configured to receive the main drive signal and output output data to an output terminal; a terminal connecting unit configured to receive a determination signal and connect to or disconnect from the output terminal in response to the determination signal; a terminal sensing unit configured to sense the output terminal and output a terminal state signal; and a driving force determining unit configured to receive a reset signal and the terminal state signal and output the driving force control signal.

Abstract: An integrated circuit (IC) includes a set of metastability-hardened storage circuits. Each metastability-hardened storage circuit may include: (a) a pulse width distortion circuit; (b) a first circuit powered by a nominal power supply voltage, and a second circuit powered by a higher-than-nominal supply voltage; (c) an inverter and a bias circuit, where the bias circuit provides a bias current based on an intermediate state of the inverter to resolve a metastable state of the inverter; or (d) a latch, and a dynamic bias circuit that causes current to be injected into the latch to resolve a metastable state of the latch.

Abstract: An impedance adjusting device includes: a calibration node; a comparison unit configured to compare a reference voltage with a voltage of the calibration node; a counting unit configured to generatean impedance code according to a comparison result of the comparison unit; a reference impedance unit having an impedance value according to the impedance code and connected to the calibration node; a storage unit configured to store the comparison result of the comparison unit upon the generation of the impedance code being completed; an interface node; and a termination unit configured to terminate the interface node, the termination unit including a plurality of parallel resistors configured to be turned on/off according to the impedance code, and a parallel resistor configured to be turned on/off according to a value stored in the storage unit.

Abstract: A semiconductor device includes a first circuit block, a second circuit block, and a data bus. The data bus is coupled between the first and second circuit blocks. A first data inverter on the data bus inverts a selected segment of data that is transferred onto the data bus. A second data inverter at an end of the data bus re-inverts the selected segment of data before the data is transferred off the data bus. The data that is transferred onto the data is not analyzed in order to determine the selected segment of data that is inverted.

Abstract: A semiconductor device includes: a driver that receives a power supply voltage and drives an external load with a driving capability; a measurement unit that measures a level of the power supply voltage; a code table that stores the level of the power supply voltage and code information for determining the driving capability of the driver; and a controller that reads the code information in accordance with the level of a measured power supply voltage in reference to the code table and controls the driving capability of the driver in accordance with the code information.