Abstract: A circuit for transmitting logic signals across a high voltage barrier has a logic signal buffer with true and complement state differential outputs. A binary flip-flop with set and reset inputs is further provided. A first coupling capacitor is coupled to the true buffer output and to the set input of the binary flip-flop. A second coupling capacitor is coupled to the complement buffer output and to the reset input of the binary flip-flop circuit.

Abstract: A semiconductor integrated circuit, a semiconductor integrated circuit control method, and a signal transmission circuit realizing optimization of the performance of a semiconductor integrated circuit and reduction of the power consumption. In the semiconductor integrated circuit, the semiconductor integrated circuit control method, and the signal transmission circuit, functional circuit blocks (400a to 400n) are composed of MIS transistors fabricated on an SOI structure silicon substrate and have at least one potential set including a high-potential side potential, a low-potential side potential, a substrate potential of a P-channel MIS transistor, and a substrate potential of an N-channel MIS transistor.

Abstract: A level shifter and method of level shifting between an input signal and an output signal which may realize improvement s in operating speed and reductions in power consumption. An example level shifter may include a pull-up signal generation unit outputting a pull-up signal at a voltage level that is a given voltage level higher than a voltage level of an input signal, a pull-up unit pulling-up an output signal in response to the pull-up signal to generate the output signal with a shifted level, and a pull-down unit pulling-down the output signal in response to the input signal.

Abstract: A device for shifting the level of a first signal of relatively low amplitude which is a function of a first supply voltage to a second signal of relatively high amplitude which is a function of a second supply voltage, comprising, between a first terminal of application of the second supply voltage and a first input terminal, a branch of two transistors of opposite types in series, having their junction point defining an output terminal, the respective control terminals of the transistors being connected to terminals of application of relatively high and low bias voltages by first resistive elements, a second input terminal, receiving the inverse of the signal applied on the first terminal, being connected to each of the control terminals of the transistors by first capacitive elements and the first input terminal being connected to each of the terminals of application of the bias voltages by second capacitive elements in series with second resistive elements.

Abstract: The present invention discloses a level shift circuit and a control pulse shaping unit therewith. A level shift circuit for transition of a low-voltage input signal into a high-voltage output signal, the circuit comprising two pairs of transistors and a control unit. Two pairs of transistors, wherein the transistors in one of the pairs are both turned on in response to the input signal so that a voltage on a reference voltage node is coupled to a gate of one of the transistors in the other pair; a control unit decoupling a reference voltage from the reference voltage node during a first phase, and partially and fully coupling the reference voltage to the reference voltage node respectively during a second and third phases.

Abstract: A semiconductor device according to an embodiment of the present invention includes an output stage circuit including a first conductive type first transistor and a second conductive type second transistor, the first conductive type first transistor being connected between a first power supply terminal and an output terminal, the second conductive type second transistor being connected between a second power supply terminal and the output terminal and having a leak current larger than that of the first transistor, and an input stage circuit outputting a logic value setting the first transistor to a non-conductive state and setting the second transistor to a conductive state in accordance with a logic circuit disable signal input when the output stage circuit is in a disable state.

Abstract: An apparatus includes a single-rail input connected to a low-voltage domain and a voltage-transition circuit connected to the single-rail input. The voltage-transition circuit is configured to convert a voltage of the low-voltage domain received via the single-rail input to a voltage of the high-voltage domain.

Abstract: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a signal on the third node in response to the signals on the first node and the second node.

Abstract: An analog level-shifting differential amplifier for providing signal amplitude and/or common mode adjustment is disclosed. In one example, a receiver system may include a first amplification stage that is powered, for example, via an I/O power supply (e.g., VDDIO) and a second amplification stage that is powered, for example, via a core logic power supply (e.g., VDD). Arranged between the first and second amplification stages may be the analog level-shifting differential amplifier. The analog level-shifting differential amplifier may include a set of variable impedance elements for controlling the output common mode and output signal swing of the level-shifting differential amplifier.

Abstract: The present invention discloses a semiconductor integrated circuit device and an on-die termination circuit. The circuit includes a level shifter for boosting an on-die termination control signal to a high voltage level; and a first NMOS transistor connected between a power voltage and a pad and terminating the pad to a first termination voltage level in response to the high voltage level. The on-die termination circuit has a reduced input capacitance.

Abstract: An active pull up configuration for data bus lines unaffected by integral pull up resistors within subsystems. The present application generally relates to digital systems comprising a plurality of power supply levels and data buses. More particularly, this invention relates to digital system comprising subsystems connected by common buses that require automatic charging of certain buses or lines.

Abstract: A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.

Abstract: A level shifting circuit for a semiconductor device comprises a controller, a level shifting portion, and a driving portion. The controller is adapted to level shift a power converting input signal having a first voltage level to generate a pair of control signals having different logic levels from each other. One of the pair of control signals has a second voltage level that is different from the first level. The level shifting portion is adapted to level shift an input signal having the first voltage level to generate a level shifter output signal having the second voltage level or a third voltage level depending on the respective logic levels of the pair of control signals. The driving portion is adapted to drive an output signal with the second or third voltage level based on the voltage level of the level shifter output signal.

Abstract: To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second inverters 300 and 200 of a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverter 300 is used as a level converting unit. A voltage level of a first control signal CS1 output from an output node no1 of the first inverter 300 is forcibly dropped down by a voltage dropping circuit CONT1 so as to accelerate the operation of the second inverter 200. As a result, the inversion of the level of an output signal of the first inverter 300 is accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverter 200 are reduced so as to suppress an increase in a circuit area.

Abstract: Described is an integrated circuit that causes an input signal having one signal mode with a high state, a low state and a transition state to be dynamically level shifted to another signal mode with a respective high and low state, while minimizing a duration of the transition state of the output signal, wherein the one signal mode and the another signal mode have respectively different high and low state levels.

Abstract: A level shifter is disclosed, which has an input control circuit, a high-level voltage supply and a step-down circuit. The high-level voltage supply provides a high-level voltage source. The step-down circuit is coupled between the input control circuit and the high-level voltage supply circuit, and includes a high-level control device and a low-level control device. The high-level control device can provide a step-down function for protecting the low-level control device. The low-level control device is control to switch by the control signal or the inverted control signal, thereby driving the high-level voltage source to output.

Abstract: A driving circuit comprising an input voltage source set, a reference voltage source, a voltage level shift unit, a logic unit, a safety unit, and an output voltage terminal. The input voltage source set provides an input voltage set. The reference voltage source provides a reference voltage. The voltage level shift unit raises one of levels of the input voltage set to a level of the reference voltage. The logic unit receives the reference voltage and the input voltage set and outputs a control voltage. The safety unit conducts the control voltage to a ground. The output voltage terminal receives the control voltage and outputs an output voltage.

Abstract: The circuit arrangement includes a first and a second input to supply a first and a second supply voltage and also an output. The circuit arrangement includes a first transistor, which is connected between the first input and the output, and a second transistor, which is connected between the second input and the output. The first and second transistors include a respective substrate connection coupled to a supply connection. In addition, the circuit arrangement includes a third and a fourth transistor, which are connected between the first input or the second input and the supply connection, and also a control circuit, which is coupled to the first and second inputs and to control connections of the first and second transistors.

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H- bridge.

Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.

Abstract: The present invention provides an integrated circuit capable of reducing a leak current and reliably holding data therein in a standby mode. A potential higher than a potential of a second source line is supplied to a first source line. A potential lower than a potential of a first ground line is supplied to a second ground line. A virtual source line and a virtual ground line are respectively connected to the second source line and the first ground line by switches in an operation mode and float thereby in the standby mode. Substrates of MOS transistors are respectively connected to the second source line and the first ground line by switches in the operation mode and connected to the first source line and the second ground line thereby in the standby mode. A gate circuit transmits an output signal of a data non-holding circuit to a data holding circuit in the operation mode and fixes an input signal of the data holding circuit in the standby mode.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: A voltage supply control circuit is arranged between a true ground voltage and a pseudo ground line. In an active mode, first and second control signals are at the “H” and “L” levels, respectively. In response to this, a first switch is turned on so that a first node is electrically coupled to a power supply voltage, and attains the “H” level. Further, a second switch is turned on to couple electrically the ground voltage to a second node. In a standby mode, the first and second control signals are at the “L” and “H” levels, respectively. In response to this, a third switch is turned on to couple electrically the first and second nodes together. Since the power supply voltage was electrically coupled to the first node according to the turn-on of the first switch in the active mode, the path of the control signal including the first node to the switch has accumulated charged charges.

Abstract: Embodiments of the invention provide an interface circuit that is capable of reducing the power consumption, which may be increased by a shoot-through current, and provide an electronic device having such an interface circuit. In one embodiment, an interface circuit exchanges signals with another electronic device via a signal transmission line. The interface circuit includes a switch for pulling up the signal transmission line and a switch for pulling down the signal transmission line. While a pull-up or pull-down is performed, the interface circuit detects the potential level of the signal transmission line to determine whether the signal transmission line is pulled down or pulled up by the other electronic device. If the signal transmission line is not pulled down/pulled up by the other electronic device, the interface circuit exercises pull-down/pull-up control.

Abstract: In a level conversion circuit, two P channel MOS transistors form a current mirror circuit. When an input signal rises from the “L” level to the “H” level, an N channel MOS transistor connected to a drain of one P channel MOS transistor is brought out of conduction to prevent a leak current from flowing through two P channel MOS transistors, which decreases a power consumption. In addition, when the input signal rises from the “L” level to the “H” level, a P channel MOS transistor connected to a drain of the other P channel MOS transistor is brought into conduction to fix a potential of a node of the drain of the other P channel MOS transistor to the “H” level, which prevents the potential of the node from becoming unstable.

Abstract: Provided is a replica bias circuit which is suitable for multi-layer stacked CMOS current mode logic (CML) and is stably used in application fields using a low power supply voltage. The replica bias circuit applies a reference voltage to gates of target transistors constituting an electronic circuit. The replica bias circuit includes a sub threshold voltage generator for maintaining a voltage difference lower than a threshold voltage of the transistor; and a replica path including devices designed by referring to dimensions of constituent devices forming a current flow path, the current flow path including the target transistors in the electronic circuit. With the replica bias circuit, multi-layer stacked CMOS current mode logic (CML) circuits can stably operate even at a low power supply voltage.

Abstract: A buffer circuit having enhanced overvoltage protection includes core buffer circuitry couplable to a first voltage source having a first voltage level. The core buffer circuitry is configured to receive a first signal and to generate a second signal which is a function of the first signal. The buffer circuit further includes a protection circuit coupled between the core buffer circuitry and a signal pad. The protection circuit is operative: (i) to clamp the first signal to about the first voltage level when a third signal received at the signal pad exceeds the first voltage level by a first amount; and (ii) to generate the first signal being substantially equal to the third signal when the third signal is less than or substantially equal to the first voltage level.

Abstract: A high voltage digital output driver with dynamically biased cascode transistors is disclosed. The cascode transistors are dynamically self-biased via capacitors from the output voltage. The dynamic self-biasing doesn't require any switching means. The output-voltage can be increased by adding additional self-biased cascode transistors. The static current consumption in low-state for each individual driver on a same chip is minimal because only one resistor string consuming static current is required for all similar output drivers.

Abstract: According to embodiments of the subject matter disclosed in this application, a wide input common mode sense amplifier may include a level shifter stage and an amplifier stage. The level shifter comprises a CMOS differential amplifier that has a rail-to-rail input common mode range. The level shifter accepts two input signals with a common mode voltage in a rail-to-rail range and produces two output signals with a stable common mode voltage. The differential amplifier amplifies the two output signals from the level shifter stage with high gain. The disclosed sense amplifier may be used to measure delay between two discrete time events.

Abstract: A logic circuit is disclosed that is tolerant of logic signals with voltages different from the voltage of the logic circuit power supply. In one embodiment, the logic circuit has an inverting amplifier therein, the amplifier having at least one input and an output and is powered by the power supply. A first transistor, in responsive to the output of the amplifier, biases the input of the amplifier to assure substantially no static current flows through the amplifier when a logic-low is present on the amplifier output. A second transistor couples at least one logic input of the logic circuit to the input of the amplifier. In one embodiment, the second transistor impedes static current flow from the first transistor, through the second transistor, to the logic input. Various other embodiments of the logic circuit include a latch/flip-flop, multiplexer, and a complex logic gate.

Abstract: A level shift circuit that shifts both the high potential level and the low potential level of an input voltage, a micro actuator and an optical switch using such a level shift circuit are disclosed. A CMOS inverter 11 connected to a +5 V power source and a 0 V power source provides, in response to an input signal, an output voltage whose H level is +5 V and whose L level is 0 V. A single channel MOS inverter 12 connected to a +15 V power source and the 0 V power source provides, in response to the output voltage of the CMOS inverter 11, an output voltage whose H level is +15 V and whose L level is 0 V. A single channel MOS inverter 13 connected to the +15 V power source and a ?15 V power source provides an output voltage whose H level is +15 V and whose L level is ?15 V. The inverter 12 has an NMOS transistor Q4 as a drive element. The inverter 13 has a PMOS transistor Q5 of the opposite conduction type as a drive element.

Abstract: A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit includes a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source. The switching circuit is controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit. The pull-up and/or pull-down circuit is controlled by the third logic circuit.

Abstract: The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven.

Abstract: A plurality of transistors are connected between an I2C bus operating at a first voltage level and an I2C bus operating at a second voltage level and a main control electrode of at least one transistor is connected to a first power supply terminal and a main control electrode of the other at least one transistor is connected to an intermediate level between the first voltage level and the second voltage level, whereby a withstand voltage required to a transistor of the bidirectional level shift circuit of the I2C bus can be lowered.

Abstract: A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between a first data storage node of the first and second inverters and an input signal swinging between the first voltage and a ground voltage. A second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

Abstract: A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals.

Abstract: A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and performing high-speed level shifting by increasing the speed of charging electric charges into or discharging electric charges from an output terminal of a differential amplification circuit included in the level shifter.

Abstract: A regulated cascode current source has a current source circuit. A level shifter circuit is coupled to the current source circuit. The level shifter circuit has a circuit for independently controlling a voltage on a cascode node.

Abstract: A level shifter circuit comprises a bias module that receives a first signal and that selectively outputs a selected one of a second signal and a third signal based on an operating frequency of said level shifter circuit. A programmable gain module receives a gain control signal, and generates a fourth signal based on said gain control signal and said selected one of said second signal and said third signal. A bias generation module communicates with said programmable gain module, receives said gain control signal, and generates a bias for said level shifter circuit based on said gain control signal.

Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.

Abstract: In a two-stage inverter circuit including an inverter circuit constituted by first and second FETs and an inverter circuit constituted by two FETs, a source and a gate of a third FET are connected to a first power source and a second power source, respectively. A drain of the third FET is connected to a source of the first FET. A source and a gate of a fourth FET are connected to the first power source and the second power source, respectively. A drain of the fourth FET is connected to a source of a seventh FET. A gate of the seventh FET is connected to the second power source, and a drain of the seventh FET is connected to a back gates of the first, third, fourth, seventh and fifth FETs. The drain of the third FET is connected to the drain of the fourth FET.

Abstract: An integrated circuit includes at least three separate power supply terminals, at least one for those portions of the circuit that must accommodate the widest signal-related voltage excursion, at least one for those that experience substantially smaller signal-related voltage excursions, and a common terminal.

Abstract: A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit blocks 41 through 48 that do not include a critical path, second circuit blocks 51 through 54 that include a critical path, first power supply wiring 25 that supplies a first power supply to first circuit blocks 41 through 48, and second power supply wiring 26 that supplies a second power supply of higher voltage than the first power supply to second circuit blocks 51 through 54, with second circuit blocks 51 through 54 being connected to second power supply wiring 26 by means of wiring areas 61 through 64 respectively, and being supplied with the second power supply.

Abstract: A drive circuit of a computer system is for driving a mode indicator. The computer system includes a first port and a second port. The mode indicator includes a first receiving end and a second receiving end. The drive circuit includes a first input end connected to the first port, a second input end connected to the second port, a first output end connected to the first receiving end, a second output end connected to the second receiving end. A power supply is connected to the first input end and the second input end via a first resistor and a second resistor respectively. The mode indicator is dichromatic and has two LEDs emitting non-matching colored light.

Abstract: A display device includes a pixel driver circuit. Each of level converter circuits in the pixel driver circuit has: an input terminal supplied with a signal swinging between a first voltage and a second voltage lower than the first voltage; a first first-conductivity-type transistor having a gate electrode coupled to the input terminal, and a source region coupled to ground; a second second-conductivity-type transistor having a gate electrode coupled to a drain region of the first transistor, a source region coupled to a power supply, and a drain region coupled to an output terminal; one circuit element among a diode, a resistor and a fourth second-conductivity-type transistor, coupled between the gate electrode of the second transistor and the power supply; a third first-conductivity-type transistor having a source region coupled to the input terminal, a drain region coupled to the output terminal, and a gate electrode supplied with a dc voltage.

Abstract: A driver circuit is improved in drive capability corresponding to a resolution increase for a CCD sensor while suppressing chip size of a driver circuit. A preceding-stage circuit, operating on VDD2 (>VDD) and VLOW2 (<VLOW), is provided in a stage preceding an output-stage circuit operating on VDD and VLOW. The output-stage has a transistor QPd that turns on when supplied with a gate voltage VLOW2 from the preceding-stage circuit, thus outputting, onto an output terminal Vout, a voltage VDD and a current according to a voltage Vgs (=VDD?VLOW2). In addition, a transistor QNd turns on when supplied with a gate voltage VDD2 from the preceding-stage circuit, thus outputting, onto an output terminal Vout, a voltage VLOW and a current according to a voltage Vgs (=VDD2?VLOW). Because these Vgs are greater than VDD?VLOW, the output-stage circuit can be improved in drive capability and transistor size be correspondingly suppressed.

Abstract: The signal amplifier has a source follower receiving an input signal, a voltage divider generating a bias voltage which is input to the source follower through a different path from the input signal, and an inverter connected in series in the subsequent stage of the source follower and having such characteristics as to compensate characteristics variation of the voltage divider due to manufacturing parameter.

Abstract: According to one exemplary embodiment, an inductor-tuned buffer circuit includes at least one input transistor for receiving a time varying input signal, where the at least one input transistor drives an output of the buffer circuit. The buffer circuit further includes a buffer inductor coupled to the output of the buffer circuit. The buffer circuit is utilized to drive a capacitive load through an interconnecting conductor, where the buffer inductor is situated in proximity to the capacitive load so as to cause a parasitic inductance of the interconnecting conductor to be less than, or much less than, the buffer inductor.