Abstract: Methods are disclosed for translating or shifting a voltage level of a single ended input. More specifically, the present invention provides a method of translating or shifting a voltage level that doesn't require a complementary input or an additional power supply if the complementary signal isn't available. One embodiment of the method of translating a voltage level of a single-ended input signal using at least one native transistor device having a threshold voltage less than 0V comprises outputting a first voltage level if the single ended input signal is in a first state. A second voltage level is output if the single ended input is in a second state.

Abstract: The present invention provides an output buffer providing multiple voltages including an arrangement of bootstrapping capacitors, and a charge replenishing mechanism which provides continuous pulses to the arrangement of bootstrapping capacitors, thereby, maintaining voltage on the bootstrapping capacitors.

Abstract: A method and apparatus is provided for a voltage translator for performing a voltage-level translation of a signal. The voltage translator of the present invention includes a first transistor that is coupled to a control signal. The control signal is in a first voltage range. The voltage translator also includes a first one-shot circuit driven by the first transistor. The first one-shot circuit is capable of providing a pulse. The voltage translator also includes a second transistor capable of receiving a complementary signal of the control signal. A first pair and a second pair of transistors are included in the voltage translator. Each pair of transistors is operatively coupled to the first and second transistors. The first and second pairs of transistors are adapted to provide a transition of a signal from a first voltage range to a second voltage range.

Abstract: A high voltage level shifter having a cost effective design that saves chip architecture and power. The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to provide an inverted input signal. A first circuit portion couples to receive the inverted input signal and connects between the first power supply rail and a second power supply rail for converting a high voltage signal into a low voltage signal. The first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node. A second circuit portion couples to receive the input signal and connects between the first power supply rail and a second power supply rail for converting a low voltage signal into a high voltage signal.

Abstract: In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

Abstract: The present invention relates to a semiconductor circuit device including a logic circuit and a signal line driving circuit. The logic circuit is operated at high supply voltage and outputs a signal with a high voltage amplitude. The signal line driving circuit receives a lower supply voltage and has a low-threshold transistor. With the above configuration, a signal can be transmitted at a high speed with a low voltage amplitude and low power consumption. Thus, the semiconductor circuit device including the signal line driving circuit can reduce operating current and can be operated with a low amplitude and low standby current at a high speed.

Abstract: An input circuit (a first transistor pair) that receives complementary input signals is connected to a latch circuit (a second transistor pair) that converts the amplitude of an input signal into second amplitude higher than first amplitude. A current mirror circuit (a third transistor pair) is disposed between the latch circuit and a high-level power supply line. The current mirror circuit makes a source voltage of the second transistors being turned on lower than the source voltage of the second transistors being turned off. The second transistors being turned on are likely to be turned off although the on-current of corresponding first transistors is low. To the contrary, the second transistors being turned off are likely to be turned on. Accordingly, even when a voltage of a high logic level of an input signal is low, the level conversion circuit can surely operate without malfunction.

Abstract: A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit (10) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting (18, 20) its value relative to a known reference (16). Portions of the I/O pad circuit are selectively enabled in response to the detected I/O supply voltage. By selecting the ratio of P-channel and N-channel transistors, physical characteristics of the circuit are controlled. Examples of the controlled physical characteristics include slew rate, signal rise and fall times, and duty cycle control which is controlled by forcing all rising and falling edges to have a midpoint at the same point in time. Therefore a same I/O pad circuit may be optimally used in numerous applications regardless of the supply voltage value.

Abstract: An electrical system has a master circuit and an interface (I/F) circuit. The master circuit generates a master output signal. The I/F circuit receives an I/F input signal and a flag signal and generates an I/F output signal for application to a slave circuit, wherein the I/F input signal is based on the master output signal, and the interface circuit generates the L/F output signal either dependent on or independent of the I/F input signal as indicated by the flag signal.

Abstract: Embodiments of the invention include apparatus with a level-up shifter including a comparator having a pair of cross coupled PFETs with sources coupled to an I/O power supply and gates coupled to each other's drain, and a differential pair of NFETs with sources coupled to ground and gates respectively coupled to a data input and an inverted data input; and first and second pull-up PFETs have sources coupled to a pull-up voltage and drains respectively coupled between the differential pair of NFETs and the pair of cross coupled PFETs. The cross coupled PFETs and differential pair of NFETs perform level translation of low swing logic levels at the data input to high swing logic levels on a drain of one of the cross-coupled PFETs, while first and second pull-up PFETs speed the level translation in response to the data input and the inverted data input.

Abstract: A system and method is provided for providing power managed common mode logic (CML) transmitters for use with main and auxiliary power sources. Power switch circuitry comprising two PMOS transistors switches the CML transmitter output circuit between a main power source node (VDD) and an auxiliary power source node (TXRAIL). A bias circuit biases the two PMOS transistors to place the main power source voltage on the auxiliary power source node (TXRAIL) when the value of the main power source voltage is nonzero. The bias circuit also biases the two PMOS transistors to remain off when the value of the main power source voltage on the main power source node (VDD) is zero.

Abstract: The circuit is to provide a type of level shift circuit that operates correctly even when the input timings of voltages from multiple power sources are different. Level shift circuit 10 that outputs the output signal of the high voltage source as a response to the input signal of the low voltage source has the following attribute: When feeding of the low voltage source is delayed with respect to feeding of the high voltage source, on the basis of the high voltage source, power-on-reset circuit 20 generates power-on-reset signal PWR. During the period before the input signal of the low voltage source is fed as a response to power-on-reset PWR, latch circuit 30 initializes the level shift circuit, and holds its output OUT at the low level.

Abstract: In a semiconductor device in which an applying voltage higher than a power supply voltage VDD is inputted to a terminal BUS, when the voltage VBUS is less than a voltage of the power supply voltage VDD plus a threshold voltage Vthp, a voltage obtained by subtracting a threshold voltage Vthn from the power supply voltage VDD is applied to the gate terminal G4 and the PMOS transistor P4 becomes conductive. The power supply voltage VDD is supplied to the gate terminal G2 to turn the PMOS transistor P2 off. When the voltage VBUS is equal to or higher than the voltage of the power supply voltage VDD plus the threshold voltage Vthp, the voltage VBUS is supplied to the gate terminal G4 to turn the PMOS transistor P4 off, and the PMOS transistor P3 conducts and supplies the voltage VBUS to the gate terminal G2 to turn the PMOS transistor P4 off. The voltage level is correctly maintained without an undesirable leak current from the terminal BUS regardless of the applying voltage VBUS.

Abstract: A level shifting circuit with a power monitor enable for mixed-voltage applications is described. The level shifter translates signals from a first power supply voltage domain to a second. The level shifter provides a known output state, rather than an undefined mid-rail state, when either of the power supplies for the voltage domains is not adequately powered. In addition, the level shifter is IDDQ (quiescent current) compliant when static, drawing negligible current from the power supply. The level shifter can be used with a power monitor circuit, which controls the level shifter during power-up with an enable signal.

Abstract: A circuit for voltage level translation with zero static current is disclosed for interfacing devices at one supply voltage with devices at another supply voltage. The translation is achieved by using a modified current mirror circuit such that the current mirror is effectively turned off when the output reaches a steady state condition.

Abstract: A semiconductor device includes a cell source line which supplies a voltage to logic circuits, a capacity source line which supplies a voltage to the cell source line, a control circuit source line, switches by which the cell source line is isolated from or connected to the capacity source line and the control circuit source line, and buffer circuits which drive signals which control the switches, respectively. When the system is activated, a potential is applied to the capacity source line for charging, after which the cell-to-capacity switch is turned on. Then, a voltage is applied to the cell source line, which allows a steep rise in voltage at the cell source line. As a result, charging time is reduced and flow-through current which flows through transistors constituting the logic circuit can be reduced as well.

Abstract: A circuit for shifting a level between two bi-directional signals having different voltage levels. The circuit includes a first analog switch including a first switching control terminal connected to first directional signal stage, a first input terminal connected to a first level of operating voltage, and a first output terminal connected to a second directional signal stage, for performing a switching operation for the first input terminal and the first output terminal based on a state of logic level of a signal from the second directional signal stage.

Abstract: A method and an apparatus are described for a voltage tolerant input buffer. An embodiment of an input buffer includes a differential circuit and a plurality of switches coupled with the differential circuit. The plurality of switches applies a voltage to the differential circuit in a first state and isolate the differential circuit from the voltage in a second state.

Abstract: A high speed voltage level translator having minimum power dissipation and reduced area, specifically in the sub 0.1 micron domain, includes a transistorized arrangement to receive a low voltage input signal and to control current in the translated high level voltage signal. The translator further provides a differential amplifier arrangement for receiving the low level voltage input signal and provides feedback signals to the transistorized arrangement thereby outputting a high level voltage translated signal.

Abstract: Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the output signals. An inverted signal of the output signal is connected to the node through an impedance (e.g., capacitor) that stores energy. The inverted signal pulls the node in the opposite voltage level direction compared to the coupling effect of the output signal, thereby leaving the reference voltage substantially unchanged. By selecting the capacitance of the capacitor equaling the parasitic capacitance between the node and the output of the output buffer, coupling may be reduced substantially.

Abstract: Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).

Abstract: In one embodiment a bus hold circuit decouples an inverter of the bus hold circuit from an operating voltage responsively to an input receiving a signal having a voltage that is approximately equal to or greater than the value of the operating voltage.

Abstract: A digital-to-analog converter has a plurality of current cells. Each of the current cells has a level shifter and a current source. The level shifter connects to a first power terminal and a second power terminal to convert a first input signal and a second input signal into a first output signal and a second output signal. The current source has two cascaded MOS transistors connected to the first power terminal in series, a first MOS switch having a gate for receiving the first output signal, and a second MOS switch having a gate for receiving the second output signal. A voltage level of the first power terminal is greater than a voltage level of the second power terminal. When one of the current cells operates, one of the first MOS switch and the second MOS switch of the current source is turned on and operates in a saturation region.

Abstract: A level shifter has a voltage converting circuit converting an input signal provided by a first power supply into an output signal provided by a second power supply, and a reset circuit outputting a reset signal when the first power supply is turned off. The voltage converting circuit has: first and second FETs which are cross-coupled; a first trigger FET connected to the second FET and triggering it in response to the input signal; a second trigger FET connected to the second FET in parallel with the first trigger FET; a third trigger FET connected to the first FET and triggering it in response to an inversion signal of the input signal; and a fourth trigger FET connected to the first FET in parallel with the third trigger FET. Any of the second and the fourth trigger FETs triggers corresponding one of the second FET and the first FET in response to the reset signal.

Abstract: According to some embodiments, provided are a static low-swing driver circuit to receive a full-swing input signal, to convert the full-swing input signal to a low-swing signal, and to transmit the low-swing signal, and a dynamic receiver circuit to receive the low-swing signal and to convert the low-swing signal to a full-swing signal. Also provided may be an interconnect coupled to the driver circuit and to the receiver circuit, the interconnect not comprising a repeater and to receive the low-swing signal from the driver circuit and to transmit the low-swing signal to the receiver circuit.

Abstract: A high voltage buffer module used in an input/output buffer circuit coupled between a high voltage circuit and a low voltage circuit, operates between a first supply voltage and its complementary second supply voltage. A pull-up module, coupled between the first supply voltage and an output node, outputs the first supply voltage to the output node, in response to an input signal. A voltage detection circuit provides the pull-up module with at least one bias voltage selected from a predetermined set of voltage levels, wherein the voltage detection circuit selects the bias voltage upon detecting a reduction of the first supply voltage.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power supply voltage terminal for receiving a second power supply voltage that is lower than the first power supply voltage. During a normal mode of operation, the second power supply voltage is not provided to the second latch. During a low power mode of operation data is transferred from the first latch to the second latch and the first latch is powered down. The data is retained by the second latch while in low power mode.

Abstract: A level shifter circuit includes a bias module that receives a first voltage value, that generates a second voltage value when an operational frequency of the level shifter circuit is less than a threshold, and that generates a third voltage value when the operational frequency is greater than or equal to the threshold. A programmable gain module generates a fourth voltage value based on the second voltage value when the operational frequency is less than the threshold and based on the third voltage value when the operational frequency is greater than or equal to the threshold. The bias module includes a load module that receives the first voltage value and that generates the second voltage value and a bypass module that receives the first voltage value and that generates the third voltage value. A gain value of the programmable gain module determines a voltage gain of the level shifter circuit.

Abstract: The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

Abstract: An adjustable level shifter with native and kicker transistors is provided. The level shifter provides high switching speeds, adjustable output voltage levels, and low jitter. The level shifter has first and second thick-oxide p-channel metal-oxide-semiconductor (PMOS) transistors, first and second thick-oxide native n-channel metal-oxide-semiconductor (NMOS) transistors, and first and second thin-oxide NMOS transistors. The first PMOS transistor, first native transistor, and first NMOS transistor are connected in series and the second PMOS transistor, second native transistor, and second NMOS transistor are connected in series. An input data signal and an inverted version of the input data signal drive the gates of the thin-oxide NMOS transistors. A node located between the first PMOS transistor and first native transistor is connected to an output data terminal. The kicker transistor is connected in parallel with the first PMOS transistor.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: To a level shift basic circuit having a CMOS configuration and composed of four transistors M1 through M4, a control circuit for preventing feed-through current through the transistors is added. Transitions of complementary data inputs Vin1 and Vin2 are made in a period in which n-MOS transistors M7 and M8 for control are turned OFF by changing a control input VS1 to an L level (switch-off period). In this switch-off period, each source of the n-MOS transistors M1 and M2 is disconnected from VSS. In addition, in the switch-off period, a control input VS2 is changed to an L level, thereby turning ON p-MOS transistors M5 and M6 for control. In a period in which the control p-MOS transistors M5 and M6 are ON, data outputs Vout1 and Vout2 are both precharged to VDD (precharge period).

Abstract: Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.

Abstract: A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.

Abstract: An input buffer for interfacing a high voltage signal received at an input node to a low voltage circuit comprising low voltage devices is provided. The buffer includes a threshold adjustment circuit including an inverter coupled to a threshold adjusted output node. The inverter includes low voltage devices and is coupled between a high supply voltage node and a ground node. The inverter includes a first and second transistors having biasing nodes coupled to a low voltage supply node of the low voltage circuit and coupled to the threshold adjusted output node. The adjustment circuit provides at the threshold adjusted output node an inverted signal corresponding to the high voltage input signal. The buffer also includes a level shifting circuit including low voltage devices and provides a low voltage signal corresponding to the high voltage input signal in response to said inverted signal.

Abstract: A level shifting circuit includes a level-shifting section responsive to an input logic signal, which varies between a first voltage level (e.g., ground) and a second voltage level (e.g., 2.1V). The level-shifting section provides an output logic signal at an output terminal. The output logic signal varies between the first voltage level and a third voltage level (e.g., 2.5V). The circuit also includes an enable/disable section with a first portion coupled between the level shifting section and a first reference voltage node (e.g., ground) and a second portion coupled between the level shifting section and the third reference voltage node. The enable/disable section causes the output terminal to be placed at a relatively high output impedance condition independent of the logic state of the input logic signal in response to a disable mode indication from an enable/disable signal.

Abstract: An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage, comprising: an inverter circuit receiving the first signal and being connected for its supply between said higher voltage and said lower voltage, one at least of these connections being performed via at least one diode, a conversion element supplied between said higher and lower voltages, and receiving the output of the inverter circuit and providing the second signal, a storage element capable of maintaining the output of the inverter circuit at said higher or lower voltage when the first signal is respectively equal to the low or high voltage.

Abstract: The present invention provides a high-voltage tolerant input buffer circuit including a first NMOS transistor having its source terminal connected to the input pin, its gate terminal connected to a first reference voltage and its drain terminal connected to a first output terminal; a second NMOS transistor having its gate terminal connected to said first reference voltage and its source terminal connected to said first output terminal; a first PMOS transistor having its gate terminal connected to the drain terminal of said second NMOS transistor, its drain terminal connected to a second reference voltage lower than said first reference voltage and its source terminal connected to a second output terminal; a second PMOS transistor having its drain terminal connected to the drain terminal of said second NMOS transistor, its source terminal connected to said second output terminal, and its gate terminal connected to a control voltage; and a third PMOS transistor having its drain terminal connected to said second

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A signal-level converter is provided between a first terminal and a second terminal. The first terminal is connected to a first logic circuit operating at a first supply voltage higher than a given reference voltage. The second terminal is connected to a second logic circuit operating at a second supply voltage higher than the first supply voltage. The signal-level converter has a switching transistor that forms a current passage between the first and the second terminals in response to a control signal supplied to a gate of the switching transistor and a bus-hold circuitry, provided between the switching transistor and either the first or the second terminal as the output terminal, the other being the input terminal, and configured to convert a voltage level of a signal transferred via the switching transistor into another voltage level at the output terminal. The bus-hold circuitry may have two bus-hold circuits between the input and the output terminals, for two-way signal transfer.

Abstract: A differential switching circuit has a first transistor connected between a first output node and a common node and a second transistor connected between a second output node and the common node. A switching driver generates first and second driving signals in response to an input data signal so as to complementarily drive the first and second transistors. A voltage level of at least one of the first and second driving signals is maintained so as to cause at least one of the first and second transistors to operate in a saturation region regardless of a voltage variation of at least one of the first or second output nodes when the at least one of the first and second transistors is turned on. Output impedance of the device is enhanced because the first and second transistors operate in the saturation region.

Abstract: A boost-biased level shifter is described. In the preferred embodiments of the present invention, a voltage divider circuit divides the high voltage applied on the receiver circuit that receives the input signal, a refresh and self-bias circuit maintains and refreshes a bias voltage that is high enough to turn on the transistors in the voltage divider circuit, and a voltage output circuit outputs a signal having the amplitude of a higher power supply source, which is higher than the input signal amplitude. The preferred embodiments can operate at input signals having a lower amplitude. The performance is improved.

Abstract: An integrated circuit for level-shifting voltage signals comprising an input/output pad, and an input/output circuit coupled to the output pad having a plurality of devices operating with a bias supply voltage operable to shift between the range of the bias supply voltage to the range of an input/output supply voltage that is higher than the bias supply voltage is provided. In addition, an integrated circuit comprises an input circuit coupled to an input pad operable to input shift signals from an input/output supply voltage range to a core supply voltage range, an output circuit coupled to an output pad operable to shift output signals from a bias supply voltage range to an input/output supply voltage range, and a core circuit coupled to the input and output circuits and having a gate dielectric thickness substantially similar to a gate dielectric thickness of the input circuit and the output circuit.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.

Abstract: A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

Abstract: A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.

Abstract: An output buffer having a first pull-up transistor and a first pull-down transistor connected in series between two nodes of a power supply, their common connection node being connected to the output node. A logic circuit receives an input signal at a logic level and controls the voltage at the gates of the first pull-up transistor and the first pull-down transistor to provide the logic level at the output node. A second pull-up transistor and a second pull-down transistor are connected in series between the two nodes of the power supply, their common connection node being connected to the output node. A control circuit provides an output indicating when the supply voltage is below a predetermined level.

Abstract: A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in parallel with the activation of the clocked inverter. The power consumption of and the area occupied by a level conversion circuit converting a voltage amplitude of the input signal are reduced without deteriorating a high-speed operating characteristics.

Abstract: A level shifter for use in a semiconductor device, includes: a first transferring unit for transferring an input signal to an inverted output node in response to a negative voltage; a second transferring unit for supplying a power supply voltage to an output node in response to the input signal; and a third transferring unit coupled to the inverted output node and the output node for supplying the negative voltage to the output node in response to an output of the first transferring unit.