Abstract: A voltage level shift circuit includes a first stage which receives an input signal having voltage levels Vcc and Vss, where Vcc>Vss, and which outputs complementary first and second intermediate signals, wherein the complementary first and second intermediate signals have voltage levels VIhigh and VIlow, where VIhigh>VIlow; and a second stage which receives the first and second intermediate signals, and which outputs complementary first and second output signals, wherein the complementary first and second output signals have voltage levels VOhigh and VOlow, where VOhigh>VOlow, wherein VIhigh>VOhigh or VIlow<VOlow, and wherein VOhigh>Vcc and VOlow<Vss.

Abstract: A voltage translator circuit capable of operating at high speed, saving the power consumption, and forming to have a smaller circuit area. When the output level of a decoder 110 is changed from the potential GND to the potential VDD, a pMOS transistor 125 is turned off, and the gate of nMOS transistor 124 comes to have a high impedance. Because of this, the self-boost effect acts on the gate of the nMOS transistor 124 to push up the source potential of the nMOS transistor 124. Consequently, the gate potential of the pMOS transistor 122 is abruptly raised, and this pMOS transistor 122 is turned off at high speed. The pMOS transistor 122 being turned off at high speed, the penetration current flowing through the transistors 121 and 122 is reduced and the electric potential of the word line WL falls at high speed.

Abstract: A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a shifted voltage threshold. Effectively, this voltage translator circuit has very little supply current (Icc) after the device switches. Specifically, the voltage translator in accordance with the present invention includes a first and second inverter coupled in series between an input node and an output node. A third inverter connects between the output node and a fourth inverter. A first circuit portion that establishes the low-to-high switching point connects between the fourth inverter and the first inverter. A second circuit portion connects between the fourth and first inverter that will block the switching current from draining the voltage supply after the transition from low-to-high has occurred.

Abstract: A level shifter circuit for converting a logic signal with logic ‘1’ and ‘0’ levels at first high and low supply voltage levels to a signal with second high and low supply voltage levels. In particular, the second high and low supply voltage levels are greater than the first high and low supply voltage levels. The disclosed level shifter is configured such that the size of the preceding logic gate and circuitry within the level shifter can be reduced, facilitating its layout in pitch-limited areas. The level shifter also includes circuitry to decouple the output pull-up and pull-down paths to further facilitate state transitions and reduce crowbar current consumption.

Abstract: To reduce a voltage applied to a scanning line driving circuit. Buffer circuits respectively connected to gate electrodes of an N-channel transistor and a P-channel transistor which are connected to the scanning lines are provided and driving voltages are made different from each other, such that voltages applied to the buffer circuits are reduced.

Abstract: A core unit implements a predetermined function. An I/O unit controls input from and output to the outside. The core unit and the I/O unit are subject to independent control for supply of power. When power is turned off in the core unit, a signal output from the I/O unit to the core unit is fixed at a low level, while power is maintained in the I/O unit. A first level shifter and a second level shifter are provided between the core unit and the I/O unit and cancel a difference in power supply voltage level between the units. Power is turned off in the first level shifter and the second level shifter when power is turned off in the core unit.

Abstract: A voltage level shifter apparatus is provided. The voltage level shifter apparatus includes a first dynamic-bias generator, a second dynamic-bias generator, and a level supply circuit. The first dynamic-bias generator dynamically outputs a first bias signal, wherein the level of the first bias signal is determined in accordance with the received input data signal. The second dynamic-bias generator outputs a second bias signal, wherein the level of the second bias signal is determined in accordance with the received input data signal. Besides receiving the input data signal, the level supply circuit is further coupled to the first dynamic-bias generator and the second dynamic-bias generator for receiving the first bias signal and the second bias signal, and generating the output data signal in accordance with the input data signal, the first bias signal, and the second bias signal.

Abstract: A level shifter for use in a dual power supply circuit operating from a VDD power supply and a VDDH power supply greater than the VDD power supply. The level shifter indicates to a status circuit in the VDDH power supply domain that the VDD power supply is enabled. The level shifter detects when the VDD power supply is on and sets an enable signal to the status circuit. The level shifter also detects when the VDD power supply is off and clears the enable signal to the status circuit.

Abstract: An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set a gate bias of one gate of the one or more multi-gate transistors within the IC. More specifically, the gate bias generator sets the gate bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).

Abstract: A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a transistor within the level shifter core circuit to prevent the occurrence of a strong P-N fight state within the level shifter.

Abstract: A liquid crystal display (“LCD”) includes a first voltage shift circuit at a front stage of an inverter circuit. The first voltage shift circuit includes a second transistor having a source serving as an input, and a gate and drain connected to each other, and is operated as a diode, and a first transistor having a source connected to a power supply, a gate connected to a ground, and a drain connected to the drain of the second transistor. An input signal shifts voltage by a threshold of the second transistor, and then is input into the inverter circuit. Further, a first condenser is inserted between an input node and the gate of the second transistor. Therefore, the LCD has a level shift circuit with a small circuit area and a rapid response speed.

Abstract: A level shifter and a flat panel display comprising the same, with reduced power consumption. The level shifter includes: a first transistor to apply a first voltage to an output terminal in correspondence with a first input signal; a second transistor to apply a second voltage to an output terminal in correspondence with voltage applied between gate and source electrodes thereof; a third transistor to lower the voltage applied between the gate and source electrodes of the second transistor according to the first input signal; and a capacitor to keep the voltage applied between the gate and source electrodes of the second transistor to turn on the second transistor in correspondence with the second input signal.

Abstract: A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.

Abstract: A level shifter circuit includes first and second reference potential supply lines; first and second output potential supply circuits each connected between the first and second reference potential supply lines; first and second input lines; first and second output lines; and a stress test circuit which functions to, during normal operation, when the first input signal and the second input signal are input to the first input line and the second input line, output the first output signal and the second output signal having respectively different potentials for the first output line and the second output line, and during the stress test, when the first input signal and the second input signal are input to the first input line and the second input line, output signals having identical potentials from the first output line and the second output line.

Abstract: A level shifting circuit for a semiconductor device comprises a controller, a level shifting portion, and a driving portion. The controller is adapted to level shift a power converting input signal having a first voltage level to generate a pair of control signals having different logic levels from each other. One of the pair of control signals has a second voltage level that is different from the first level. The level shifting portion is adapted to level shift an input signal having the first voltage level to generate a level shifter output signal having the second voltage level or a third voltage level depending on the respective logic levels of the pair of control signals. The driving portion is adapted to drive an output signal with the second or third voltage level based on the voltage level of the level shifter output signal.

Abstract: A digital circuit such as a level shifter circuit includes a current mirror having first and second current supply transistors configured to provide an output signal to an output node based on an input signal. A leakage current control circuit is configured to maintain the first and second current supply transistors in an off state in response to the output signal. An output compensation circuit coupled to the output node is configured to maintain a voltage level of the output node based on a level of output signal.

Abstract: A level shift circuit having a latch function includes a precharging PMOS transistor MP1 which is turned on in a precharge period to interrupt a through current of an input stage, an NMOS transistor MN1 which inputs data and performs discharging in a data input period, and a transistor MP2 for holding data after level shifting. Thus, each of the transistors can have a minimum configuration. Since the level shift circuit has a latch function, it is possible to omit a circuit for latching input data, thereby reducing a circuit area.

Abstract: A level shifting multiplexing circuit provides an interface between a two conductor full duplex bus (two conductor bus) and a single conductor bidirectional half duplex bus (single conductor bus) where the two conductor bus is operates at a first supply voltage and the single conductor bus operates at a second supply voltage. A first switching circuit connected between the single conductor bus and the reception conductor of the two conductor bus is configured to provide a low logic signal to the reception conductor when a first switching voltage threshold is exceeded and to provide a high logic signal, otherwise. A second switching circuit connected between the single conductor bus and the transmission conductor of the two conductor bus is configured to provide a voltage less than the first switching voltage threshold when voltage at the transmission conductor exceeds a second switching voltage threshold unless a high logic signal is received on the single conductor bus.

Abstract: An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.

Abstract: A voltage selective circuit of a power source having a first voltage and a second voltage of the present invention includes a selective switch module, a high voltage bias module, a level shift module and a high voltage selective module. The selective switch module includes two first transistors. A power supply is selected from either the first voltage or the second voltage to output to integrated circuits. The high voltage bias module selects a higher voltage from the power supply and the power source of the first/second voltage to output to wells of the two first transistors. The level shift module includes two level shifters. The high voltage selective module selects a higher voltage from the first voltage and the second voltage as internal power to supply to the level shift module.

Abstract: A level conversion circuit that converts a signal outputted from a second internal circuit receiving a first power supply voltage to a signal of a level of a second power supply voltage having a voltage level different than the first power supply voltage to apply its output signal to a first internal circuit, is provided with a mechanism for cutting off a path passing a through current in the level conversion circuit when the first power supply voltage is cut off.

Abstract: A configuration circuit, comprising: a configurable storage element coupled between a ground voltage and a first voltage, said storage element generating an output; and a voltage conversion circuit coupled between the ground voltage and a second voltage at a lower level than said first voltage, said circuit further coupled to said output; wherein, the voltage conversion circuit generates a configurable control signal either at the ground voltage level or the second voltage level by configuring the storage element.

Abstract: A circuit architecture, or topology, that provides a level shifter which is substantially independent of the duty cycle of an input signal includes an H-bridge arrangement of field effect transistors, a pair of capacitively coupled inputs terminals connected to the gates of the high-side (i.e., connected to the positive power supply) transistors and a pair of voltage dividers to set the bias voltage at the gates of the high-side transistors, wherein one side of each voltage divider is coupled to the power supply node and the other side of each voltage divider is cross-coupled to the output node of the opposite side of the H-bridge.

Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

Abstract: A level shift circuit includes a capacitor element that has one terminal to which a logic input signal having a first logic amplitude is input; a logic output circuit that includes a first logic inverting circuit having a first logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element; and a second logic inverting circuit having a second logic inversion level with respect to an input terminal thereof connected to the other terminal of the capacitor element, and that inverts a logic output signal having a second logic amplitude when output polarities of the first logic inverting circuit and the second logic inverting circuit coincide with each other; and a third logic inverting circuit whose input and output terminals are connected to the other terminal of the capacitor element and that has a third logic inversion level with respect to the input terminal thereof connected to the other terminal of the capacitor element.

Abstract: A pre-buffer level shifter and an I/O buffer apparatus are provided. The pre-buffer level shifter includes a switchable current source, a current mirror, a buffer unit, a first clamping circuit and a second clamping circuit. Because of a clamping circuit inside a thin oxide MOS transistor device of the pre-buffer level shifter, the present invention can control the voltage swing of the signal for driving an output buffer within a suitable voltage range. Thus, the pre-buffer level shifter can correctly drive the output buffer made of thin oxide MOS transistor devices, increase the operating speed and ensure the reliability thereof.

Abstract: To provide a level shift circuit in which the margin of level shift operation is prevented from deteriorating when the potential difference between a first power supply and a second power supply is large. A level shift circuit for changing the signal level in a first logic circuit fed from a first power supply to the signal level in a second logic circuit fed from a second power supply, comprises: a pull-up and/or pull-down circuit fed from the second power supply for pulling up and/or pulling down the output of a level shift core circuit; and a control circuit fed from the second power supply, which receives level shift input signals and level shift output signals for controlling the pull-up and/or pull-down circuit.

Abstract: A semiconductor circuit including an input terminal, an impedance converting portion configured to receive an input signal from the input terminal and to output an output signal corresponding to the input signal, an input impedance of the semiconductor circuit being higher than an output impedance of the semiconductor circuit, a detecting portion connected to a node between the input terminal and the impedance converting portion, and configured to detect whether the input signal is higher than a predetermined threshold, and a variable impedance connected to a reference voltage and the node, an impedance of the variable impedance configured to decrease after the input signal is detected as higher than the predetermined threshold.

Abstract: An output stage structure includes first and second PMOS transistors and first and second NMOS transistors, wherein the MOS transistors are manufactured with a twin well process. The first PMOS transistor has a source coupled to a supply voltage (VDD), and a gate coupled to the first voltage. The second PMOS transistor has a source coupled to a drain of the first PMOS transistor, a gate coupled to the second voltage, and a drain coupled to an output pad. The first NMOS transistor has a drain coupled to the output pad, and a gate coupled to the third voltage. The second NMOS transistor has a drain coupled to source of the first NMOS transistor, a gate coupled to the fourth voltage, and a source coupled to ground.

Abstract: Equalization circuitry includes additional components to boost the performance of the circuitry to a higher-order response. The additional components are preferably controllably variable so that the response can be adjusted to perform a wide range of equalization tasks. For example, the equalization circuitry can be used on signals received from connections having a wide range of signal propagation characteristics and/or on signals having a wide range of data rates, including data rates that can be very high.

Abstract: A semiconductor integrated circuit device has an electrically rewritable non-volatile memory that operates with a first power supply, and a second circuit that operates with a second power supply having a voltage lower than the voltage of the first power supply. The second circuit has a gate oxide film which is thinner than the gate oxide file of the electrically rewritable non-volatile memory. A depletion NMOS transistor has a gate connected to the second power supply, a gate oxide film whose thickness is the same as that of the gate oxide film of the electrically rewritable non-volatile memory, and transmits a signal from an output terminal of the electrically rewritable non-volatile memory to an input terminal of the second circuit.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: A semiconductor integrated circuit includes an input circuit for taking in signals and an output circuit for outputting signals. The input circuit is so set that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition. The output circuit is so set that the driving force during the second half of signal transition is lower than the driving force during the first half of transition. Such setting that the input impedance during input signal transition is lower than the input impedance on other occasions than input signal transition reduces reflected waves during input signal transition. Such setting that the driving force during the second half of signal transition is lower than the driving force during the first half of transition suppresses production of reflected waves during the second half of signal transition.

Abstract: A circuit includes a first native or depletion n-channel Metal Oxide Semiconductor (MOS) transistor and a second native or depletion n-channel MOS transistor. The first and second native or depletion n-channel MOS transistors are capable of receiving an input signal. The circuit also includes a standard p-channel MOS transistor and a standard n-channel MOS transistor. The standard MOS transistors are coupled to the native or depletion n-channel MOS transistors and are capable of providing an output signal. The output signal is based on the input signal. Gates of the native or depletion n-channel MOS transistors may be thicker than gates of the standard MOS transistors. The native or depletion n-channel MOS transistors may be capable of blocking excessive voltage from the standard MOS transistors. The standard MOS transistors may be capable of selectively blocking the input signal from the output signal.

Abstract: There is provided a CML to CMOS converter comprising two current sources both connected between a first power supply, having a first potential, and a driving node, first and second push-pull drive stages each having a current path connected between a second power supply, having a second potential, and the driving node, and each having a control input for one half of a CML signal and an output node. Each of the two output nodes is connected to the control node of a respective one of the current sources, each current source being connected to decrease the current it supplies to the driving node if the potential of its respective output of the converter moves towards the potential of the first power supply.

Abstract: A level shifter circuit including first and second circuits and a protection layer. The first circuit receives an input signal and switches first and second nodes to opposite states within a first voltage range between first and second supply voltages. The second circuit switches the third and fourth nodes to opposite states within a second voltage range between third and fourth supply voltages in response to switching of the first and second nodes. The protection layer couples the first and second nodes to third and fourth nodes via respective first and second isolation paths. The isolation paths operate to keep the first and second nodes within the first voltage range and to keep the third and fourth nodes within the second voltage range. Isolation enables the use of thin gate-oxide devices for speed while extending the voltage range beyond the maximum voltage allowable for a single thin gate-oxide device.

Abstract: The level shifter comprises a coupling block, a PMOS switch, a first PMOS transistor and a second PMOS transistor. The coupling block receives a first signal and a second signal to generate a first control signal and a first reference voltage. The first signal and the second signal are of opposite phases. The PMOS switch is controlled by the first control signal to choose the first reference voltage or a second reference voltage to be a second control signal. The first PMOS transistor is controlled by the first control signal. The second PMOS transistor is controlled by the second control signal. The connection point between the second PMOS transistor and the first PMOS transistor outputs an output signal.

Abstract: A level shifter is provided. The level shifter includes a first input transistor, a second input transistor, a first bias transistor, a second bias transistor, a first switch transistor and a second switch transistor. At the time of change of the signal status, by raising the potential of the body terminal of the first input transistor, the threshold voltage is reduced so that the current flowing through the second input transistor is increased to shorten the time of the change of the signal status.

Abstract: An input buffer circuit achieving rail-to-rail operation maintains a uniform common mode output voltage even though an input signal having any voltage level is inputted. The input buffer circuit has a differential amplifier structure receiving two differential input signals. A first input part has a first inverter circuit into which a first differential input signal is inputted, and a second input part has a second inverter circuit into which the second differential input signal is inputted. The first inverter circuit has a first output node connected to a diode structure having an operating current twice the operating current of the first inverter circuit, and outputs a first output signal. Rail-to-rail operation is achieved, and a common mode output voltage is provided uniformly, with reduced current consumption.

Abstract: A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) require that the differential signals are never driven to ground. However, some non-compliant video transmitters drive differential signals to ground when disabled. External pullup resistors or internal pullup transistors in the bus switch chip are added to the bus signals from non-compliant transmitters to pull disabled signals above the 1.5-volt chip ground to prevent damage from signals below the chip's 1.5-volt ground.

Abstract: A system and method for providing a driver for a multi-voltage island/core architecture of an integrated circuit chip are provided. A complementary metal oxide semiconductor (CMOS) inverter is built with a high threshold voltage p-channel field-effect transistor (hi-Vt PFET) and a regular threshold voltage n-channel field-effect transistor (NFET), which uses the maximum positive voltage supply (Vdd) on the chip. The threshold voltage of the hi-Vt PFET is determined based on the maximum Vdd, the Vdd of the Voltage island/core that drives the CMOS inverter, and a subthreshold leakage current requirement of the hi-Vt PFET.

Abstract: A power supply circuit and a control method are provided, in which the original enable pad and output pad, or the enable pad and feedback pad are used to trim the output voltage of the power supply circuit without extra trim pads.

Abstract: An apparatus for coupling two circuits having different supply voltages is described herein.

Abstract: A level shifter apparatus and method for minimizing duty cycle distortion are provided. The level shifter includes a bank of comparators each having an associated threshold built into it. The comparators compare a difference in source voltages for two power domains to these built-in thresholds and output a signal indicative of whether the threshold is exceeded. The output signals from the comparators are provided to a thermometric decoder which generates control signals based on these output signals. The control signals are used to control stages in a level shifter for modifying the voltage output of the level shifter. Individual stages may be enabled to thereby monotonically modify the voltage output of the level shifter and thereby decrease a time required to achieve a voltage having a level that causes a state change in a driven circuit. As a result, duty cycle distortion is minimized and maximum operational frequency is increased.

Abstract: A system and method for reducing forward inadvertent biasing of a switch having a transistor. The gate of the transistor is connected to ground and a voltage source less than ground. A control signal of the gate is then applied to a level translator to compensate for the voltage applied to the gate.

Abstract: A signal transmitting system comprising a signal outputting unit and a signal receiving unit is provided. The signal outputting unit receives a first signal and outputs a second signal. The signal receiving unit receives the second signal and outputs a third signal. The signal outputting unit comprises an inverting device which receives the first signal and outputs a first inverted signal, and a signal driving device which receives the first inverted signal and outputs the second signal. The signal driving device comprises two NMOS transistors. The first NMOS transistor has a drain biased by a first voltage, and a gate receiving a control signal. The second NMOS transistor has a gate receiving the first inverted signal, a source biased by a second voltage, and a drain electronically coupled to the source of the first transistor. The drain of the second NMOS transistor outputs the second signal.

Abstract: An improved voltage tolerant protection circuit for input buffer comprising a transmission gate circuit receiving input from the pad for passing the input signal to the input of the input buffer, a control signal generator electrically coupled between the transmission gate circuit and the pad to provide a control signal for operating the transmission gate circuit, and an N-Well generation circuit electrically coupled between the pad and the transmission gate circuit, and also electrically coupled to the control signal generator for generating a bias signal for the transmission gate circuit and the control signal generator. Thus, the present invention provides a voltage tolerant protection circuit that prevents electrical stress on transistors, minimizes power supply consumption and transfers signals without any change in amplitude.

Abstract: Described is a level shifting device for high-frequency operation. The level shifting device includes first through fifth transistors. The first transistor has its gate connected to an input signal, its source connected to the voltage node at an lower voltage value, and its drain connected to an output signal. The second transistor has its gate connected to an inverted version of the input signal, its source connected to the voltage node at the lower voltage value, and its drain connected to an inverted version of the output signal. The third transistor has its gate connected to the drain of the second transistor and its drain connected to the drain of the first transistor. The fourth transistor has its gate connected to the drain of the first transistor, its drain connected to the drain of the second transistor, and its source connected to the voltage supply at an first upper voltage value.

Abstract: A voltage level translation circuit includes a first power supply voltage, a second power supply voltage, wherein the second supply voltage is lower than the first supply voltage, a low voltage input, wherein the low voltage input is referenced from the second supply voltage, a resistive element leaker transistor having a source and a drain, wherein the source is coupled to the first power supply voltage, a PMOSFET having a gate and a source, wherein the source is coupled to the first power supply voltage, and a pulse generator coupled to the gate of the PMOSFET, wherein the pulse generator is capable of controlling the operation of the PMOSFET.

Abstract: The present invention provides a level conversion circuit including first and second transistors, a clock terminal, first switch means, second switch means, and a capacitance element. The first and second transistors are of the opposite conduction types to each other connected in series between a first power supply potential and a second power supply potential. The clock terminal is inputted a clock signal. The first switch means is connected between the clock terminal and the gate of the first transistor and has an on state when a circuit operation control signal is in an active state. The second switch means is connected between the second power supply potential and the gate of the second transistor and has an off state when the circuit operation control signal is in an active state. The capacitance element is connected between the clock terminal and the gate of the second transistor.

Abstract: A photopolymerizable composition comprising an addition polymerizable compound, an N-aryl-.alpha.-amino acid and a photosensitizer capable of absorbing a light having a wavelength of 300 nm or more such as thioxanthones, isoalloxazines, coumarines, and the like is excellent in sensitivity to irradiated light and is suitable for preparing relief images, photoresists, etc.