Abstract: A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low voltage circuit outputs a low drive voltage or ground voltage. The high voltage circuit outputs a high drive voltage or a high reference voltage, which is supplied to an RS latch circuit via a potential adjustment circuit at a level equal to an output potential at the low voltage circuit. The RS latch circuit uses the output of the potential adjustment circuit when the input voltage shifts to a high level and uses the output of the low voltage circuit when the input voltage shifts to a low level.

Abstract: A semiconductor integrated circuit device which includes a logical circuit containing a MIS transistor on a semiconductor substrate, a control circuit for controlling a threshold voltage of the MIS transistor in the logical circuit, an oscillation circuit containing a MIS transistor on the semiconductor substrate, and a buffer circuit, the control circuit compares the frequency of the oscillation output and frequency of a clock signal to output a first control signal, the first control signal controls a threshold voltage of the MIS transistor of the oscillation circuit, and the buffer circuit is inputted with the first control signal to output a second control signal corresponding to the first control signal, the second control signal controlling the threshold voltage of the MIS transistor of the logical circuit.

Abstract: A power supply detection circuit biased by at least two power supply voltages for controlling a signal driver circuit. Upstream and downstream amplifiers, powered by upstream and downstream power supply voltages, respectively, process an original control signal to produce a differential signal via output signal electrodes. Capacitances coupling respective ones of the output signal electrodes to the downstream power supply voltage and the circuit reference potential discharge and charge respective ones of the output signal electrodes in relation to initial receptions of the upstream and downstream power supply voltages and original control signal, following which voltage clamp circuitry maintains such discharged and charged states pending reception of the original control signal in a predetermined state.

Abstract: An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

Abstract: A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

Abstract: A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least one transistor device having a first threshold voltage associated therewith. The voltage level translator circuit further includes a latch circuit operative to store a signal representative of a logic state of the input signal, the latch circuit including at least one transistor device having a second threshold voltage associated therewith, the second threshold voltage being greater than the first threshold voltage. A voltage clamp circuit is connected between the input stage and the latch circuit. The voltage clamp circuit is operative to limit a voltage across the input stage, an amplitude of the voltage across the input stage being controlled as a function of a voltage difference between the first and second voltage supplies.

Abstract: A mixed-voltage I/O buffer comprises an input circuit, an output circuit, an I/O pad, a pre-driver circuit coupled to the output circuit, two added coupled N-type transistors, and a dynamical gate-controlled circuit coupled to each gate of the two N-type transistors and the pre-driver circuit; one of the N-type transistors is coupled to the input circuit and the output circuit; the other N-type transistor and the dynamic gate-controlled circuit are together coupled to the I/O pad. Thereby, a mixed-voltage I/O buffer which receives 2×VDD-tolerant input signals and overcomes the hot-carrier degradation is realized.

Abstract: A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.

Abstract: Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.

Abstract: A semiconductor integrated circuit with low power consumption is provided. In one embodiment, the semiconductor integrated circuit includes a logic circuit portion that is connected between a first power line and a virtual ground line. The logic circuit portion includes at least one NMOS transistor having a first threshold voltage and at least one PMOS transistor having a second threshold voltage. The semiconductor integrated circuit further includes a first MOS transistor, which is connected between the virtual ground line and a ground voltage, where the first MOS transistor has the first threshold voltage and applies the ground voltage to the virtual ground line in an active state.

Abstract: An interface of the present invention includes a first inverter circuit that inverts a logic level of an input signal given to an external input terminal and outputs the inverted logic level, a second inverter circuit that outputs a potential in which a logic level of an output signal of the first inverter circuit is inverted, that is, a potential higher or lower than a logic of an input signal applied to the first inverter circuit by the amount of a predetermined potential, and a feedback path that positive-feedbacks an output signal of the second inverter circuit to the external input terminal. The interface circuit of the invention positive-feedbacks a potential of the output signal of the second inverter circuit and shifts the potential of the external input terminal in a floating state to an H or L level potential.

Abstract: For raising low voltage levels of a voltage range without over-broadening the voltage range, a first stage voltage level shifting circuit, which is capable of raising an upper bound of its input voltage range, is coupled to a second voltage level shifting circuit, which is capable of raising both an upper bound and a lower bound of its input voltage range. Therefore, a two-stage voltage level shifting module, which is generated by coupling the first voltage level shifting circuit to the second voltage level shifting circuit, is capable of providing appropriate voltages for external I/O devices having different biasing voltage ranges, where an upper bound and a lower bound of each of the provided biasing voltage ranges precisely indicates a digital logic 0 or a digital logic 1 indicated by a digital signal.

Abstract: A low leakage monotonic CMOS logic circuit and a method, a method of design and a system for designing such circuits. The circuit, including: one or more logic stages, at least one of the logic stages having a predominantly high input state or having a predominantly low input state; wherein the logic stages having the predominantly high input state, comprise one or more thin gate dielectric and high threshold voltage PFETs with respect to a reference PFET and one or more thick gate dielectric and low threshold voltage NFETs with respect to a reference NFET; and wherein the logic stages having the predominantly low input state, comprise one or more thick gate dielectric and low threshold voltage PFETs with respect to the reference PFET and one or more thin gate dielectric and high threshold voltage NFETs with respect to the reference NFET.

Abstract: A level shift circuit is used to receive a low-voltage signal to generate a corresponding high-voltage signal. The circuit has a first transistor of a first type, a second transistor of a second type, a third transistor of the second type and a fourth transistor of the second type. The first transistor has a gate receiving the low-voltage signal and a source receiving a first supply voltage. The second transistor has a source receiving a second supply voltage and a drain coupled to a drain of the first transistor. The third transistor has a source receiving the second supply voltage, a drain outputting the high-voltage signal and a gate coupled to a gate of the second transistor. The fourth transistor has a source and a gate commonly coupled to receive a third supply voltage, and a drain coupled to the drain of the third transistor.

Abstract: A printed circuit unit implementing with organic transistors is provided. The printed circuit unit includes an input signal circuit, a load circuit and a level shifter. The input signal circuit includes N serially connected organic transistors. When one of the serially connected organic transistors is cut-off, the signal input circuit is cut-off, so that the circuit is maintained to output a correct voltage level. The level shifter circuit includes an organic transistor having a gate for receiving the input signal. The organic transistor can also serve as a load for improving a gain of the level shifter.

Abstract: A buffer circuit (318) including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M4, M9) as the input device and a source follower, a second MOS transistor (M23, M22) as a transconductance amplifier device, and a third MOS transistor (M5, M8) as a folded cascode device. The first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage. The first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage. The buffer circuit has a very low input capacitance where the input capacitance does not vary with the buffer input voltage and other operating conditions, such as fabrication process, temperature and power supply voltage variations.

Abstract: In a logic circuit, a first switching device is connected between a first voltage and an output terminal through which an output signal is output. The switching device is selectively activated and deactivated based on an input signal. A second switching device is connected to a ground voltage and is selectively activated and deactivated based on the input signal. A control circuit outputs a control signal in response to the input signal. The control signal has a first voltage level during a first time period in which a state of the input signal changes, and has a second voltage level during a second time period in which a state of the input signal is constant. The second voltage level is lower than the first voltage level. A field relaxation circuit is connected between the terminal through which the output signal is output.

Abstract: The present invention discloses a level shift circuit which comprises: level shift means for receiving an input of a first operational voltage and generating an output of a second operational voltage; and a current path connecting with a source of the second operational voltage and providing current to the output of the level shift means to speed up output level switching. The circuit preferably further comprises a power consumption control circuit for stopping excess power consumption when the output of the level shift means has substantially accomplished level switching.

Abstract: A level shifter circuit for ensuring a high impedance state even in a transitional period such as when activating an external power supply while reducing power consumption. A latch circuit is set to a low level by a set circuit when a high potential power supply voltage increases. When the high potential power supply voltage exceeds a threshold voltage, a p-channel MOS transistor of the latch circuit is activated and the high potential power supply voltage is applied to a first transistor via a connection node. When a high potential enable signal having normal high level signal voltage is provided to a second transistor, which is connected to the first transistor, the reset circuit provides the high level signal to the latch circuit and stops the voltage application to the first transistor via the connection node.

Abstract: A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.

Abstract: A five volt tolerant integrated circuit signal pad having an initial fast pull-up to three volts and then operating as an open drain output with an external resistor for pulling up the output from about three volts to about five volts. The initial fast (active) pull-up is accomplished with active devices that reduces the overall pull-up time of a newer technology (lower operating voltage) integrated circuit output when transitioning from a logic 0 to a logic 1. Circuits of the integrated circuit output driver protect the internal operating circuit nodes from excessive voltage and leakage currents that would otherwise result from a voltage on the signal pad that is more positive than the operating voltage of the integrated circuit.

Abstract: A bus switch circuit includes a switch element having two terminals whose electrical connection is controlled when a control signal is input into a control terminal. The bus switch circuit further includes a first pull-up resistor and first switch circuit, a second pull-up resistor and second switch circuit. The control signal controls the electrical connections of the first and second switch circuits.

Abstract: A voltage level conversion circuit is provided with a level converter for converting a VDD1 system input signal into a VDD2 system signal, and a NOT circuit for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD1 system NOT circuits constituting the level converter are input to only high breakdown voltage transistors in the level converter while a signal having a logical voltage level corresponding to the low power supply voltage VDD2 is input to low breakdown voltage transistors, and further, only the input signal level-converted by the level converter is input to the NOT circuit.

Abstract: An integrated receiver circuit for amplifying an input signal based on a reference signal includes two voltage converters to respectively convert the input and reference signals to level-converted input and reference signals. An amplifier stage includes a PMOS input differential amplifier driven by the converted input and reference signals, and an NMOS input differential amplifier driven by the input and reference signals. The amplifier stage is connected to a first control stage to compensate an output offset current generated by the amplifier stage. A second control stage is cascaded to the first control stage to provide a duty cycle correction of an output signal. The receiver circuit ensures amplification of an input signal even if a level of the reference signal is close to a supply voltage, the input and reference signals have a large variation range, or the input signal has an asymmetrical input swing about the reference signal.

Abstract: A voltage translating control structure for switching logic is described. A battery drain problem is corrected by this structure. The voltage translating feature allows reliable switching between power supply and battery even if the power supply voltage has significantly decreased. Operation is adaptable to include all DC power systems. Logic circuitry that also allows voltage translation is presented.

Abstract: A level shifter circuit includes a level shifter unit and a latch unit. The level shifter unit receives two complementary input signals and converts the voltage levels of two complementary input signals. The latch unit latches the state of two output nodes before the low voltage supply is turned off. On condition that the low voltage supply is off, the level shifter circuit avoids current drainage and ensures the voltage level of the output. The invention has the advantages of small circuit size and being easy to design.

Abstract: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus comprises a level shifter and an asynchronous dynamic control circuit. The level shifter has a first switch and connected to a high power supply voltage source via the first switch, wherein the level shifter shifts a level of an input signal and outputs an output signal if enabled. The asynchronous dynamic control circuit sends an enabling signal for temporarily turning on the first switch to enable the level shifter.

Abstract: A circuit arrangement includes a first level shifter, an output stage, and a feedback circuit. The first level shifter is coupled to receive an input signal having a first voltage level from an input terminal, and is configured to provide a level-shifted signal having a second voltage level higher than the first voltage level. The output stage includes a first transistor that has a control terminal operably coupled to an output of the first level shifter. The output stage is configured to provide at an output terminal of the output stage an output signal based on the level-shifted signal. The feedback circuit is configured to feed back the output signal to the output of the first level shifter.

Abstract: Embodiments of a high-speed level shifter are described. The level shifter may include a first transistor having a drain, a source, and a gate and a second transistor having a drain, a source, and a gate. The first and second transistors may be operable to receive a pair of differential signals. The level shifter may further include a third transistor having a drain, a source, and a gate, the drain of the third transistor directly coupled to the source of the first transistor, and the source of the third transistor directly coupled to the source of the second transistor. The gate of the third transistor is driven by a level-shifted version of an output voltage generated from the pair of differential signals.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.

Abstract: An I/O output circuit is disclosed for interfacing a first system operating at a first voltage with a second system operating at a second voltage higher than the first voltage. The I/O output circuit includes an output stage module having one or more PMOS transistors and one or more NMOS transistors for coupling with the second system. A switch module is coupled to the output stage module for selectively providing the PMOS and NMOS transistors with various gate biases. A feedback circuit is coupled between an I/O pad that couples the output stage module to the second system and the switch module for controlling the switch module to generate the gate biases in response to a voltage at the I/O pad, thereby ensuring voltages across gates of the PMOS and NMOS transistors to be within a predetermined range.

Abstract: A level shifter circuit for shifting a voltage level of a logic signal from a first voltage to a second voltage includes an input stage operating in a domain of a first voltage supply that receives an input signal. The input stage includes a first inverter receiving the input signal and providing a first inverted signal. An output voltage level shifting stage operating in a domain of a second voltage supply is coupled to the input stage and providing an output signal having a voltage level corresponding to the second voltage supply domain and a logic value corresponding to the input signal. The level shifter circuit enables voltage level shifting a logic signal from a high to a low operating voltage, or from a low to a high operating voltage. The level shifter circuit enables high frequency operation, providing both fast switching and low capacitance.

Abstract: A semiconductor device having a level shifter, a differential amplifier circuit, and the like, where power consumption is reduced by reducing an unnecessary through current and distortion of an output waveform can be suppressed. A gate terminal of the first transistor is a first input terminal and a gate terminal of a second transistor is a second input terminal. The gate terminal of the first transistor is connected to a source terminal of the second transistor. The gate terminal of the second transistor is connected to a source terminal of the first transistor.

Abstract: A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shift circuit of the present invention can successfully convert a small input voltage into a large output voltage with less DC current and/or without any additional bandgap circuit.

Abstract: In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally. As for a signal outpuffed from the correcting circuit, when a transistor in the objective digital circuit is required to be turned OFF, the correcting circuit outputs a corresponding signal, namely a first power source potential. At this time, the transistor is turned OFF. On the other hand, when the transistor is required to be turned ON, the correcting circuit outputs a first input potential. Consequently, the objective digital circuit is turned OFF when it is required to be in an OFF state while turned ON when it is required to be in an ON state. Thereby, the objective digital circuit can be normally operated.

Abstract: A voltage conversion circuit changes an input signal of a first voltage into an output signal of a second voltage. The circuit includes an input terminal receiving an input signal, an output terminal generating an output signal, and first and second level-shifting units connected in parallel between the input and output terminals. The first and second level-shifting units have different transition delay characteristics, enabling rising and falling transition delays to be variable in the same ratio when the first and second voltages are changed.

Abstract: A level shifter is disclosed. The level shifter includes a level shifter core circuit and a pull-up control logic circuit. In response to an input signal and an output signal of the level shifter core circuit, the pull-up control logic circuit selectively turns on a transistor within the level shifter core circuit to prevent the occurrence of a strong P-N fight state within the level shifter.

Abstract: A first inverter circuit comprises a first transistor in which one end of a current path is grounded, and a second transistor in which one end of a current path is connected to the other end of the current path of the first transistor. A first signal is supplied to gates of the first and second transistors. A third transistor is connected between the other end of the current path of the second transistor and a node to which a second voltage higher than the first voltage is supplied. A control signal constituted of one of the ground potential and the second voltage is supplied to a gate of the third transistor behind a change of a first signal. A second signal constituted of one of the ground potential and the second voltage is output from an output terminal of the first inverter circuit.

Abstract: A voltage level converter includes a static voltage level converter and a split-level output circuit coupled to the static voltage-level converter. In another embodiment, the voltage-level converter includes a static voltage level-converter, a first transistor, and a second transistor. The static voltage-level converter includes an input node, a first pull-up node, a second pull-up node, an inverter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node.

Abstract: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors a current equivalent to or greater than the OFF leakage currents flowing through the signal-input transistors when they are OFF, thereby canceling the OFF leakage currents. Therefore, one of nodes which is at H level is surely fixed to a potential equal to a higher voltage supply. Thus, the level shifter surely operates with a high speed even when large OFF leakage currents flow through the signal-input transistors.

Abstract: A dual power supply digital device includes a down converter for converting an externally applied supply voltage to a regulated first supply voltage for powering a core part of the logic circuitry of the digital device. A second supply voltage source provides a second supply voltage for powering input buffers of the I/O pads of the digital device. A voltage translator latch stage may be powered at the regulated down converted first supply voltage for replicating a stored inverted replica of a logic value present on a respective I/O pad of the digital device onto an input node of a respective second input logic buffer powered at the regulated core supply voltage. The device may further include a transistor having a turn-on threshold coupling the input node of the second buffer to the regulated down converted core supply voltage, with the transistor having a control gate connected to the second power supply source.

Abstract: A control circuit including a first control unit, controlling a logic circuit, connected between a power supply and a virtual ground, the control unit connecting the virtual ground to a ground in response to a mode control signal when the logic circuit operates in an active mode and disconnecting the virtual ground from the ground in response to the mode control signal when the logic circuit operates in a sleep mode. A method of controlling including connecting the logic circuit between a power supply and a virtual ground, connecting the virtual ground to a ground in response to a mode control signal when the logic circuit operates in an active mode, and disconnecting the virtual ground from the ground in response to the mode control signal when the logic circuit operates in a sleep mode.

Abstract: An integrated circuit is provided with body bias generation circuitry. The body bias generation circuitry generates a body bias signal that is provided to transistors on a body bias path. The body bias generation circuitry contains an active latch-up prevention circuit that clamps the body bias path at a safe voltage when potential latch-up conditions are detected. The level of body bias signal that is generated by the body bias circuitry is adjustable. The body bias generation circuitry regulates the body bias voltage on the body bias path using a p-channel control transistor. An isolation transistor is coupled between the p-channel control transistor and the body bias path. During potential latch-up conditions, the isolation transistor is turned off to isolate the body bias path from ground. Control circuitry adjusts a body bias voltage that is applied to body terminals in the p-channel control transistor and isolation transistor.

Abstract: A voltage translator circuit for low level to high level voltage translation includes a plurality of transistors coupled to an inverter for receiving a common input signal at an input node of the plurality of transistors and passing a translated output signal to the output node of the plurality of transistors. A latch circuit is connected between a first node at the output node of the plurality of transistors and a second node that is connected to a feedback element at an input side of the plurality of transistors to form a feedback circuit that minimizes static power dissipation.

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract: A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal.

Abstract: An over-voltage tolerant input stage in a semiconductor device is disclosed. The input stage includes: an input pad for receiving an input signal to the semiconductor device, a buffer coupled to the input pad for buffering the input signal, a pullup circuit for limiting current in the input signal, a switching circuit coupled to the input pad for controlling the pullup circuit, and a voltage supply coupled to the input pad, the pullup circuit and the switching circuit. In operation, the switching circuit is enabled to cause the pullup circuit to stop current flow between the input signal and voltage supply in the event of an over-voltage condition.

Abstract: A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between a first data storage node of the first and second inverters and an input signal swinging between the first voltage and a ground voltage. A second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

Abstract: A pre-driver for large I/O pull-up and pull-down transistors is provided so that the I/O pull-up and pull-down transistors do not experience crowbar current, and the pre-driver circuit likewise does not experience crowbar current or require large driver transistors. One pre-driver circuit includes two NAND gates and two NOR gates with delay circuitry provided by two series inverters from a data input to a first node, and two additional series inverters from the first node to a second node. A further pre-driver circuit includes feedback from the pre-driver outputs to ensure its NMOS and PMOS transistors do not turn on together to create crowbar, while allowing faster switching. With the pre-driver circuit embodiments, a conventional level shifter can be used. Further with the pre-driver circuitry, slew rate control can be provided in the pull-up and pull-down driver circuitry, rather than in the pre-driver circuitry.