Abstract: The present invention relates to a level converter used in a multiple supply voltage system that is required to design a low-power and high-performance semiconductor, and more particularly, to a single supply pass gate level converter (SPLC) for a multiple supply voltage system, which has low power consumption, operates at high speed, and uses only a single supply voltage. The SPLC includes an input data providing circuit unit which receives an input signal of a low supply voltage; a data inversion circuit unit which receives input data from the input data providing circuit unit and outputs inversed input data; a feedback circuit unit which is fed back by an output of the data inversion circuit unit; and a data output buffer which inverses an output of the data inversion circuit unit and outputs an inversed signal.

Abstract: A semiconductor device according to the present invention includes: a first internal terminal; a second internal terminal; a first switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a first reference electric potential and a state in which the second internal terminal is not electrically coupled to the first reference electric potential; a second switching circuit coupled to the second internal terminal to switch between a state in which the second internal terminal is electrically coupled to a second reference electric potential and a state in which the second internal terminal is not electrically coupled to the second reference electric potential; and a comparator coupled to the first internal terminal and the second internal terminal to compare an electric potential of the first internal terminal with an electric potential of the second internal terminal, in which the first switching circuit and the second swi

Abstract: An improved interface circuit is provided herein for translating a relatively high input voltage into a relatively low output voltage using only low voltage transistors and a single, low voltage power supply. According to one embodiment, the interface circuit includes a power supply, a pair of input transistors with source terminals coupled together for receiving a relatively low voltage from the power supply, and a current sense amplifier with a pair of input terminals, each coupled to a drain terminal of a different one of the pair of input transistors for receiving a pair of differential currents and for generating a pair of differential voltages therefrom.

Abstract: A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit 5, a barrier gate circuit 2 and a holding circuit (MMP1, MMP2). The level converter circuit converts a signal level of a circuit operating in a VDD1 system to a signal level of a VDD2 system. The barrier gate circuit is responsive to a standby signal (STBY) to fix input signals (AB, AAB) of the level converter circuit 5 at a LOW level. The holding circuit holds an output of the level converter circuit 5 at a constant voltage when the input signals (AB, AAB) are at the LOW level (FIG. 1).

Abstract: A level shift circuit includes a level shifter, the level shifter configured to receive input signals and generate level-shifted signals by level-shifting the input signals, an output buffer that includes a first sourcing circuit and a first sinking circuit, the first sourcing circuit and the first sinking circuit being connected in series between a first power and a second power, a first buffer coupled between the level shifter and the output buffer, the first buffer configured to buffer the level-shifted signals and provide a first driving signal to the first sourcing circuit, and a second buffer coupled between the level shifter and the output buffer, the second buffer configured to buffer the level-shifted signals and provide a second driving signal to the first sinking circuit.

Abstract: A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.

Abstract: A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to the normal lines, a level shifting circuit for receiving an input signal swinging between a power supply voltage level and a ground voltage level, and shifting the input signal to an output signal swing between the power supply voltage level and a low voltage level lower than the ground voltage level by a predetermined level to output a shifted signal via the shield line, and a signal input unit for transferring the signal provided via the shield line to an output node.

Abstract: A circuit, includes first, second, and third inverters. The first inverter has a first input coupled to a first port and a first output coupled to a second port. The second inverter has a second input coupled to the second port and a second output coupled to the first port. The third inverter has a third input coupled to the first port through a first capacitor and to a third port. The third inverter has an output coupled to the second port through a second capacitor. The circuit receives a signal having a voltage between a first voltage potential and a second voltage potential and in response outputs a signal having a voltage between the second voltage potential and a third voltage potential. The third voltage potential is higher than the first and second voltage potentials with respect to ground.

Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.

Abstract: An isolated level shifter base cell that is configurable as either an isolated HIGH level shifter or an isolated LOW level shifter based on changes to connection layers, e.g., metal-2 and/or via-1 layers, without adjusting lower layers, or base layers, that form the isolated level shifter base cell. Regardless of the configuration selected, the isolated level shifter base cell requires the same footprint and provides the same input-to-output path timing. Further, the isolated level shifter base cell is configurable as either a HIGH or LOW isolation cell, i.e., without level shifting, based on changes to the connection layers while again maintaining the same footprint and input-to-output path timing. The configuration of the described isolated level shifter base cell can be changed late in the integrated circuit design process without affecting integrated circuit base layers, without changing the integrated circuit footprint, and without introducing integrated circuit timing changes.

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Abstract: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bi-directional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.

Abstract: Disclosed herein is an apparatus for outputting complementary signals using bootstrapping technology. The apparatus for outputting complementary signals includes a precharaged logic block, one or more output nodes, and a bootstrapping circuit block. The precharged differential logic block generates a differential signal depending on an input signal. The one or more output nodes output the complementary signals depending on the differential signal. The bootstrapping circuit block is shared by the one or more output nodes, and amplifies the complementary signals.

Abstract: A method for increasing responding speed and lifespan of a buffer includes detecting an edge of an input signal of the buffer, triggering a pulse signal with a predetermined period according to the detected edge, and driving the buffer for generating an output signal according to the pulse signal and the input signal.

Abstract: A level shifter for integrated circuits includes input stage transistors, reference stage transistors, a cascode stage coupled to the input stage and the reference stage transistors and a pair of comparators. The cascode stage generates a first cascode output and a second cascode output. The input stage transistors selectively conduct a low reference voltage as the first cascode output based on a pair of inputs provided to the input stage transistors. The reference stage transistors selectively conduct a high reference voltage as the second cascode output based on a first comparator output and a second comparator output. The pair of comparators generate the first and the second comparator outputs based on the first and the second cascode outputs.

Abstract: A logic signal transmitting circuit includes a CMOS inverter, a first transistor switch and an inverter. The CMOS inverter includes a p-type transistor and an n-type transistor and is configured for inverting an input signal. The first transistor switch is connected to an input of the CMOS inverter and controlled by the input signal. The inverter is connected between the p-type transistor and the first transistor switch, in which the inverter turns off the p-type transistor when the first transistor switch is turned on and the inverter turns on the p-type transistor when the first transistor switch is turned off.

Abstract: A level shifter circuit of the present invention includes a level shifter for converting a low-voltage signal to a high-voltage signal, and is provided with a unit that sets a voltage condition of an input signal to a transistor for input of the level shifter, when a high-voltage power supply is inputted to the level shifter circuit of the present invention before a low-voltage power supply.

Abstract: In one embodiment, the present disclosure includes a level shift circuit. The level shift circuit includes a clocked latch to receive a digital data signal and a complement of the digital data signal. Outputs of the clocked latch are coupled to inputs of a second latch through capacitors. The clocked latch is powered by first and second power supply voltages that are different than third and fourth power supply voltages used for powering the second latch. Latch output signals from the second latch have high and low voltage values at the third and fourth power supply voltages. In one embodiment, transistors in circuitry driven by the level shift circuit may receive output signals from the level shift circuit that have high and low voltage values within a safe operating range of the transistor receiving the output signal.

Abstract: A method for increasing responding speed and lifespan of a buffer includes detecting an edge of an input signal of the buffer, triggering a pulse signal with a predetermined period according to the detected edge, and driving the buffer for generating an output signal according to the pulse signal and the input signal.

Abstract: A data output driving circuit for a semiconductor apparatus includes a code converter that varies an input on-die termination code according to a control signal and outputs the code, and a driver block having impedance which can be modified according to the code generated by the code converter.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node ? into a floating state. When the node ? is in the floating state, a potential of the node ? is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.

Abstract: Hotsocket detection circuitry is provided for detecting hotsocket conditions in integrated circuits such as programmable logic device integrated circuits. Power-on-reset circuitry may provide a power-on-reset signal that is indicative of when power supply voltages are ready to power circuitry on the integrated circuit for normal operation. A delay circuit that is powered by a power supply voltage may receive the power-on-reset signal and may generate a corresponding delayed version of the power-on-reset signal. The delayed version of the power-on-reset signal may be provided to the hotsocket detection circuitry to ensure that the hotsocket detection circuitry produces a hotsocket signal that transitions after a transition in the power-on-reset signal. The delay circuit may include one or more inverter stages.

Abstract: A voltage level shifting circuit may include a differential first-stage level shifter that receives a binary input signal and generates a non-inverted first-stage shifted output signal and an inverted first-stage shifted output signal, a second-stage level shifter that receives the first-stage shifted output signals and generates a non-inverted second-stage shifted output signal and an inverted second-stage shifted output signal, and a signal generator that generates a level shifted final output signal corresponding to the binary input signal that is based on the non-inverted second-stage shifted output signal and the inverted second-stage shifted output signal. The voltage swing of the first stage output signals may be limited to swing between a non-zero lower value and an upper value that is less than or equal to a source-to-drain voltage rating of transistors in the differential first-stage level shifter.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

Abstract: In a particular embodiment, a method includes receiving an input voltage at an input to a level shifting circuit that includes voltage pull-up logic. The method includes providing an output signal from the level shifting circuit. The method also includes selectively activating the voltage pull-up logic circuit of the level shifting circuit.

Abstract: A level shifter circuit includes first and second transistors that receive a first input signal at control inputs. A level shifted output signal is generated by the first and the second transistors. Third and fourth transistors receive a second input signal at control inputs. The first input signal is an inverse of the second input signal. A first multiplexer circuit is configurable to couple a control input of a fifth transistor to the first and the second transistors. A second multiplexer circuit is configurable to couple a control input of a sixth transistor to the third and the fourth transistors.

Abstract: A circuit for converting a lower voltage logical signal to a higher voltage. The circuit comprises a current mirror structure having first and second branches, each comprising at least a first transistor of a first kind, an input transistor of a second kind, and a second transistor of the first kind coupled between them. The first transistors are arranged as a current mirror. The input transistors are driven using a logical signal at the lower voltage, controlling the current mirror structure to output a corresponding logical signal at the higher voltage. The second transistors are driven by an intermediate reference voltage so as to reduce the operating voltage of the third transistors. The first kind is tolerant of a higher operating voltage than the second kind.

Abstract: A level converter for providing an output signal at a circuit output based on an input signal includes an output coupling circuit formed to provide an output signal based on a first partial output signal and a second partial output signal, a driver circuit formed to provide the second partial output signal such that the second partial output signal is switchable between two different signal levels depending on the state of the input signal, wherein an input of the driver circuit is capacitively coupled to the input of the level converter in order to allow for switching between the signal levels of the second partial output signal by the capacitive coupling in response to a change in the state of the input signal, and a holding circuit formed to keep the state of the second partial output signal constant in case of a constant state of the input signal.

Abstract: Implementations are presented herein that include a level shifter circuit.

Abstract: A level shifter includes a level shifting circuit which receives input signal from a function block and changes the voltage level of the input signal, to output an output signal; a current blocking circuit, which suppresses current flowing to the level shifting circuit in an input suppression mode in which power supplied to the function block is cut and deactivates the level shifting circuit; and an output control circuit, which controls the output signal of the level shifting circuit to have a direct current (DC) voltage level in the input suppression mode.

Abstract: Disclosed is a level shift circuit that includes a first level shifter which is connected between an output terminal and a first power supply terminal that supplies a first voltage and sets the output terminal to a level of the first voltage when an input signal received at an input terminal assumes a first value; a second level shifter which is connected between the output terminal and a second power supply terminal that supplies a second voltage and sets the output terminal to a level of the second voltage when the input signal assumes a complementary value of the first value; and a feedback control unit that performs control of deactivating the first level shifter during a predetermined time interval including a point of time when the input signal is supplied when it is detected that the output terminal immediately before the input signal is received at the input terminal assumes the first voltage level.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a first circuit portion including: a first circuit that is connected between a first high-side power line and a low-side power line and that outputs a second signal based on a first signal input thereto; and a second circuit portion including: a first transistor that is connected between a second high-side power line and a node and that has a normally-on characteristic; a second circuit that is connected between the node and the low-side power line and that outputs a third signal based on the second signal input thereto.

Abstract: Arrangement for accepting an input signal in a first voltage range and producing an output signal in a second voltage range. A transition detection circuit (230) detects a transition from a high level to a low level of the input signal and a control circuit (245) operates a first FET to produce the low level of the output signal. A second FET is operated by the high level of the input signal to output the high level of the output signal.

Abstract: The invention relates to a CMOS input circuit for receiving low-swing input signals, which is an alternative to the CMOS input circuits as known from the prior art.

Abstract: The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems.

Abstract: A dual-wire communications bus circuit, compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus. The bus has a first line for carrying data signals from a master device to one or more slave devices and a second line to carry a clock signal between the devices. A pullup resistor is located in each part of the communications bus circuit; the pullup resistor in the first part couples to the first line of the communications bus and the pullup resistor in the second part couples to the second line of the communications bus. To improve data throughput and reduce noise, an active pullup device, working in conjunction with the pullup resistor, is located in each part of the communications bus circuit, providing a high logic level on at least one of the communications bus lines.

Abstract: Provided is a complementary metal oxide semiconductor (CMOS) input buffer circuit that is capable of lower voltage operation with lower current consumption. The CMOS input buffer circuit includes: a depletion type NMOS transistor including a drain connected to a power supply terminal (VDD), and a gate connected to an output terminal; a PMOS transistor including a source connected to a source of the depletion type NMOS transistor, a drain connected to the output terminal, and a gate connected to an input terminal; and an NMOS transistor including a source connected to a reference terminal (GND), a gate connected to the input terminal, and a drain connected to the output terminal.

Abstract: A high voltage CMOS output buffer is constructed from low voltage CMOS transistors. The output buffer employs a series of unique CMOS inverter stages, each of which contains a switched PMOS transistor, one or more voltage drop blocks, and a switched NMOS transistor. The voltage drop blocks are composed of stacked PMOS transistors that are diode-connected—i.e., the PMOS gate terminal is connected to the PMOS drain terminal, and the PMOS body (N-well) terminal is connected to the PMOS source terminal. The diode-connected PMOS transistors reduce the voltage across the transistor gate oxide to a safe value, for all internal PMOS/NMOS transistors inside the CMOS output buffer.

Abstract: The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block.

Abstract: An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode.

Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

Abstract: Described herein is the method and apparatus for generating symmetrical level shifted signals by a symmetrical level shifter. The symmetrical level shifter comprises an edge detector operable to generate transition edge based pulses from an input signal based on a first power supply level; a voltage level shifter, coupled with the edge detector, operable to convert the transition edge based pulses based on the first power supply level to edge based pulses based on a second power supply level; and a divider circuit, coupled with the voltage level shifter, operable to generate an output signal from the edge based pulses based on the second power supply level.

Abstract: Subject matter disclosed herein relates to circuit design, and more particularly relates to low power circuit techniques for receiver circuits.

Abstract: A cross-coupled inverter includes a first inverter and a second inverter cross-coupled such that the input terminal of each inverter is connected to the output terminal of the other inverter. A set signal is input to the gate of a first set transistor, and an inverted set signal is input to the gate of a fourth set transistor. A reset signal R is input to the gate of a first reset transistor of a reset unit, and an inverted reset signal is input to the gate of a fourth reset transistor thereof. The gate of the second set transistor and the gate of the third reset transistor are connected to the output terminal of the second inverter. The gate of the third set transistor and the gate of the second reset transistor are connected to the output terminal of the first inverter.

Abstract: A conditional level shifter circuit is used to substantially eliminate sneak current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Sneak current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground, VSS, of the integrated circuit device. The conditional ground restoration circuit shifts the virtual ground logic “0” to the true ground level. This eliminates sneak current and logic level corruption.

Abstract: A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level.

Abstract: A level shift circuit includes: a first transistor coupled to a first reference voltage for receiving a first voltage input signal; a second transistor coupled to a second reference voltage; a first diode-connected transistor coupled between the second transistor and the first diode-connected transistor; a third transistor coupled to the first reference voltage and the second transistor, for receiving a second voltage input signal, wherein the first voltage input signal is an inverse version of the second voltage input signal; a fourth transistor coupled to the second reference voltage and the first transistor; a second diode-connected transistor coupled between the fourth transistor and the third transistor; and a fifth transistor coupled to the second voltage input signal, the first reference voltage, and the fourth transistor, wherein a level-shifted output signal corresponding to the first voltage input signal is generated at an output node of the fourth transistor.