Bus Driving Patents (Class 326/86)
  • Patent number: 10318700
    Abstract: A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven B. Gold, Wen Wei Low, Feng Xue, Yvonne Chii Yeo, Jung H. Yoon
  • Patent number: 10236883
    Abstract: A circuit includes a first driver unit and a second driver unit. The first driver unit is configured to generate a first output signal in response to a data signal and an enable signal, and drive the first output signal towards a power supply voltage, or towards a reference voltage, or hold the first output signal at a previous voltage level. The second driver unit is configured to generate a second output signal in response to the data signal and the enable signal, and drive the second output signal towards the power supply voltage, or towards the reference voltage, or hold the second output signal at a previous voltage level. The first output signal and the second output signal are complementary to each other.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: March 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jack Liu
  • Patent number: 10223951
    Abstract: A scanning direction control circuit includes a selection control circuit configured to output a first control signal to a start signal reception control circuit and output a second control signal to a direction control circuit; the start signal reception control circuit configured to, under the control of the first control signal, enable a scanning pulse signal input end to be electrically coupled to a forward scanning start signal input end during forward scanning, and enable the scanning pulse signal input end to be electrically coupled to a backward scanning start signal input end during backward scanning; and the direction control circuit configured to, under the control of the second control signal, output a forward scanning control signal to a scanning direction control end during forward scanning, and output a backward scanning control signal to the scanning direction control end during backward scanning.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: March 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventors: Hao Shang, Zhidong Yuan, Tao Zhang
  • Patent number: 10211840
    Abstract: A charge pump driver circuit comprises an output stage and a current generator component. The output stage is arranged to receive at an input node thereof a control current signal and comprises a resistance network coupled between the input node thereof and a reference voltage node and arranged to provide a resistive path through which the control current signal flows. The output stage is arranged to generate at an output node thereof a charge pump control voltage signal based on the voltage level at the input node thereof. The current generator component is arranged to receive an indication of a voltage level of a charge pump output signal, and to generate a feedback current dependent on the voltage level of the output signal, wherein the feedback current is injected into the resistive path of the resistance network through which the control current signal flows.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pierre Pascal Savary, Dominique Delbecq, Birama Goumballa
  • Patent number: 10187147
    Abstract: A signal decoding method which enables communication between various devices is disclosed according to one aspect. The signal decoding method includes: a step SF1 of determining whether or not a Datapart length that is a bit length of a data part included in a packet of a visible light signal is an eight bit; and a step SF2 of decoding the data part according to a result of the determination of the Datapart length, and, in step SF2, the decoding is performed according to LSB first when it is determined in step SF1 that the Datapart length is not an eight-bit length, and the decoding is performed according to MSB first when it is determined in step SF1 that the Datapart length is the eight-bit length.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: January 22, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hideki Aoyama, Mitsuaki Oshima
  • Patent number: 10176136
    Abstract: A system on chip, semiconductor device, and/or method are provided that include a plurality of masters, an interface, and a semaphore unit. The interface interfaces the plurality of masters with a slave device. The semaphore unit detects requests of the plurality of masters, controlling the salve device, about an access to the interface and assigns a semaphore about each of the plurality of masters by a specific operation unit according to the detection result.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: DongSik Cho, Jeonghoon Kim, Rohitaswa Bhattacharya, Jaeshin Lee, Honggi Jeong
  • Patent number: 10082532
    Abstract: The present disclosure provides a detection circuit and a method for detecting an abnormal interface coupling. The detection circuit includes: a power circuit; a first USB interface, including a first power wire and a first signal wire, in which a power end of the first power wire is coupled to the power circuit; a second USB interface, including a second power wire and a second signal wire, in which the second USB interface is coupled with the first USB interface, such that the second signal wire is coupled with the first signal wire; and a controller, configured to acquire a voltage difference between a voltage of the first power wire and a voltage of the second power wire, and to determine whether the interface coupling is abnormal according to the voltage difference.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: September 25, 2018
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Jialiang Zhang, Kewei Wu, Jie Wu, Xingwei Yuan, Feiwu Shuai
  • Patent number: 10033360
    Abstract: Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventor: Chee Hong Aw
  • Patent number: 9965426
    Abstract: According to various embodiments, a method of operating a two-wire digital bus includes applying a bias voltage to the two-wire digital bus at a first interface node, measuring a common mode voltage of the two-wire digital bus at the first interface node, and adjusting the bias voltage at the first interface node based on the measured common mode voltage.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: May 8, 2018
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Eric Pihet
  • Patent number: 9958306
    Abstract: A thermal-type flow meter for representing a flow rate of air by the frequency of a periodic signal, wherein abnormalities in the waveform of an output signal due to frequency variation is prevented while high-frequency noise is suppressed. The thermal-type flow meter pertaining to the present invention is provided with a plurality of switching elements connected in parallel, and varies a delay width between the switching elements in accordance with variation of the frequency of a periodic signal for representing a flow rate.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: May 1, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Ryo Ando, Daisuke Terada, Takeo Hosokawa
  • Patent number: 9904652
    Abstract: A serial low-power inter-chip media bus communications link is deployed in apparatus having multiple Integrated Circuit devices. Communications capabilities of a device coupled to the communications link may be determined and configuration or framing message may be sent to the first device based on the capabilities. The messages may be transmitted on a primary data line of the communications link with a clock used to control timing of transmission on at least the primary data line. The communications capabilities can include information identifying a number of data wires supported by or coupled to the device. A first device may be configured to communicate with a second device over a secondary data line, which may be reserved for such direct communication. Communications on the secondary data line may be synchronized using the clock signal and may be controlled by a different protocol than the protocol used for the primary data line.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: February 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Gilad Sthoeger, Michael Zilberstein, Alexander Khazin, Ben Levin
  • Patent number: 9906220
    Abstract: A circuit comprises an input terminal configured to receive an input signal. A high-side driver is configured to provide a high-side control signal to a high-side power transistor via a high-side terminal based on the input signal. A low-side driver is configured to provide a low-side control signal to a low-side power transistor based on the input signal. An interface is configured to couple the high-side terminal and the low-side terminal via a capacitor.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 27, 2018
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Wolfgang Frank, Remigiusz Viktor Boguszewicz
  • Patent number: 9817787
    Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Mohan K. Nair, Brent D. Thomas, Ramamurthy Krithivas
  • Patent number: 9813152
    Abstract: Methods and systems for optoelectronics transceivers integrated on a CMOS chip are disclosed and may include receiving optical signals from optical fibers via grating couplers on a top surface of a CMOS chip, which may include a guard ring. Photodetectors may be integrated in the CMOS chip. A CW optical signal may be received from a laser source via grating couplers, and may be modulated using optical modulators, which may be Mach-Zehnder and/or ring modulators. Circuitry in the CMOS chip may drive the optical modulators. The modulated optical signal may be communicated out of the top surface of the CMOS chip into optical fibers via grating couplers. The received optical signals may be communicated between devices via waveguides. The photodetectors may include germanium waveguide photodiodes, avalanche photodiodes, and/or heterojunction diodes. The CW optical signal may be generated using an edge-emitting and/or a vertical-cavity surface emitting semiconductor laser.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: November 7, 2017
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Steffen Gloeckner, Sherif Abdalla, Sina Mirsaidi, Peter De Dobbelaere, Lawrence C. Gunn, III
  • Patent number: 9755632
    Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: September 5, 2017
    Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.
    Inventors: Vikas Rana, Fabio De Santis
  • Patent number: 9749004
    Abstract: A transceiver and an operation method thereof are provided. The transceiver includes a transmitter and a receiver. The transmitter is configured to receive an output reference signal to provide an output signal to a signal channel. The receiver is coupled to the signal channel to receive a receiving reference signal to provide a receiving signal. The receiver includes a comparator unit and a signal adjusting unit. The comparator unit is configured to compare a first signal and a second signal to obtain the receiving signal. The signal adjusting unit is coupled between the output reference signal, the receiving reference signal and the comparator unit to adjust a voltage level of at least one of the output reference signal and the receiving reference signal to obtain the first signal and the second signal.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 29, 2017
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yu-Chang Lien, Chiao-Wei Hsiao, Yu-Hsuan Lin
  • Patent number: 9712159
    Abstract: A differential driving circuit includes a source current source, a sink current source, an H-bridge circuit, an error detector unit and a circuit network. The H-bridge circuit is connected to the source current source and the sink current source, that has a first output terminal and a second output terminal, and that generates differential output from the first output terminal and the second output terminal. The error detector unit adjusts a common mode voltage at the first output terminal and the second output terminal of the H-bridge circuit by controlling at least one of the source current source and the sink current source. The circuit network is configured by resistors and capacitors connected to the first output terminal and the second output terminal of the H-bridge circuit.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: July 18, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Naoki Isoda
  • Patent number: 9672169
    Abstract: A memory module such as a DIMM includes two separate memories with corresponding data, address and control interfaces. Each separate memory core includes plural memory banks for corresponding portions of the data interface. The separate interfaces include separate byte strobes and control signals. The two memories may be separately powered or share power connection. The two memories may be disposed on a single semiconductor integrated circuit or separate semiconductor integrated circuit. The two memories may be connected to two external memory interfaces of a single data processor or to separate data processors.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: June 6, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: William Hinson Winderweedle
  • Patent number: 9652431
    Abstract: Systems and techniques for single-wire communications are described. A described system includes a host device, and a slave device coupled with the host device via a single-wire bus. The host device can be configured to transmit synchronization information based on transitions over the single-wire bus. The slave device can be configured to detect the transitions on the single-wire bus, determine timing information of the host device based on a first transition of the transitions and a second transition of the transitions, determine a predicted start time of a host sampling window based on the timing information, and determine, based on a predicted charging duration, whether to perform a charge operation before the predicted start time or after a predicted end time of the host sampling window. The charge operation can include drawing power from the single-wire bus to charge the device.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 16, 2017
    Assignee: Atmel Corporation
    Inventor: Eustace Ngwa Asanghanwa
  • Patent number: 9583156
    Abstract: A selected gate (SG) driver circuit, including a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor. A gate electrode of the first NMOS transistor is connected to a gate electrode of the first PMOS transistor, a source electrode of the first NMOS transistor being connected to a drain electrode of the third NMOS transistor, and a drain electrode of the first NMOS transistor being connected to a drain electrode of the first PMOS transistor and a gate electrode of the second NMOS transistor. A source electrode of the second NMOS transistor is connected to a source electrode of the third NMOS transistor, and a drain electrode of the second NMOS transistor being connected to a drain electrode of the second PMOS transistor and a gate electrode of the third NMOS transistor.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Guangyan Luo, Hao Ni, Changwei Yin, Xiao Zheng
  • Patent number: 9553569
    Abstract: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 24, 2017
    Assignee: INPHI CORPORATION
    Inventors: James Lawrence Gorecki, Han-Yuan Tan
  • Patent number: 9479172
    Abstract: The differential output buffer comprises the differential output circuit, and the bias voltage generation circuit that is the replica circuit of the differential output circuit. The bias voltage generation circuit generates, by the operational amplifier, the bias voltage for controlling currents respectively flowing in the first current source of the differential output buffer and the second current source of the bias voltage generation circuit such that the voltage of the third internal node between the third internal and external resistors and the third switch of the bias voltage generation circuit becomes equal to the reference voltage equal to the voltage of the first internal node when the first switch of the differential output buffer is in an ON state or equal to the voltage of the second internal node when the second switch of the differential output buffer is in an ON state.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: October 25, 2016
    Assignee: MegaChips Corporation
    Inventor: Tomoaki Kuramasu
  • Patent number: 9479174
    Abstract: A tristate gate includes an output port and at least two transistors. Each of the transistors has at least a first and a second gate configured such that a high-impedance value (Z) on the output port is set by controlling the threshold voltage of at least one of the transistors.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: October 25, 2016
    Assignee: SOITEC
    Inventor: Richard Ferrant
  • Patent number: 9471518
    Abstract: A multi-modal memory interface that supports each of current-mode and voltage-mode signaling by a memory controller with a memory which includes one or more memory devices. In a first type of system, the memory interface is configured to provide differential current-mode signaling from the memory controller to a first type of memory, and differential voltage-mode signaling from the memory to the memory controller. In contrast, in a second type of system, the memory interface is configured to provide single-ended voltage-mode signaling from the memory controller to the memory, and single-ended voltage-mode signaling from a second type of memory to the memory controller. To support these different types of systems, the memory controller couples different types of drivers to each I/O pad. The resulting capacitance is reduced by sharing components between these drivers. Moreover, in some embodiments, the memory interface is implemented using “near-ground” current-mode and voltage-mode signaling techniques.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: October 18, 2016
    Assignee: Rambus Inc.
    Inventors: Amir Amirkhany, Wendemagegnehu Beyene
  • Patent number: 9438232
    Abstract: A semiconductor device is provided. The semiconductor device includes a driver circuit, a dummy circuit, and a control unit. The driver circuit is configured to provide a termination resistor at a signal transmission path. The driver circuit includes a plurality of resistors having at least two different types of resistor. The dummy circuit is electrically connected to the driver circuit and is configured to compensate for a mismatch between the at least two different types of resistors. The control unit is configured to control the dummy circuit, based on a result obtained by detecting the mismatch.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyung-Soo Ha
  • Patent number: 9287003
    Abstract: A memory controller includes logic to determine corresponding reference voltage values and delay values for one or more memory devices. The memory controller includes a command-address (CA) interface to send a command to a memory device to set a reference voltage value of the memory device to a test value, a data interface to write a data pattern to the memory device and read the data pattern from the memory device, and test reference voltage logic to perform a density check on at least a portion of the data pattern read from the memory device and determine whether the test value is a potential reference voltage value based on the density check. An operational reference voltage value selected from one or more potential reference voltage values may be used to determine a delay value.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: March 15, 2016
    Assignee: Rambus Inc.
    Inventors: Liji Gopalakrishnan, Mahabaleshwara Mahabaleshwara
  • Patent number: 9287856
    Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Jie Zhan, Tsung-Hsin Yu
  • Patent number: 9245597
    Abstract: Described examples include sensing circuits and reference voltage generators for providing a reference voltage to a sensing circuit. The sensing circuits may sense a state of a memory cell, which may be a PCM memory cell. The sensing circuits may include a cascode transistor. Examples of reference voltage generators may include a global reference voltage generator coupled to multiple bank reference voltage generators which may reduce an output resistance of the voltage generator routing.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: January 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Xinwei Guo, Mingdong Cui
  • Patent number: 9246476
    Abstract: An object is to prevent malfunction of a power device. In a semiconductor device for driving a power device for power supply, a buffer circuit and a level-shift circuit are configured by transistors having the same conductivity type. Furthermore, a capacitor is provided in the level-shift circuit, and a signal to be boosted is supplied to the capacitor and is boosted using capacitive coupling of the capacitor. Furthermore, a structure can be employed in which the signal is boosted in such a manner that, in the level-shift circuit, a capacitor is provided between a wiring for supplying a low power source potential and a wiring for supplying a potential to boost the signal so that a power transistor can be driven.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: January 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventor: Kei Takahashi
  • Patent number: 9236022
    Abstract: According to one aspect of the present invention, the provided is a gate driving circuit, comprising: a first switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register units; a second switch control circuit, being configured to be respectively coupled to each of the multiple stages of shift register units. The first switch control circuit controls the multiple stages of shift register units to turn on in a forward sequence; the second switch control circuit controls the multiple stages of shift register units to turn on in a backward sequence.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: January 12, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaofang Gu, Rui Ma, Ming Hu
  • Patent number: 9231706
    Abstract: A drive circuit includes a duty cycle adjusting circuit that changes the duty cycle of a first signal; and a calculating circuit that with respect to signals that include the first signal for which the duty cycle has been adjusted and a second signal having a phase and amplitude that differ from that of the first signal, performs any one of subtracting one of the signals from the other signal and adding the signals.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: January 5, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Yukito Tsunoda
  • Patent number: 9148146
    Abstract: Disclosed is a high-swing voltage-mode transmitter or line driver. The transmitter can operate over a wide range of supply voltages. Increasing the available output swing merely involves increasing the supply voltage; the circuit adapts to maintain the desired output impedance. This allows for a tradeoff between output amplitude and power consumption. Another advantage of the proposed architecture is that it compensates for process, voltage, and temperature (PVT) and mismatch variations so as to keep rise and fall times matched. This feature reduces common-mode noise and hence EMI in systems in which the transmitter is used.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: September 29, 2015
    Assignee: PMC-Sierra, Inc.
    Inventors: Julien Faucher, Michael Ben Venditti
  • Patent number: 9130557
    Abstract: A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: September 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Chul Cho, Jung Bae Lee, Jung Hwan Choi
  • Patent number: 9118346
    Abstract: The present disclosure provides embodiments of an improved current steering switching element for use in a digital to analog (DAC) converter. Typically, each current steering switching element in the DAC converter provides a varying set of currents for converting a digital input signal. Generally, the switches and drivers in the current steering switching elements are scaled down proportionally to the current being provided by the current steering switching element according to a ratio as less and less current is being driven by the switching element in order to overcome timing errors. However, device sizes are limited by the production process. When a switch is not scaled proportionally to the current, settling timing errors are present and affects the performance of the DAC. The improved current steering switching element alleviates this issue of timing errors by replacing the single switch with two complementary current steering switches.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: August 25, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Matthew Louis Courcy, Martin Clara, Gabriele Manganaro, Gil Engel, Lawrence A. Singer
  • Patent number: 9111187
    Abstract: A contactless card includes an inductive circuit configured to send and receive signals, a rectifier circuit coupled to the inductive circuit and configured to generate a DC voltage from an AC voltage generated by the inductive circuit, a clamp circuit configured to limit the DC voltage, a regulator circuit configured to regulate the DC voltage and a control circuit configured to selectively enable and disable the clamp circuit and the regulator circuit.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 18, 2015
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Jong Pil Cho, Il Jong Song, Sang Hyo Lee
  • Patent number: 9106465
    Abstract: Continuous-time linear equalization of received signals on multiple wire channels while maintaining accurate common mode signal values. Multiwire group signaling using vector signaling codes simultaneously transmits encoded values on multiple wires, requiring multiple receive signals to be sampled simultaneously to retrieve the full transmitted code word. By misaligning transitions on multiple wires, skew introduces a transient common mode signal component that is preserved by using frequency-selective common mode feedback at the receiver to obtain accurate sampling results.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: August 11, 2015
    Assignee: KANDOU LABS, S.A.
    Inventor: Christoph Walter
  • Patent number: 9088276
    Abstract: A pre-emphasis circuit is disclosed. In one embodiment, a pre-emphasis circuit includes a first signal path configured to receive a first signal and a second signal path configured to receive the first signal. The second signal path includes a re-timing circuit configured to delay the first signal by a pre-determined amount to produce a second signal. The pre-emphasis circuit also includes a summing circuit coupled to receive the first signal from the first signal path and the second signal from the second signal path. The summing circuit is configured to add the second signal to the first signal to produce a third signal, wherein the third signal is logically equivalent to the first signal. The third signal has a first magnitude for a first portion of a bit-time of the first signal, and a second magnitude for a second portion of the bit-time of the first signal.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: July 21, 2015
    Assignee: ATI TECHNOLOGIES ULC
    Inventors: Sandra Liu, Eric W. Hu, Chih-Tsung Ku
  • Patent number: 9086711
    Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: July 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Jan Diffenderfer, Yu Song
  • Patent number: 9076398
    Abstract: A display and an operating method thereof are provided. The display includes a display panel, a timing controller, and a plurality of source drivers. The timing controller has a plurality of signal output terminals. The source drivers are coupled to the timing controller and the display panel. The timing controller outputs a plurality of training packets to the source drivers. When the source drivers lock a clock of the timing controller according to the training packets, the timing controller outputs a plurality of control packets and a plurality of color data packets to the source drivers. The source drivers respectively output a plurality of pixel voltages corresponding to the color data packets to the display panel according to the corresponding control packets. The training packets, the control packets, and the color data packets are serially transmitted to the source drivers via the signal output terminals.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: July 7, 2015
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hsin-Chia Su, Jia-Hao Wu, Chuan-Che Lee
  • Patent number: 9030228
    Abstract: An intelligent current drive is disclosed that couples an active current source to a bus line to increase the rate of pull-up and decouples the active current source from the bus line prior to reaching the desired pull-up voltage.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: May 12, 2015
    Assignee: Atmel Corporation
    Inventor: Lloyd Clark
  • Patent number: 9024654
    Abstract: An active termination circuit for a differential receiver includes a first receiver element configured to receive a first component of a differential signal, a second receiver element configured to receive a second component of a differential signal, a common mode measurement element configured to receive the differential signal and generate a transmit common mode signal (Vcm) representing an average value of the differential signal, and a receiver (RX) common mode signal node. The termination circuit also comprises an active element configured to receive the transmit common mode signal (Vcm) and provide an output to the receiver common mode signal node, the output configured to drive the value of the signal at the receiver common mode signal node to the value of the transmit common mode signal (Vcm), and a capacitive element coupled to the receiver common mode signal node in parallel with the active element.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: May 5, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Robert Thelen, Michael Farmer, Jade Kizer
  • Patent number: 9013209
    Abstract: A apparatus, having a processing system and an input buffer coupled with both the processing system and one of two IO pads, and a reference buffer coupled to both the input buffer and the second of the IO pads such that the reference generator controls the input threshold of the input buffer in response to an analog voltage received from an external circuit on the second of the IO pads.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: April 21, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Timothy John Williams, David G. Wright, Gregory John Verge, Bruce E. Byrkett
  • Patent number: 8988102
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 8988106
    Abstract: A voltage mode driver circuit able to achieve a larger voltage output swing than its supply voltage. The voltage mode driver circuit is supplemented by a current source or “current booster.” The circuit includes a first inverter, a second inverter, and a current source. The first inverter receives a first input and outputs a signal at a node. The second inverter receives a second input signal and outputs an inverted second input signal at the same node. The current source provides current to the node via a first switch, the first switch receiving an input at a first input where the voltage output swing at the node is larger than a power supply voltage applied to the current source. The voltage mode driver circuit uses a stable power supply voltage using a power amplifier with feedback.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Wei Chih Chen
  • Patent number: 8980642
    Abstract: The present invention relates to the use of cyanocinnamic acid derivatives as a matrix in the MALDI mass spectrometry of an analyte.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: March 17, 2015
    Assignee: Sigma-Aldrich International GmbH
    Inventors: Michael Karas, Thorsten Wolfgang Jaskolla
  • Patent number: 8975915
    Abstract: A driver circuit for a digital signal transmitting bus includes a main switch. The main switch is connected to the bus, is controllable by the digital signal to be transmitted, and has one on-switching state in which it has maximum electrical conductivity, one off-switching state in which it has minimum electrical conductivity and at least one intermediate switching state with an electrical conductivity between the minimum and maximum conductivity. The digital signal has a first logic state and a second logic state, the first logic state controls the main switch to be in the on-switching state and the second logic state controls the main switch to be in the off-switching state. The main switch is in the intermediate switching state during switching from the on-switching state to the off-switching state and/or vice versa.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: March 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: David Astrom, Daniel Mandler
  • Patent number: 8952725
    Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal).
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 10, 2015
    Assignee: Via Technologies, Inc.
    Inventors: Yeong-Sheng Lee, Kuen-Chir Wang
  • Patent number: 8952718
    Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: February 10, 2015
    Assignee: Mediatek Inc.
    Inventors: Yan-Bin Luo, Sheng-Ming Chang, Bo-Wei Hsieh, Ming-Shi Liou, Chih-Chien Hung, Shang-Ping Chen
  • Patent number: 8952719
    Abstract: Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Masayasu Komyo, Yoichi Iizuka
  • Patent number: 8933727
    Abstract: An integrated circuit comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of complementary outputs based upon a plurality of inputs, a first control signal, and a second control signal. The plurality of inputs may be received in parallel in a first mode and as a serial bit stream in a second mode. The second circuit may be configured to generate a plurality of outputs in response to a third control signal and a fourth control signal.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: January 13, 2015
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: Chengxin Liu, Christopher D. Weigand