Abstract: There is formed a semiconductor device including, as the uppermost-layer wiring of the multilayer wiring layer, a plurality of first wirings, a second wiring, a plurality of first dummy wirings, a second dummy wiring, and a passivation film covering these wirings. The passivation film is patterned by etching with a photoresist film used as a mask, the plurality of first wirings and the plurality of first dummy wirings close thereto are densely formed, and the second dummy wiring is formed so as to surround a periphery of the second wiring sparsely formed directly above an analog circuit portion.

Abstract: Disclosed is an inverter which includes a first P-MOS transistor connected between a node receiving a drain voltage and a first path node and operated based on an input voltage, a first N-MOS transistor connected between the first path node and an output terminal outputting an output voltage and operated based on the drain voltage, a second P-MOS transistor connected between the output terminal and a second path node and operated based on a ground voltage, a second N-MOS transistor connected between the second path node and a node receiving the ground voltage and operated based on the input voltage, a third P-MOS transistor connected between the first path node and the second path node and operated based on the input voltage, and a third N-MOS transistor connected between the first path node and the second path node and operated based on the input voltage.

Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.

Abstract: A self-clocked SAR ADC sensor circuit includes an ADC having a capacitor array with a plurality of capacitors connected through a respective plurality of switches, a comparator, an SAR module, and a delay element circuit for ring oscillator and stall detection. The delay element circuit includes a delay block with a NAND gate followed by a plurality of inverters.

Abstract: An output driver includes a pullup driver, a pulldown driver and a resistive element. The pullup driver includes a first PMOS transistor having a source coupled to a first supply voltage and a gate receiving a first data representative of a transmitted data, and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a gate receiving a first analog signal. The pulldown driver includes a first NMOS transistor having a source coupled to a second supply voltage and a gate receiving a second data representative of the transmitted data, and a second NMOS transistor having a source coupled to a drain of the first NMOS transistor, a drain coupled to a drain of the second PMOS transistor, and a gate receiving a second analog signal. The resistive element is coupled between the drain terminal of the second NMOS transistor and a pad.

Abstract: Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory.

Abstract: A transmission device of the present disclosure includes: a driver unit that transmits a data signal with use of a first voltage state, a second voltage state, and a third voltage state interposed between the first voltage state and the second voltage state, and is configured to make a voltage in the third voltage state changeable; and a controller that changes the voltage in the third voltage state to cause the driver unit to perform emphasis.

Abstract: Methods and systems are provided for transmitting data using thin-oxide devices. The methods and system generate a first bias voltage and a second bias voltage based on a power supply voltage of the second voltage domain, the first bias voltage value representing a high-level voltage signal of the first voltage domain, and the second bias voltage representing a low-level voltage signal of the second voltage domain and its value corresponds to a difference between the second voltage domain and the first voltage domain. The methods and systems generate an output of the thin-oxide device interface using first and second thin-oxide devices, the output of the thin-oxide device interface having a range corresponding to the second voltage domain.

Abstract: Disclosed is a low-voltage detection floating N-well bias circuit. The circuit includes a power detector configured to detect states of first power (VDD) and second power (DVDD) at different power levels; a switch configured to perform a switching operation according to the states of the first power (VDD) and the second power (DVDD); and a voltage output circuit configured to output the first power (VDD) or the second power (DVDD) as an N-well bias voltage according to the states of the first power (VDD) and the second power (DVDD) and the switching operation of the switch. Accordingly, when the first power (VDD) and the second power (DVDD) are supplied and the second power (DVDD) has a low voltage state, the floating N-well bias circuit can continuously bias an N-well with the second power (DVDD), without dropping the second power (DVDD).

Abstract: The disclosure provides a level shifter circuit. The level shifter circuit includes a first transistor and a second transistor. The first transistor and the second transistor generate an output voltage according to a first control signal and a second control signal, respectively. A time interval of rising edges of the output voltage is greater than a time interval of falling edges of the output voltage.

Abstract: A repeater for open-drain bus communication and a system including the same is provided. The bus repeater includes an A-to-B buffer to receive the signal at the A-side terminal and to produce a first buffered signal, a B-side pull-down control unit to produce a first control signal based on the received first buffered signal, and a B-side pull-down element to pull down the voltage at the B-side terminal based on the first control signal. The B-side pull-down element includes a B-side pull-down transistor that is arranged in between the B-side terminal and a B-side ground reference terminal. The first control signal controls a voltage at the control terminal of the B-side pull-down transistor. The B-side pull-down control unit includes a B-side comparing unit to compare the voltage at the B-side terminal to a first reference voltage, and to generate the first control signal based on a result of the comparison.

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

Abstract: A testing method includes the following steps of: accessing a memory chip to put the memory chip into a write leveling mode; inputting a strobe signal into the memory chip under the write leveling mode; adjusting signal edges of the strobe signal to sample a clock state of a clock signal in the memory chip under the write leveling mode; generating a data signal according to the strobe signal under the write leveling mode; and determining types of the memory chip according to the data signal under the write leveling mode.

Abstract: To reduce power consumption of a driver circuit used in a vertical drive circuit of an image processing device. In the driver circuit, a drive signal output circuit outputs a drive signal in accordance with a predetermined trigger signal. Furthermore, at a time of rising of the drive signal, a step-up switch sequentially selects a plurality of voltages in ascending order, and supplies the selected voltage to the drive signal output circuit. Moreover, at a time of falling of the drive signal, a step-down switch sequentially selects a plurality of voltages in descending order, and supplies the selected voltage to the drive signal output circuit.

Abstract: An integrated circuit includes a diode string, a first transistor, a second transistor, and a third transistor. The diode string is coupled between a first reference voltage pin and an input/output (I/O) pad. A first terminal of the second transistor is coupled to a first node, and a gate terminal of the second transistor is coupled to a second reference voltage pin. In response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to a gate terminal of the first transistor.

Abstract: A voltage level shifter includes an input transistor, a control circuit, a reset circuit, and a keeper circuit. The input transistor is configured to receive an input voltage and a first reference voltage. The control circuit is configured to generate a pulse voltage according to the input voltage and one of a node voltage, an output voltage, and an inversion input voltage. The reset circuit is configured to receive the first reference voltage and a second reference voltage and controlled by the pulse voltage. The reset circuit is coupled to the input transistor at a first node where the node voltage is generated. The keeper circuit is coupled to the first node and configured to generate the output voltage according to the node voltage, the first reference voltage, the second reference voltage, and the output voltage.

Abstract: Embodiments of redrivers and resistive termination units for redrivers are disclosed. In an embodiment, a resistive termination unit for a redriver includes a resistor connected to an input/output terminal of the redriver, a first switch connected to the resistor and to a supply voltage of the redriver, a second switch connected to the first switch and configured to be turned on or off in response to a change in the supply voltage of the redriver, and a control circuit connected to the first switch through the second switch and configured to generate a control signal for the first switch.

Abstract: An attenuation device for a CAN transceiver comprises two device output nodes configured to electrically couple the attenuation device via the device output nodes between two transceiver terminals of the CAN transceiver. The attenuation device is configured to change from a first device state to a second device state when a common mode voltage is applied to the device output nodes that is either greater than a first reference voltage or less than a second reference voltage that is less than the first reference voltage. The attenuation device causes a first electrical output resistance at each device output node during the first device state and causes a second electrical output resistance at each device output node during the second device state in which the second output resistance is less than the first output resistance.

Abstract: This application relates to monitoring of electronic devices (100) and in particular to methods and apparatus for the detection and recording of an electrical overstress applied to a connector (101, 102) of the device. The apparatus describes an integrated circuit (103, 105) of the host device having a first set of one or more circuit contacts (201, 203, 204, 205) for connection to a connector (101) of a host electronic device. The circuit has an electrical overstress monitor (106, 106a) for detecting and recording an electrical overstress comprising a voltage exceeding a predetermined parameter applied to at least one of said first set of circuit contacts. The electrical overstress monitor (106) may have an overvoltage detector (205) and may have a memory (206) for recording the occurrence of an overvoltage and/or a communication module (207) for communicating with other components of the host device in the event of an electrical overstress.

Abstract: A system and method to allocate serial interconnection lanes on a die to multiple communication protocols is disclosed. The die has at least one processing core. The die incudes a first communication subsystem including a controller, a protocol coding sublayer (PCS) for interchanging data, and a data interface coupled to the core. The die includes a second communication subsystem including a controller, a PCS for interchanging data, and a data interface coupled to the core. A mode input selects at least one of the first or second communication protocol. A data router has an input coupled to the PCS of the first communication subsystem and an input coupled to the PCS of the second communication subsystem. The data router has an output coupled to the set of serial interconnection lanes, and a selection input coupled to the mode input to allocate some of the lanes for the selected protocol.

Abstract: A protection circuit applied in a hub chip including a power pin, a first data pin, and a second data pin is provided. A voltage generation circuit generates and adjusts output voltage according to the voltage of the power pin and the voltage of the first data pin. A PMOS transistor includes a first gate, a first electrode, a second electrode, and a first bulk. The first electrode is coupled to the power pin. The second electrode is coupled to the first data pin. The first bulk receives the output voltage. A detection circuit is coupled to the first gate and detects the voltage of the power pin. In response to the voltage of the power pin being equal to the first voltage, the detection circuit transmits the voltage of the first data pin to the first gate.

Abstract: A signal compensation line includes at least one of: a first signal compensation line including a first end connected to a main line (3) on a side closer to a first communication device (1) with respect to a first connection point (8-1) counted from the first communication device (1) among connection points (8-1) to (8-3) between the main line (3) and respective first ends of branch lines (5-1) to (5-3), and a second end grounded; or a second signal compensation line including a first end connected to the main line (3) on a side closer to a second communication device (2) with respect to the first connection point (8-3) counted from the second communication device (2) among the respective connection points (8-1) to (8-3), and a second end grounded.

Abstract: A repeater for open-drain bus communication and a system including the same is provided. The repeater includes at least one repeating unit having an A-side terminal connected to an A-side open-drain bus, and a B-side terminal electrically connected to a B-side open-drain bus. The repeater has a first mode to receive a signal at the A-side and to produce a signal at the B-side. The repeating unit includes a B-side accelerator element connected to the B-side terminal. The repeating unit when in a first mode includes a first control unit to, control the B-side accelerator element to pull up a voltage at the B-side when the voltage at the A-side surpasses a first threshold voltage during a rising edge of the voltage, and to subsequently control the B-side accelerator element to stop pulling up the voltage at the B-side when the voltage at the B-side surpasses a second threshold voltage.

Abstract: Circuits and methods that use harvested electrostatic energy from transient: on-chip data are described in the Application. In one aspect, a method inverter circuit use harvested electrostatic charge held at any electric potential higher than the common ground reference potential of CMOS circuits in a chip, to partially drive a 0?1 logic transition at the output of the inverter at lower energy drain from the on-chip power grid than a conventional CMOS inverter with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Abstract: Circuits and methods for preventing glitch in a circuit are disclosed. In one example, a circuit coupled to an input/output pad is disclosed. The circuit includes: a first level shifter, a second level shifter, and a control logic circuit. The first level shifter is configured for generating a data signal. The second level shifter is configured for generating an output enable signal. The first and second level shifters are controlled by first and second power-on-control signals, respectively. The control logic circuit is coupled to the first level shifter and the second level shifter.

Abstract: Circuits and methods that harvest electrostatic energy from transient on-chip data are described in the Application. In one aspect, a method and inverter circuit harvests electrostatic charge held at its output node at an electric potential comparable to the power supply voltage rail to a common grid/node as the output makes a 1?0 logic transition. This charge harvested at a common grid/node can be used by circuits (described in applications 63/090,169, 63/139,744) to drive 0?1 logic transition at their output nodes at lower energy drain from the on-chip power grid than a conventional CMOS inverter would with similar performance, slew rates at inverter input and output and with similar output driving transistor geometries.

Abstract: A system and method for bidirectionally based electrical information storage, processing and communication. Bidirectional memory (tristate) offers the capability to store and interpret multiple bits (Shannon's) of information per memory cell, for structures such as dynamic random-access memory (DRAM), and read-only memory (ROM), and communication circuits, for operation, rather than traditional memory able to store a single “bit” (Shannon) of information per cell. Where, instead of traditional memory cells capable of two possible states (binary digit) and a single defined bit (1 Shannon), bidirectional memory is capable of three states (tristate), where the third information representing state can be a specifically defined state capable of representing multiple bits (multiple Shannon's) for each individual cell, which may be defined to represent a specific sequence of bits (sequence of Shannon's).

Abstract: A semiconductor device of an embodiment includes a buffer configured to perform data transmission by turning on and off a first output transistor group and a second output transistor group; a first correction circuit configured to calibrate a resistance value of the buffer by controlling an on-off state of each of first transistors of the first output transistor group; a second correction circuit configured to calibrate the resistance value of the buffer by controlling an on-off state of each of second transistors of the second output transistor group; and a control circuit configured to cause the calibration by the first correction circuit to be performed in a non-communication duration other than a duration of data transmission from the buffer and cause the calibration by the second correction circuit to be performed in a duration other than a duration of the calibration by the first correction circuit.

Abstract: Technologies for jitter extraction are described. A receiver device includes an analog-to-digital converter (ADC) and a signal processing circuit. The signal processing circuit includes an equalizer block to output current data based on samples from the ADC. A clock-recovery (CR) block includes a timing error detector (TED) or a phase detector to measure a sampling offset. The CR block can use the sampling offset to control sampling of subsequent data by the ADC. A jitter extraction block can use the sampling offset to re-sample the current data to obtain re-sampled data based on the sampling offset to remove jitter from the current data.

Abstract: A transceiver includes a transmitter and a receiver coupled to each other through a first line and a second line. The transmitter transmits a first voltage signal of a second logic level or a fourth logic level, among a first logic level, the second logic level, a third logic level, and the fourth logic level, through the first line. The transmitter transmits a second voltage signal of the first logic level or the third logic level through the second line. The receiver generates an output signal having one of four values based on the first voltage signal and the second voltage signal.

Abstract: In described examples, a circuit includes a switch. The switch includes first transistors and second transistors. A voltage generation circuit is coupled to the switch. A level shifter is coupled to the voltage generation circuit and is configured to receive a control signal. A logic unit is coupled to the level shifter and the voltage generation circuit. The logic unit is configured to generate a secondary signal. The first transistors are configured to receive the control signal, and the second transistors are configured to receive the secondary signal.

Abstract: The present invention relates to differential receivers, and more particularly to a fail-safe circuit for low-voltage differential signaling (LVDS) receivers having single differential input disconnect detection with a latchable control signal interrupt capability. In operation, the receiver output is applied to a Vout output as long as the control signal is in a normal operating state, and on the first occurrence of a fault condition trigger is applied to the input of a latch, the latch latches applying a fault state to the control signal which causes the Vout output to follow the control signal blocking the receiver output until the latch is reset after the fault has been corrected.

Abstract: Capacitive coupling may enable more tightly synchronized operation of components in a multi-domain distributed driver that provides slope-controlled switching of differential signal lines. One illustrative distributed driver includes: a first set of transistors each coupled to drive a first bus line; a first set of delay elements configured to enable and disable the first set of transistors sequentially; a second set of transistors each coupled to drive a second bus line; a second set of delay elements configured to enable and disable the second set of transistors sequentially; and at least one capacitance coupling a first node in the first set of delay elements to a corresponding second node in the second set of delay elements to synchronize signal transitions at the first and second nodes.

Abstract: A battery-powered system includes a battery pack (10; 71; 81) connected to an electrical equipment (30; 50; 76; 86). The battery pack includes a first positive electrode terminal (11), a first negative electrode terminal (12), a first communication terminal (13), a first data input circuit (23), and a first limiting circuit (D11; D72; D82) that limits a flow of electric current in a direction from the first negative electrode terminal to the first communication terminal via the first data input circuit. The connected equipment includes a second positive electrode terminal (31; 51), a second negative electrode terminal (32; 52), a second communication terminal (33; 53), a second data input circuit (43; 63; 77; 87), and a second limiting circuit (D31; D51; D77; D87) that limits a flow of electric current in a direction from the second negative electrode terminal to the second communication terminal via the second data input circuit.

Abstract: This document describes apparatuses and techniques for termination for single-ended (SE) mode operation of a memory device. In various aspects, a termination circuit can terminate an unused signal line of a differential pair to a ground or power rail using a switch element when operating in the SE mode. The termination circuit may also disconnect the unused signal line from a first input of a differential amplifier and connect a reference voltage to the first input of the differential amplifier. Based on the reference voltage, the differential amplifier amplifies an SE signal received using another signal line of the differential pair at a second input of the differential amplifier to provide a clock signal for memory operations. Thus, the termination circuit may reduce an amount by which noise associated with the unused signal line affects the differential amplifier when the memory device operates in SE mode.

Abstract: An integrated circuit (IC) includes logic components and a scan test circuit coupled to the logic components. The IC also includes a scan input pin coupled to the scan test circuit. The IC also includes a scan input/output pin coupled to the scan test circuit. The scan test circuit includes a decoder coupled to at least one of the scan input pin and the scan input/output pin. The decoder includes storage elements configured to store different scan control signals and to output at least one of the different scan control signals in response to a master control signal.

Abstract: An apparatus may include a first inverter and a second inverter cross-coupled between a first node and a second node to store a signal state represented by complementary voltages at the first node and the second node. The apparatus may further include a first path defined by the second inverter that includes an impedance element to resist a flow of charge suitable to change the signal state. The apparatus may further include the first inverter and a third inverter selectively cross-coupled between the first node and the second node to store a received signal state represented by the complementary voltages at the first node and the second node responsive to an assertion of a write enable signal.

Abstract: CMOS output stages, electrostatic discharge (ESD) protection circuits and input bus-keeper functions are provided that block dc and ac leakage paths within inactive powered-down integrated circuits used in redundant high-reliability system configurations employing cold-sparing to provide backup circuitry. These circuits and methods avoid both undesirable power consumption in a cold-spared backup unit and loading of connected active units when powered down, without compromising performance or functionality of the backup unit when in its active powered state. Inputs and outputs using an analog majority voting principle to implement in-circuit redundancy for on-chip fault tolerance are also provided, incorporating the low-leakage principles of the invention for low power dissipation when powered down. Such on-chip redundancy can harden an IC against various faults, such as single-event effects in high-radiation environments, while maintaining the other advantages in a cold-sparing system.

Abstract: A communication device is configured to exchange regular data bidirectionally with counterpart communication device via a regular interface; and to exchange additional data bidirectionally with the counterpart device via an additional interface. The device has a regular pinout corresponding to the regular interface that enables communication of regular data with the counterpart device; and an additional pinout with at least one additional pin, corresponding to the additional interface that enables communication of additional data with the counterpart device. The device has default data handling circuitry communicatively coupled to the additional pin, and configured, in a default mode, to transmit and receive additional default data via the additional pin. The first device has additional function data handling circuitry communicatively coupled to the additional pin and configured, in an active mode, to transmit and receive additional function data via the additional interface.

Abstract: An integrated circuit includes first and second bus terminals, a pass-gate transistor, first and rising time accelerator (RTA) control circuits, and first and second falling time accelerator (FTA) control circuits. The pass-gate transistor couples between the first and second bus terminals. The first RTA control circuit couples to the first bus terminal, detects a rising edge on the first bus terminal, and accelerates the rising edge on the first bus terminal. The first FTA control circuit couples to the first bus terminal, detects a falling edge on the first bus terminal having a slope below a threshold, and accelerates the falling edge on the first bus terminal. The second RTA and FTA control circuits function similar to the first RTA and FTA control circuits but with respect to the second bus terminal.

Abstract: The present application provides a differential signal interface and a display device adopting the differential signal interface. A plurality of different differential signals are transmitted between a transmitting end and a receiving end of the differential signal interface by a plurality of differential pairs. A plurality of moderating modules are disposed between the transmitting end and the receiving end. Each moderating module is connected to a corresponding differential pair and is configured to adjust the impedance of the transmitting end and/or the receiving end such that the impedance of the transmitting end and/or the receiving end matches the impedance of the corresponding differential pair.

Abstract: A network node for coupling to a communication bus, the node comprising: a receiver configured to receive messages from the communication bus; and a transmitter configured to transmit first messages having a first message format and configured to transmit diagnosis messages having a second message format on the communication bus for use in determination of communication errors, wherein said transmitter is configured to send said one or more diagnosis messages having one or more of: (i) a predetermined pattern of symbols; (ii) a predetermined sending schedule; (iii) a predetermined line encoding method; (iv) a predetermined bit rate; (v) a predetermined position in one or more of the first messages; (vi) a predetermined signalling frequency that is out of a frequency band used for transmission of the first messages; and (vii) a predetermined signal strength different from the signal strength used to send the first messages.

Abstract: A level-shifting output buffer has cascode transistors with varying rather than fixed gate bias voltages. An adaptive regulator bypasses the I/O pad voltage to a regulator output when the I/O begins switching, but later clamps the regulator output to a middle bias voltage. The regulator output can be applied to a supply terminal of a buffer that drives the gate of the cascode transistor. Since the adaptive regulator follows the I/O pad voltage as switching begins, a voltage boost is provided to the gates of the cascode transistors, allowing for higher currents or smaller cascode transistors and preventing over-voltage stress. The adaptive regulator has an n-channel bypass transistor between the I/O pad and the regulator output, and an n-channel clamp transistor between the regulator output and the middle bias, with a gate driven from the I/O pad by either a p-channel gate-biasing transistor or an n-channel gate-biasing transistor.

Abstract: A memory device includes a communication circuit configured to communicate a first signal and a second signal; and a selection mechanism coupled to the communication circuit and configured to select between operating the communication circuit the first signal and the second signal (1) independent signals for separate memory operations or (2) a complementary set for a memory operation.

Abstract: Provided are computer systems, methods, and devices for operating an artificial neural network. The system includes neurons. The neurons include a plurality of synapses including charge-trapped transistors for processing input signals, an accumulation block for receiving drain currents from the plurality of synapses, the drain currents produced as an output of multiplication from the plurality of synapses, the drain currents calculating an amount of voltage multiplied by time, a capacitor for accumulating charge from the drain currents to act as short-term memory for accumulated signals, a discharge pulse generator for generating an output signal by discharging the accumulated charge during a discharging cycle, and a comparator for comparing an input voltage with a reference voltage. The comparator produces a first output if the input voltage is above the reference voltage and produces a second output if the input voltage is below the reference voltage.

Abstract: Systems, apparatuses and methods may provide for origination camera technology that generates a cell representation of a local space associated with an origination camera in a multicast domain, predicts that an object in the local space will exit the local space and enter one or more adjacent spaces associated with additional cameras in the multicast domain, and sends the cell representation and a trajectory of the object to the additional cameras before the object exits the local space. Additionally, transition camera technology may generate a leader election message based on a multicasted trajectory of an object and a predicted trajectory of the object, send the leader election message from a transition camera to one or more additional cameras in a multicast domain, and track the object in the local space in response to a leader notification message.

Abstract: A circuit for a bus system. The circuit includes: a measuring circuit, which is configured to measure a first resistance value between two bus-side terminals of the circuit; an ascertainment circuit, which is configured to ascertain a second resistance value as a function of the first resistance value; and a resistive circuit, which is configured to set a resistor connectable between the two bus-side terminals to the second resistance value.

Abstract: In an integrated circuit, a first current source is coupled between a first supply voltage and a first node. An output stage includes a first current steering PMOS transistor coupled to the first node, a first current steering NMOS transistor including a first current electrode coupled to the first current steering PMOS transistor at a second node, a second current steering PMOS coupled to the first node, and a second current steering NMOS transistor including a first current electrode coupled to the second current steering PMOS transistor at a third node. Voltage at the second node is used to drive a gate of the second current steering PMOS transistor, and voltage at the third node is used to drive a gate of the first current steering PMOS transistor. First and second programmable slew rate pre-drivers provide outputs to the gates of the first and second current steering NMOS transistors, respectively.

Abstract: Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.

Abstract: A buffer circuit includes a first MOSFET including a first source electrode, a first gate electrode, and a first drain electrode, and a second MOSFET, which includes a second source electrode, a second gate electrode, and a second drain electrode, and is same in polarity as the first MOSFET, and the first gate electrode and the second gate electrode are electrically connected to each other.