Abstract: Described herein is a low-voltage circuit with an inductor tail and a common mode feedback loop for amplitude and current control. A first transistor pair can receive clock inputs, and a second transistor pair can receive data inputs and output the data to a logic gate. A tail inductor can be coupled to the first transistor pair to suppress high frequency common mode bounce induced by clock transitions in independent common emitter branches. A common mode feedback loop can be provided to maintain a constant average current. The common mode feedback loop and the tail inductor can together function in the same way as a tail current source at low frequencies and high frequencies respectively.

Abstract: A device includes an output circuit including a plurality of unit buffers, each of the unit buffers having an adjustable impedance; a controller circuit operable to selectively activate at least one of the unit buffers; and an impedance adjustment part operable to adjust the impedance of each of the unit buffers in response to a change of the number of the unit buffers that are selectively activated by the controller circuit.

Abstract: A detector circuit is disclosed that detects bus signal conditions. To detect a START condition, asynchronous sequential logic detects a first bus signal transition (e.g., from high to low) and a second bus signal (e.g., a high signal). The outputs of the asynchronous sequential logic are combined to produce a START signal that can be latched, so that the START signal can be used to wake up a system or for other purposes. To detect a STOP condition, asynchronous sequential logic is set by a transition (e.g., low to high) of the first bus signal and a second bus signal (e.g., a high signal), producing a STOP signal that can be used to reset the asynchronous sequential logic and the latch.

Abstract: A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.

Abstract: Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

Abstract: Integrated circuit devices may utilize automatic methods for adjusting the tail currents of current mode logic (CML) cells, which compensate for variations in process corners and thereby enable reliable operation of high performance circuits, such as frequency synthesizers. An integrated circuit may include a current mode logic (CML) circuit responsive to at least one input signal and a variable current source electrically coupled to the CML circuit. This variable current source can be configured to sink (or source) a first current from (or to) the CML circuit in response to a control signal. A control circuit may also be provided, which is configured to generate the control signal in response to a process corner indication signal. This process corner indication signal, which may be generated by a process corner detection circuit, preferably has a magnitude that estimates a relative speed of a process corner associated with the integrated circuit device.

Abstract: A differential output circuit has a current source, a voltage source, first paired transistors which, in a first operating mode, switch that current from the current source should be flown to which of paired output terminals, depending on logic levels of differential input signals, and is always turned off in a second operating mode, second paired transistors which, in the second operating mode, switch which of the paired output terminals should be applied with a voltage correlated with a voltage of the voltage source, depending on the logic levels of the differential input signals, and configured to be always turned off in the first operating mode, third paired transistors which, in the second operating mode, pass the current inputted into one of the paired output terminals toward a predetermined reference potential, and is always turned on in the first operating mode, and paired impedances.

Abstract: A signal transceiver includes a connector for receiving a signal, a band-pass filter coupled to the connector for filtering the signal, a front-end module for demodulating the signal and an adaptive impedance switch circuit coupled between the band-pass filter and the front-end module for switching an impedance value between the band-pass filter and the front-end module.

Abstract: A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal.

Abstract: An embodiment of a pre-emphasis circuit, an embodiment of a method for pre-emphasizing complementary single-ended signals, an embodiment of a transmitter, and an embodiment of a communication system.

Abstract: The present disclosure provides an output control circuit including a signal feedback circuit and an enable control circuit, wherein the signal feedback circuit is configured to compare an output voltage with a set output voltage threshold and to output a disable signal to an enable control circuit when the output voltage arrives at the set output voltage threshold, and wherein the enable control circuit is configured to stop an operation of a translation circuit, upon reception of the disable signal from the signal feedback circuit.

Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.

Abstract: A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored.

Abstract: A differential transmission circuit comprises a sending unit that generates a pair of differential signals from an input signal, and sends the differential signals; a receiver that receives the differential signals sent by the sending unit; and a transmission path that transmits the differential signals from the sending unit to the receiver, wherein the sending unit has a selector that selects one of the input signal and a signal obtained by inverting a polarity of the input signal, and generates the differential signals from the signal selected by the selector.

Abstract: In one embodiment, a hybrid output buffer having both an H-bridge mode and a CML mode of operation includes a plurality of transistor switches arranged between an upper rail and a bottom rail. A first pair of the transistor switches couples between the upper rail and respective output nodes. A pair of resistors couples between the output nodes and a central node. During H-bridge mode, the hybrid output buffer controls a potential of the upper rail responsive to a feedback signal proportional to a difference between a potential of the central node and a common-mode voltage.

Abstract: A smart data storage apparatus and data transmitting method for the same are to combine the hard disk with the dual interface memory, and are to use radio frequency identification (RFID) technology or near field communication (NFC) technology. The information of the self-monitoring analysis and reporting technology (SMART) of the hard disk still could be received by the handheld device without the power for the hard disk. Moreover, the external hard disk could be registered with the handheld device quickly.

Abstract: An embodiment of communication cell for enabling data communication between an integrated circuit and an electronic unit distinct from the integrated circuit, comprising a contact pad unit, configured for capacitively coupling, in a first operating condition of said communication cell, to the electronic unit for receiving an input signal from said electronic unit, and for ohmically coupling, in a second operating condition of said communication cell, to the electronic unit for receiving the input signal; a receiver device, including signal-amplifying means, coupled between said contact pad unit and said integrated circuit, configured for receiving the input signal and generating an intermediate signal correlated to the input signal; signal-selection means receiving the intermediate signal, the input signal, and providing an output signal which is the intermediate signal during the first operating condition, and the input signal during the second operating condition; and an input stage, connectable between the

Abstract: An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.

Abstract: A driver circuit of a semiconductor apparatus includes a driver and a control unit configured to vary a voltage level of a power supply terminal of the driver in response to a standby mode signal.

Abstract: A system having an input and output buffer includes a dynamic driver reference generator to generate dynamic driver reference signals based on a data signal and an IO buffer supply voltage, a level shifter to generate level shifted signals based, in part, on the dynamic driver reference signals, and a driver having at least one stress transistor. The driver dynamically adjusts a voltage across the stress transistor based on at least one of dynamic driver reference signals, the level shifted signals, and a current state of an IO pad.

Abstract: In accordance with an embodiment, a transceiver includes a bidirectional data transmission circuit coupled to a direction control circuit and method for transmitting electrical signals in one or more directions. The direction control circuit generates a comparison signal in response to comparing input/output signals of the bidirectional data transmission circuit. Transmission path enable signals are generated in response to the comparison signal.

Abstract: A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.

Abstract: A digital to analog converter including at least one current steering source and a master replica bias network. Each current steering source includes a data current source, two switches, two buffer devices, and two activation current sources. The switches are controlled by a data bit and its inverse for switching the source current between first and second control nodes. The buffer devices buffer the control nodes between corresponding output nodes. The activation current sources ensure that each buffer device remains active regardless of the state of the switches. The master replica bias network includes a replica buffer device coupled to a replica control node and a master buffer amplifier. The master buffer amplifier drives the first, second and replica buffer devices in parallel to maintain the first, second and replica control nodes at a common master control voltage to minimize noise and glitches at the output.

Abstract: A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines.

Abstract: A device and method for dc isolation and level shifting includes a driver circuit powered by a first voltage range, a capacitor connected to the driver circuit, and a latching circuit connected to the capacitor. The latching circuit is powered by a second voltage range and is configured to restore and/or minimize charge loss of the capacitor during a voltage transition at the capacitor. A device and method for analog isolation and measurement configured to measure an analog voltage at a second potential without requiring analog circuits at the second potential.

Abstract: This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to toggle the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A transmitter circuit in which a driver circuit includes MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input controlled by a voltage value of transmitted data signals, controlled by a voltage value of a bias voltage, and driver circuits include MOS transistors for bias voltage application, in which a driving current flows, cascode-connected to MOS transistors for differential signal input that is controlled by a voltage value of signals obtained by the transmitted data signals, connected to a load portion, and controlled by a voltage value of a bias voltage.

Abstract: A semiconductor device has a ZQ circuit (40) which generates impedance control information and an output buffer having an impedance controlled in response to the impedance control information. A plurality of control bits constituting the impedance control information are serially transferred from the ZQ circuit.

Abstract: An interface device for connection between two electronic components of an electronic circuit, includes: an input terminal, an output terminal and a reference terminal, an input voltage between the reference and input terminals, an output voltage between the reference and output terminals, an input impedance, and an output voltage gain, at least one resistance connected to at least one terminal among the input and output terminals, at least one analog switch positioned between the output and reference terminals, the switch having a closed or an open state, and control elements for each switch, at least one parameter among the input impedance and the output voltage gain of the device having distinct values as a function of whether the analog switch is closed or open, each analog switch including at least one N-type field effect controllable transistor and one P-type field effect controllable transistor connected in series.

Abstract: Systems and methods for implementing tristate signaling are described. The systems include an integrated circuit that further includes a tristate system. The tristate system converts an encapsulated unidirectional signal into a tristate signal. A relation between multiple unidirectional signals and the tristate signal is established by encapsulating the unidirectional signals to represent the tristate signal. The establishment of the relation facilitates control of the tristate signal by controlling the encapsulated unidirectional signals.

Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.

Abstract: Provided is a pre-emphasis circuit which transmits a pre-emphasis output current to an output node of an output driver in response to first to fourth pre-emphasis control signals generated by a logical operation on differential input signals. The pre-emphasis circuit includes: a first pre-emphasis circuit driven in a range between a first voltage and a second voltage and configured to generate a first pre-emphasis output current in response to the first and second pre-emphasis control signals and output the generated first pre-emphasis output current to a first output node of the output driver; and a second pre-emphasis circuit driven in the range between the first voltage and the second voltage and configured to generate a second pre-emphasis output current in response to the third and fourth pre-emphasis control signals and output the generated second pre-emphasis output current to a second output node of the output driver.

Abstract: An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines.

Abstract: Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Abstract: An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.

Abstract: A method of manufacture of an integrated circuit communication system including providing a semiconductor wafer; and fabricating a cross-over current mirror driver on the semiconductor wafer for generating a crossing point at a reference voltage.

Abstract: A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.

Abstract: A voltage mode transmitter equalizer has high efficiencies, yet consumes substantially constant supply current from the power supply and provides constant back-match impedance. The voltage mode transmitter equalizer is configured such that the output voltage of the signal to be output on a pair of transmission lines can be controlled according to the input data, but its return impedance is substantially matched to the differential impedance of the transmission lines and it draws substantially constant supply current from the power supply regardless of the output voltage of the signal. Further, an equalizer for a voltage-mode transmitter provides fine-granularity equalization settings by employing a variable pull-up conductance and a variable pull-down conductance. Conductance is varied by selectively enabling a plurality of conductance channels, at least some of which have resistance values that are distinct from one another.

Abstract: A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

Abstract: A DA conversion device includes a current output type DA converter, a high-speed operational amplifier operating at a low voltage and configured to generate a voltage corresponding to an output current from the DA converter, and a buffer amplifier connected to an output terminal of the high-speed operational amplifier and operating at a high voltage. The device also includes positive and negative floating power supplies separated from a power supply system and provided as power supplies for driving the DA converter and the high-speed operational amplifier. A midpoint between potentials at the floating power supplies is connected to an output terminal of the buffer amplifier to cause the DA converter and the high-speed operational amplifier to operate mainly based on an output voltage from the buffer amplifier.

Abstract: A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor.

Abstract: Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost signal. Additional apparatus, systems, and methods are disclosed.

Abstract: In an integrated circuit device having dynamically selected on-die termination, a set of data inputs are coupled respectively to a set of termination circuits, each termination circuit having multiple controllable termination impedance configurations.

Abstract: A redriver chip is inserted between a transmitter chip and a receiver chip and re-drives differential signals from the transmitter chip to the receiver chip. The redriver chip has switched output termination that switches to a high value to detect far-end termination at the receiver chip, and to a low value for signaling. An output detector detects when the receiver chip has termination to ground and enables switched input termination to provide termination to ground on the lines back to the transmitter chip so that the far-end termination on the receiver chip is mirrored back to the transmitter chip, hiding the redriver chip. An input signal detector detects when the transmitter chip begins signaling and enables an equalizer, limiter, pre-driver, and output stage to re-drive the signals to the receiver chip. The input signal detector also causes the switched output termination to switch to the low value termination for signaling.

Abstract: A structure is described having a plurality of electronic devices with the same or different internal CMOS voltages; an interconnection between two or more of the electronic devices; driver and receiver circuits which provide selectable input/output voltage levels for interfacing with several generations of CMOS technology, thus allowing chips fabricated in such technologies to communicate using a signal voltage range most suitable for each chip; Circuitry for selecting or adjusting the type of receiver circuit used, thus allowing either the use of a differential comparator circuit with an externally supplied reference voltage, or alternatively, the use of an inverter style receiver with an adjustable threshold, the selection being accomplished by setting the external reference to a predetermined voltage; Circuitry for selecting or adjusting the switching threshold of the inverter receiver circuit, which enables the threshold to be set appropriately for a given input signal voltage range.

Abstract: A semiconductor device includes a main driving unit configured to serialize first and second data applied in parallel and output the serialized data to a data output pad, and an auxiliary driving unit configured to drive the data output pad in a period when the first and second data have different logic levels.

Abstract: An on-die termination circuit is capable of increasing a resolution without enlargement of a chip or a layout size. The on-die termination circuit includes a control means, a termination resistance supply means, a code signal generating means. The control means sequentially generates a plurality of control signals in a response to a driving signal. The termination resistance supply means supplies a termination resistance in response to a coarse code signal having a plurality of bits and a fine code signal having a plurality of bits. The code signal generating means controls the fine code signal and the coarse code signal in response to the plurality of the control signals in order that the termination resistance has a level which is correspondent to an input resistance.