Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: A power transistor circuit suppling an internal voltage to an internal voltage supply node. The power transistor circuit includes external terminals, to each of which signals and/or voltages are applied, for each of the input node, output node and control node of the power transistor. The power transistor circuit includes the power transistor, a current draw transistor, a first diode connected between an external control terminal and the internal voltage supply node, and a second diode connected between the current draw transistor output node and the internal voltage supply node. The power transistor circuit includes a charge pump that receives power from the internal voltage supply node and outputs a voltage to the control node of the current draw transistor. In operation, the internal voltage supply node receives power from the external control terminal via the first diode, or an external input terminal via the current draw transistor and the second diode.

Abstract: A driver is suitable for use with a gallium nitride (GaN) power stage, and includes a voltage regulator and a high side driver. The voltage regulator provides a boot voltage between first and second terminals thereof that varies within a range between a turn-on voltage of a GaN transistor, and a safe voltage limit between a gate and a source thereof throughout an active time of said GaN transistor. The high side driver has an input for receiving a high side drive signal, an output for coupling to said gate of said GaN transistor, a power supply terminal coupled to said first terminal of said voltage regulator, and a ground terminal for coupled to said second terminal of said voltage regulator.

Abstract: A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A complementary metal oxide semiconductor (CMOS) circuit of a memory device includes a high-voltage functional circuit and an auxiliary clamping circuit. The high-voltage functional circuit includes at least one MOS transistor. One of a source terminal and a drain terminal of an MOS transistor is coupled to an input high-voltage. The high-voltage functional circuit has an output voltage that, when an enable signal is valid, gradually increases and reaches a maximum value. The auxiliary clamping circuit is arranged between the input high-voltage and the one of the source terminal and the drain terminal of the MOS transistor, and is configured to clamp the voltage input to the one of the source terminal and the drain terminal of the MOS transistor during a rising phase of the output voltage, so that the clamping voltage is smaller than the input high-voltage.

Abstract: A switching circuit includes a high-side transistor and a low-side transistor, each of which is of an N-channel type. A switch and a rectifying element of a PMOS transistor are provided in series between a constant voltage line through which a constant voltage is supplied and a bootstrap line. A comparison circuit operates using a high-side power supply voltage, which is a potential difference between the bootstrap line and a switching line, as a power supply to generate a detection signal indicating a magnitude relationship between the high-side power supply voltage and a threshold voltage. A level shift circuit level-shifts the detection signal down to a signal of which a ground voltage is low. A PMOS driver drives the switch asynchronously with switching of the low-side transistor in response to an output of the level shift circuit.

Abstract: A bootstrapping circuit that utilizes multiple pre-charged capacitor voltages and applies the capacitor voltages to the high side FET of a GaN bootstrapping driver. During the pre-charging phase of the bootstrapping driver, multiple capacitors are charged in parallel to the supply voltage. During the driving phase of the bootstrapping driver, the capacitors are connected in series through a number of FETs and connected to the gate terminal of the high side FET of the bootstrapping driver. As a result, the gate-to-source voltage of the high side FET is equal to or greater than the supply voltage during the driving phase, increasing the driving capability of the high side FET and reducing the total required capacitance and die area of the bootstrapping driver.

Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.

Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

Abstract: A power converter circuit included in a computer system magnetizes and de-magnetizes an inductor coupled to a switch node using high-side and low-side switches to alternatively couple a switch node to an input power supply node and a ground supply node. In response to detecting a drop in the voltage level of the input power supply node, the power converter circuit may adjust an on-resistance of the high-side switch to maintain performance at the lower voltage level of the input power supply node.

Abstract: A semiconductor device that restores degraded data is provided. The semiconductor device includes a first circuit, a storage portion, and an arithmetic portion. The first circuit includes a current source and a first switch. The storage portion includes a first transistor and a first capacitor. The arithmetic portion includes a second transistor. A first terminal of the first transistor is electrically connected to a control terminal of the first switch, a first terminal of the first switch is electrically connected to an output terminal of the current source, and a second terminal of the first switch is electrically connected to a first terminal of the second transistor. When data retained in the arithmetic portion is restored, the first transistor is turned on, and the data retained in the storage portion is supplied to the control terminal of the first switch through the first transistor.

Abstract: An object is to provide a semiconductor device which can suppress characteristic deterioration in each transistor without destabilizing operation. In a non-selection period, a transistor is turned on at regular intervals, so that a power supply potential is supplied to an output terminal of a shift register circuit. A power supply potential is supplied to the output terminal of the shift register circuit through the transistor. Since the transistor is not always on in a non-selection period, a shift of the threshold voltage of the transistor is suppressed. In addition, a power supply potential is supplied to the output terminal of the shift register circuit through the transistor at regular intervals. Therefore, the shift register circuit can suppress noise which is generated in the output terminal.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: Circuits, systems, and methods are described herein for generating a boost voltage for a write operation of a memory cell. In one embodiment, a boost circuit includes a first inverter and a second inverter, each configured to invert a write signal. The boost circuit also includes a transistor and a capacitor. The transistor is coupled to an output of the first inverter. The transistor is configured to charge a capacitor based on the write signal and provide a supply voltage to a write driver. The capacitor is coupled to an output of the second inverter. The capacitor is configured to generate and provide a delta voltage to the write driver.

Abstract: The present application provides an output driving circuit and a memory. The output driving circuit includes: a signal input terminal inputting a positive input signal and a negative input signal complementary to each other; a pull-up output unit and a pull-down output unit connected to the signal input terminal, the positive input signal acting as an input signal of the pull-up output unit, and the negative input signal acting as an input signal of the pull-down output unit; at least one compensation unit connected in parallel with the pull-up or pull-down output unit; at least one pulse signal generation circuit, and generating a pulse signal, the pulse signal acting as a control signal of the compensation unit; and a signal output terminal connected to an output terminal of the pull-up output unit, an output terminal of the pull-down output unit and an output terminal of the compensation unit.

Abstract: A circuit for converting a first voltage to a second voltage in a communication system is disclosed. The circuit includes a pass transistor including a first terminal, a second terminal and a gate, wherein the first terminal is coupled with the first voltage. The circuit is also includes an error amplifier. The error amplifier includes a first input that is coupled with a constant reference voltage and a second input that is coupled with a first switch that is coupled with an output port. A second switch is included and is coupled between the first voltage and an output of the error amplifier. The output of the error amplifier is coupled with the gate of the pass transistor. A third switch is included and is coupled between ground and the output of the error amplifier. The second switch is configured to be driven by a first one shot pulse generated from an input signal of the communication system and the third switch is configured to be driven by a second one shot pulse generated from the input signal.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. The first transistor comprises a drain terminal coupled to an input voltage node, a source terminal coupled to a first node, and a gate terminal coupled to a second node. The second transistor comprises a drain terminal coupled to a third node, a source terminal coupled to a fourth node, and a gate terminal coupled to a fifth node. The third transistor comprises a drain terminal coupled to a sixth node, a source terminal configured to couple to a gate terminal of a switching transistor, and a gate terminal coupled to a seventh node. The first capacitor is coupled between the first node and the third node. The second capacitor is coupled between the fourth node and the sixth node.

Abstract: An auxiliary circuit for outputting a supplying voltage or a detection signal includes a normally-on device and a signal processing circuit. A drain terminal of the normally-on switching device is coupled to a first terminal, a gate terminal of the normally-on switching device is coupled to a second terminal. An input voltage between the first terminal and the second terminal switches between two different levels. The signal processing circuit is configured to output the supplying voltage or the detection signal according to a voltage at a source terminal of the normally-on switching device.

Abstract: The present disclosure provides a gate driving circuit, a current adjusting method thereof, and a display device. The gate driving circuit includes at least one gate driving sub-circuit. Each gate driving sub-circuit includes an output circuit and a current limiting circuit. The output circuit is configured to output a gate driving signal. The current limiting circuit is electrically connected to the output circuit. The current limiting circuit is configured to limit a current magnitude of the gate driving signal.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A high-side switching transistor of a rectifier circuit is driven by a high-side driver circuit to supply current to an output node. The high-side driver circuit is powered between a capacitive bootstrap node and the output node. A boot charge circuit charges the bootstrap capacitor by supplying current to the bootstrap node. The boot charge circuit includes: a first current path that selectively supplies a first charging current to the bootstrap node when the rectifier circuit is operating in a switching mode; and a second current path that selectively supplies a second charging current to the bootstrap node when the rectifier circuit is operating in a reset mode.

Abstract: A transmission/reception device for a bus system, and a method for reducing conducted emissions, are provided. The transmission/reception device has a transmission stage that has a first and a second transmission block, the first transmission block being configured to transmit a transmitted signal onto a first bus wire of a bus of the bus system, in which bus system exclusive, collision-free access by a subscriber station to the bus of the bus system is at least temporarily guaranteed, and the second transmission block is configured to transmit the transmitted signal onto a second bus wire of the bus; a reception stage for receiving the bus signal transferred on the bus wires; and an emissions reduction unit for controlled switching in of a capacitance unit in parallel with the second transmission stage in order to reduce conducted emissions of the transmission/reception device.

Abstract: A bootstrap diode circuit includes an anode for coupling to a power supply voltage terminal and a cathode for coupling to a bootstrap voltage terminal. The bootstrap diode circuit also includes a high-voltage p-type metal-oxide-semiconductor (PMOS) transistor, having a source forming the cathode of the bootstrap diode circuit and a drain forming the anode of the bootstrap diode circuit. The high-voltage PMOS transistor has a breakdown voltage higher in magnitude than a voltage drop between a maximum bootstrap voltage and the power supply voltage.

Abstract: A method and a charging circuit are provided for flexible bootstrapping in power electronics circuits. The charging circuit includes a blocking diode, at least one bootstrap transistor, at least one resistor and at least one electrical component that is designed to conduct a current flow when a predetermined potential difference is exceeded. An energy storage device used for controlling a power semiconductor switch and a source/emitter potential of the power semiconductor switch are at the same potential. Charging of the energy storage device is effected as soon as the potential of a supply voltage is above a potential of the energy storage device. Overcharging is prevented as soon as the predetermined potential difference in the electrical component is exceeded, and discharging of the energy storage device is prevented by the blocking diode.

Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A method for high-speed voltage level translation includes biasing a high-voltage (HV) gate of an HV transistor to an intermediate voltage with a bias device. A low-voltage (LV) transistor is activated with a positive voltage transition applied to an LV gate of the LV transistor, wherein the HV transistor is connected in series between an output and an LV drain of the LV transistor. The intermediate voltage is bootstrapped to a bootstrapped voltage in response to the positive voltage transition on the LV gate coupled to the HV gate through a capacitor therebetween. The output is discharged. A time constant, defined by a resistance of the bias device and a capacitance of the capacitor, is greater than a minimum time constant, thereby maintaining the bootstrapped voltage on the HV gate at or above a drive voltage for a minimum period to discharge the output to a minimum voltage.

Abstract: A system includes a trickle charge control circuit coupled to a charge pump and a motor driver circuit. The trickle charge control circuit is configured to sense a voltage at a bootstrap capacitor voltage node (VBST) of the motor driver circuit; as a result of the voltage at VBST being greater than a voltage at an input voltage node (VIN), couple a charge pump voltage node (VCP) to VBST of the motor driver circuit, where a voltage at VCP is greater than the voltage at VIN; and as a result of the voltage at VBST being less than the voltage at VIN, decouple VCP from the charge pump from VBST of the motor driver circuit.

Abstract: A laser uniformly machining apparatus and method thereof are provided. The apparatus includes a laser unit, a shaping element, a collimating element, a scaling element and a focusing element. The laser unit provides a laser beam for machining. The shaping element shapes the laser beam into an annular beam. The collimating element modifies the direction of the annular beam in accordance with the direction of an optical axis to turn the annular beam into a collimated annular beam. The scaling element adjusts the collimated annular beam in accordance with a scaling ratio to produce a scaled annular beam. The focusing element focuses the scaled annular beam. The scaled annular beam is produced by the scaling element to form a focused beam having a uniformly distribution of light intensity in the direction of the optical axis.

Abstract: A switch-node rising edge detection circuit is provided for a switched-mode DC/DC boost converter. A high-side gate-driver couples a gate of the high-side NMOS power transistor to either a first terminal of a bootstrap capacitor or the switch-node. The detection circuit includes an AND gate that receives an activation signal on a first input and provides a switching signal to the high-side gate-driver. A PMOS transistor is coupled in series with an inverter between the first terminal of the bootstrap capacitor and a second input of the AND gate. The inverter receives supply voltages from the first terminal of the bootstrap capacitor and the switch-node. The gate of the PMOS transistor receives the activation signal. An NMOS transistor is coupled between an output voltage and a node between the PMOS transistor and the inverter. A gate of the NMOS transistor is coupled to the bootstrap capacitor's first terminal.

Abstract: It is an object of one or more embodiments of the present disclosure to provide a power stage overdrive circuit, at low supply voltages, that can be enabled/disabled on the fly. The power stage overdrive circuit increases the overdrive of a power switch to allow for simple power stage architecture with high voltage PMOS and NMOS devices. The power stage overdrive circuit comprises a driver, configured to drive the power switch having a control terminal, for example a gate terminal, and a boost circuit, further comprising a boost capacitor having a first terminal coupled to a power supply, for example a battery, and a second terminal coupled to the control terminal, configured to provide an overdrive voltage to the control terminal to turn the power switch on.

Abstract: An electronic device includes: a clock booster including a doubler capacitor, the clock booster configured to precharge the doubler capacitor and provide a boosted intermediate voltage greater than an input voltage; a secondary booster including a booster capacitor, the secondary booster configured to use the voltage stored on the doubler capacitor to generate a stage output greater than the boosted intermediate voltage; and a connecting switch connected to the clock booster and the secondary booster, the connecting switch configured to electrically connect the doubler capacitor and the booster capacitor during a direct charging duration for charging the booster capacitor using source-secondary current from an input voltage supply instead of or in addition to the voltage stored on the doubler capacitor.

Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments, a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions.

Abstract: A method and circuitry for switching current to a load. The circuitry for supplying a current to a load comprises a sensor configured to sense the current supplied via a sensor input and to produce an output signal representing a time derivative of the sensed current, and a switch configured to switch the current, a switching frequency of the switch being controlled by said output signal representing a time derivative of the sense current, thereby producing a switched output current to the load.

Abstract: Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A sample-and-hold circuit having an error correction circuit portion that compensates for charge injection and noise. The error correction circuit portion includes an error-current-accumulating capacitor and a feedback circuit. The error-correction circuit performs error correction during a sampling operation by accumulating, at the error-current-accumulating capacitor, an error current output from an amplifier of the sample-and-hold circuit, and then applying, via the feedback circuit, a voltage boost to an input of the amplifier. The magnitude of the voltage boost depends on a voltage of the error-current-accumulating capacitor, and on various design parameters of the components of the circuit. By appropriately setting the design parameters, the magnitude of the fed-back voltage boost can be made to cancel out error due to charge injection and noise.

Abstract: An output discharge circuit for a load switch may include a capacitor coupled between a power rail of the output discharge circuit and a ground lead, and a diode coupled between a power input of the output discharge circuit and the power rail. The output discharge circuit may charge the capacitor via a current path formed by the diode while power is being supplied to the load switch. When the power supply to the output discharge circuit is turned off, the diode may prevent the capacitor from discharging through the current path, and the stored charge on the capacitor may be used to power the output discharge switch for a period of time after the power supply has been turned off. In this way, the output discharge circuit may continue to discharge the output of the load switch even when power is no longer being supplied to the load switch.

Abstract: The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire. One of a source and a drain of the third transistor is connected to a second wire, the other of the source and the drain thereof is connected to the gate electrode of the second transistor, and a gate electrode thereof is connected to a fourth wire.

Abstract: An inverter includes first, second, third, fourth, and fifth transistors, and first and second capacitors. The transistors and capacitors are connected in such way that the reverse conduction of the second transistor is prevented through controlling the gate electrode of the second transistor and maintaining the electrical potential at the gate electrode of the fifth transistor by the second capacitor. The electrical potential at the gate electrode of the fifth transistor is maintained stable when a first clock signal changes from high to low (when the first to fifth transistors are NMOS transistors) or from low to high (when the first to fifth transistors are PMOS transistors), so that the output signal of the inverter may not be affected by a change of the first clock signal, thus enabling the inverter to generate a stable output signal and a display panel comprising the inverter to obtain a better display effect.

Abstract: A voltage level shifter to provide an output logic signal in response to an input logic signal, where the input logic signal is in a first voltage domain and the output logic signal is in a second voltage domain. In one embodiment, a voltage boost module provides a boosted voltage in response to the input logic signal going HIGH, where the boosted voltage is sufficient to turn OFF a pull-up transistor operating in the second voltage domain. Contention among pull-down and pull-up transistors may be avoided.

Abstract: A device including a memory cell including a variable resistive memory element; a capacitor; a voltage generation circuit; and a switch circuit including a first switch and a second switch. The first switch is coupled between the voltage generation circuit and the capacitor without an intervention of the second switch. The second switch is coupled between the capacitor and the memory cell without an intervention of the first switch. The first switch is configured to take an on-state during a first period of time and an off-state during a second period of time following the first period of time and the second switch is configured to take an off-state during the first period of time and an on-state during the second period of time.

Abstract: A drive capability of a dynamic logic circuit is improved. A logic circuit includes a dynamic logic circuit, a first output node, a first transistor that is diode-connected, and a capacitor. The dynamic logic circuit includes a second output node. The first transistor and transistors in the dynamic logic circuit have an n-type conductivity or a p-type conductivity. The first output node is electrically connected to a first terminal of the capacitor, and the second output node is electrically connected to a second terminal of the capacitor. A first terminal of the first transistor is electrically connected to the first output node, and a first voltage is input to a second terminal of the first transistor.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: Devices and methods for analog to digital conversion are provided. The device can have a supply voltage coupled to a bootstrap circuit operable to provide a boosted voltage during a first period defined by a sample phase (Ps) signal and a hold phase (Ph) signal. The device can also have a sampling circuit having an input node and operable to sample an input signal supplied to the input node. The device can also have a switching circuit having a first switch and a second switch. The switching circuit can be coupled to the bootstrap circuit and to the sampling circuit. The switching circuit can be configured to isolate the input node from shorting currents to the supply voltage for a portion of the first period.