Abstract: A high-side transistor driver including a driver circuit for generating a driving signal to drive a high-side transistor is provided. A floating supply terminal provides a supply voltage to the driver circuit. A floating ground terminal is connected to a source of the high-side transistor. A bootstrap diode is coupled between the floating supply terminal and a voltage source. A capacitor is connected to the bootstrap diode and is coupled between the floating supply terminal and the floating ground terminal. A high-voltage transistor is used for switching off the driving signal and the high-side transistor in response to an input signal. A speed-up capacitor is coupled to the driver circuit for speeding up the driving signal. Furthermore, the positive feedback circuits in the driver circuit further accelerate the driving signal and save power for the driver circuit.

Abstract: A bootstrapping circuit capable of sampling input signals beyond a supply voltage is disclosed. In one embodiment, the bootstrapped circuit is implemented having a reduced area and/or power consumption requirement.

Abstract: A solution for increasing the switching speed of a bus driver circuit includes a pair of transistors controlled by a pair of control circuits. Pumping circuits are placed between the control electrodes of the transistors to speed up the conduction of one of the transistors immediately after the other is in an off state. An output interface for a differential bus is produced using two bus driver circuits, the control signals of one of the circuits being inverted relative to the other of the circuits.

Abstract: A buffer circuit has a first transistor and a second transistor in a cascode, and a buffer switch coupled from an output of the buffer to a gate of the second transistor. The buffer circuit is bootstrapped by a bootstrap capacitor, a diode circuit, and a bootstrap switch. The bootstrap capacitor is coupled from the output to the gate of the second transistor through the bootstrap switch. A potential difference is set up across the bootstrap capacitor through the diode circuit. When a low input is given to the buffer circuit, the second transistor turns off and the output goes to a high bias voltage through the first transistor. When a high input is given, the first transistor turns off, the second transistor turns on, and as the output goes low, the gate of the second transistor is bootstrapped to drop the output completely down to a low bias voltage.

Abstract: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present invention provides a supplemental current that is active during this transition period to supply the missing current. The present disclosure also details a common mode circuit that maintains a stable common mode output level to help control EMI issues when the power supply for the driver changes.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.

Abstract: It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided.

Abstract: A source follower in which any one of the following three modes is selected by a plurality of switching elements: a first mode in which a first potential is supplied to a gate of a transistor and an input potential is supplied to a first electrode of a capacitor respectively and a second electrode of the capacitor and a source of the transistor are connected, a second mode in which an input potential is supplied to the first electrode and the gate of the transistor and the second electrode floats, and a third mode in which the first electrode and the gate of the transistor are connected and a potential thereof floats and a second potential is supplied to the second electrode, a drain of the transistor is supplied with a third potential, and a potential of the source of the transistor is supplied to a subsequent circuit.

Abstract: A high-voltage switching circuit comprises: a high-voltage switch configured to transfer a high voltage; a pumping circuit configured to boost signals of first, second, and third nodes by conducting pumping operations in response to a plurality of clock signals; and a drive signal transmission circuit configured to boost the signal of the second node at a constant rate while maintaining a voltage level of the third node regardless of variation of a voltage level at the first node and transfer the boosted signal of the second node to the high-voltage switch, activating the high-voltage switch.

Abstract: Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64.

Abstract: The present invention provides an output buffer providing multiple voltages including an arrangement of bootstrapping capacitors, and a charge replenishing mechanism which provides continuous pulses to the arrangement of bootstrapping capacitors, thereby, maintaining voltage on the bootstrapping capacitors.

Abstract: An output driver circuit including a transistor for pulling down an output terminal voltage and a charge pump for driving an input of the transistor to pull-down the output terminal voltage substantially to zero volts in response to a selected level of an input signal.

Abstract: A circuit for generating word line control signals that have a stable boosting margin of the sub-word line driver: The circuit includes a first address buffer, a pre-decoder unit, a second address buffer, a main decoder and a circuit for generating a word-line boosting signal. The second address buffer delays a refresh count signal for a predetermined time and generates an enable signal having a predetermined pulse width in response to a row address setup signal and the delayed refresh count signal, and receives and latches a pre-decoded row address signals to output decoded row address signals in response to the enable signal. Accordingly, the circuit for generating word line control signals is capable of obtaining a stable self-boosting margin when the semiconductor memory device operates in a refresh mode.

Abstract: A system and method for controlling boot options for a workstation on a computer network includes initiating a boot on a workstation in communication with the network, downloading an application to the workstation from a server in communication with the network, gathering information about the workstation using the bootstrap code and forwarding the information to a policy server in communication with the network. The system and method also include determining, by the policy server, based on the forwarded information and based on a boot policy stored in a policy directory of the network, at least one boot option for booting the workstation, forwarding the boot option to the workstation, requesting, by the workstation, a boot image corresponding to the boot option, forwarding of the boot image to the workstation and completing the boot of the workstation based upon the boot option received by the workstation.

Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.

Abstract: An output circuit includes a source follower constituted by a n-channel MOS transistor, having a drain connected to a power source and a source connected to an output terminal, and applying an output voltage to a load through the output terminal when a gate is charged, a voltage detector determining if the output voltage is at a first voltage or at a second voltage level, a first discharge circuit discharging the gate of the source follower according to an inputted turn-off signal when the output voltage is at the first voltage level, and stopping discharging the gate of the source follower when the output voltage decreases to the second voltage level and a second discharge circuit discharging the gate of the source follower more gradually than the first discharge circuit does according to the turn-off signal when the output voltage decreases from the first voltage to the second voltage level.

Abstract: A bootstrap driver comprises an output stage having an N-type high-side transistor and a low-side transistor, also of the N-type, which are arranged in series between a positive supply terminal and a negative supply terminal. A control circuit of the high-side transistor and a control circuit of the low-side transistor are respectively supplied by a first voltage regulator and a second voltage regulator, which are mutually independent. A recovery diode is connected by its anode to the output of the first voltage regulator and by its cathode to the positive supply terminal, in order to conduct the reverse current of a bootstrap diode when the output of the circuit switches from a low state to a high state.

Abstract: Methods and apparatus provide for front-end processing of a first differential output current, whereby a first differential output current is received and a second differential output current having reduced spurious content is produced. Current steering is used to divide, and reassemble, the first differential output current so as to provide an output signal with reduced spurious content. Current steering is implemented by a return-to-zero circuit that is coupled to the terminals of a first differential current output stage. During a first phase, the return-to-zero circuit provides a differential output current equal to the first differential current output. During a second phase, the return-to-zero circuit provides a differential output current equal to zero. The current steering return-to-zero circuit is implemented with MOSFETs or any other suitable electrical circuit element that provides the ability to controllably pass or refrain from passing current.

Abstract: There is provided a semiconductor device in which fabrication steps can be reduced by constructing a circuit using only TFTs of one conductivity type and in which a voltage amplitude of an output signal can be normally obtained. A capacitance (205) is provided between a gate and a source of a TFT (203) connected to an output node, and a circuit formed of TFTs (201) and (202) has a function to bring a node a into a floating state. When the node ? is in the floating state, a potential of the node a is caused higher than VDD by using gate-source capacitance coupling of the TFT (203) through the capacitance (205), thus an output signal having an amplitude of VDD-GND can be normally obtained without causing amplitude attenuation due to the threshold value of the TFT.

Abstract: A charge pump includes a pair of capacitors each having a first terminal coupled to a pumped node. A charge voltage is initially applied to the pumped node to charge the capacitors. A second terminal of the first capacitor is then pumped to increase the voltage at the pumped node, with the charge of the first capacitor being shared with the second capacitor. The second terminal of the second capacitor is then pumped to again increase the voltage at the pumped node. The pumped node is then coupled to an output terminal.

Abstract: A method and apparatus for providing a preselected voltage to test or repair a semiconductor device. The apparatus includes a one-stage pump and a transfer device. The one-stage pump is adapted to access a first voltage and provide a second voltage using the first voltage. The transfer device is capable of providing the first voltage to a node using the second voltage.

Abstract: An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.

Abstract: There is provided a control circuit which instructs, using a control signal, validation and invalidation of operations of an input/output interface circuit suitable for a bus such as the IIC bus and maintains an output element included in the input/output interface circuit to the OFF stage without relation to voltage change at the external terminal corresponding to the input/output interface circuit in response to invalidation of operation due to the control signal. Accordingly, a semiconductor device which can be used flexibly with a simplified structure and prevents erroneous output in the output circuit corresponding to the IIC bus can be obtained.

Abstract: In a first phase a first sensor signal, essentially comprising the current offset signal of the sensor, is applied to the input of an electronic circuit. The first sensor signal is fed to a first signal path and stored therein. In a second phase a second sensor signal, comprising the current offset signal and a time-dependent measured signal, is applied to the input and the stored first sensor signal is fed to the input by means of the first signal path, such that essentially the time dependent measured signal is fed by means of a second signal path coupled to the input.

Abstract: An embodiment of a graphics device that maintains load balance on a graphics bus when an upgrade graphics device is installed is disclosed. The embodiment includes load balancing buffers for the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB# on a 2X mode AGP graphics device. The load balancing buffers couple the 2X mode AGP graphics device to the strobe compliment signals AD_STB0#, AD_STB1#, and SB_STB#, but the load balancing buffers are not connected to any internal circuits within the 2X mode AGP graphics device. The load balancing buffers provide equal capacitive loading between the strobe signals AD_STB0 , AD_STB1 , and SB_STB and their compliment signals AD_STB0#, AD_STB1#, and SB_STB# when an upgrade 4X mode AGP graphics device is installed.

Abstract: An apparatus and method for selectively enhancing the soft error rate (SER) immunity of a dynamic logic circuit. The apparatus includes a bootstrap capacitor coupled to a precharge input signal and a dynamic node of the dynamic logic circuit, and a device, such as an FET, for selectively connecting the bootstrap capacitor to the dynamic node.

Abstract: The signal transmission circuit is provided, said signal transmission circuit being capable of stable operations even with a source power of low voltage and a fast operation. The signal transmission circuit comprises plural stages of circuit in each of which the pulse voltage according to the driving pulse is sequentially outputted.

Abstract: A capacitor-coupling acceleration apparatus is an accelerating circuit capable of being applied to interconnect lines in an integrated circuit in order to reduce delay owing to parasitic resistance and capacitance of the interconnect lines in the integrated circuit. The apparatus can be disposed between the interconnect lines. When a signal transmitted on the interconnect line has a change from a low-level voltage to a high-level voltage, the apparatus detects the voltage level change of the signal and provides a charging loop to charge the interconnect line, thereby accelerating the change from the low-level voltage to the high-level voltage. When a signal on the interconnect line has a change from the high-level voltage to the low-level voltage, the apparatus detects the voltage level change of the signal and provides a discharging loop to discharge the interconnect line, thereby accelerating the change from the high-level voltage to the low-level voltage.

Abstract: An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.

Abstract: The high-side transistor driver according to the present invention includes a high-side transistor, a low-side transistor, a drive-buffer and an on/off transistor. When the low-side transistor is turned on, a charge-pump diode and a bootstrap capacitor produce a floating voltage. The drive-buffer will propagate the floating voltage to switch on the high-side transistor. The on/off transistor is used to switch the drive-buffer. The high-side transistor drive further includes a speed-up circuit. The speed-up circuit has a capacitive coupling for generating a differential signal. When the on/off transistor is turned off, the speed-up circuit accelerates the charge-up of the parasitic capacitor of the on/off transistor, thus accelerating high-side transistor switching.

Abstract: A capacitive pump circuit suitable for use in loop powered level measurement and time of flight ranging systems. The capacitive pump circuit comprises an input buffer, a level shifter and an output stage. The input buffer receives a clocking signal which is also coupled to the input of the output stage through the level shifter. The output from the input buffer is switched by the output stage to charge a capacitor and generate a voltage output which has the opposite polarity of the voltage supply rail. According to another aspect, a capacitive voltage doubler circuit is provided which is also suitable for use in loop powered level measurement and time of flight ranging systems.

Abstract: A bus interface having a first circuit based on a first pair of transistors of opposite types having a control electrode and a common electrode for providing a first output potential. A second circuit has a second pair of transistors of opposite types and having a common electrode for providing a second potential switching in opposite direction from the former. This device has a first capacitive coupling means for feeding a portion of the signal existing at said first potential back into said control electrode of said second transistor pair and second capacitive coupling means for feeding a portion of the signal existing at said second potential back into said control electrodes of said first transistor pair. Thus variations between the rise and decay times of the transistors of each pair can be compensated for.

Abstract: A CMOS inverter capable of operating at low voltages is provided. The gate of a p-channel MOS transistor and the gate of an n-channel MOS transistor are AC coupled to an input terminal via first and second capacitors, respectively. Signals whose amplitude centers are optimized according to the threshold voltages of the p- and n-channel MOS transistors by bias voltages from first and second variable voltage sources, respectively, are supplied to the gates of these MOS transistors. In consequence, the CMOS inverter can operate at high speeds at low power supply voltages without being affected by the threshold voltages.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A circuit with a large load driving capability, which is structured by single polarity TFTs, is provided. With a capacitor (154) formed between a gate electrode and an output electrode of a TFT (152), the electric potential of the gate electrode of the TFT (152) is increased by a boot strap and normal output with respect to an input signal is obtained without amplitude attenuation of an output signal due to the TFT threshold value. In addition, a capacitor (155) formed between a gate electrode and an output electrode of a TFT (153) compensates for increasing the electric potential of the gate electrode of the TFT (152), and a larger load driving capability is obtained.

Abstract: A programmable gate array comprising: a plurality of logic modules, each logic module having at least one output coupled to an isolation transistor, each isolation transistor in each of the plurality of logic modules having a gate; and a charge pump having a pump-voltage output line coupled to the gates of each isolation transistor in each of the plurality of logic modules. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 CFR 1.72(b).

Abstract: Embodiments of the present invention relate to a voltage clamp circuit including a transistor and a switch. The switch is coupled between a gate of the transistor and a source or a drain of the transistor. Embodiments of the present invention can quickly raise and lower a voltage level supplied to a memory device.

Abstract: The invention simplifies the configuration of a level shifter and to allow fast operation. A level shifter includes a capacitor, to a first end of which a low-amplitude logic signal is input; first TFTs to apply an offset voltage to a second end of the capacitor; a capacitor, to a first end of which the low-amplitude logic signal is input; third TFTs to apply an offset voltage to a second end of the capacitor; and second TFTs connected in series between a supply line of a power supply voltage for a high-amplitude logic signal and a supply line of a reference voltage therefor, a node therebetween serving as an output terminal. A threshold voltage of one of the second TFTs is set to be not higher than the offset voltage applied by the first TFTs , and an offset voltage of the other of the second TFTs is set to be higher than or equal to the offset voltage applied by the third TFTs.

Abstract: A logic state transition sensor circuit. The logic state transition sensor circuit detects and records transitions in voltage corresponding to a transition of a digital logic state (high to low; low to high). The logic state transition sensor circuit may include a sensing circuit containing sensing and amplification elements and a recording circuit containing recording elements. When a logic state transition occurs at an input of the sensing circuit, a positive logic pulse may be generated. Propagation of the logic pulse to the recording circuit causes a charge to be transferred to an output stage capacitor. Repeated logic state transitions cause similar incremental increases in the charge of the output stage capacitor. Charge transfer is governed by ratios of capacitors internal to the recording circuit and hence may be insensitive to process variation. The output stage capacitor may output a voltage representative of a number of logic state transitions sensed.

Abstract: A capacitive pump circuit suitable for use in loop powered level measurement and time of flight ranging systems. The capacitive pump circuit comprises an input buffer, a level shifter and an output stage. The input buffer receives a clocking signal which is also coupled to the input of the output stage through the level shifter. The output from the input buffer is switched by the output stage to charge a capacitor and generate a voltage output which has the opposite polarity of the voltage supply rail. According to another aspect, a capacitive voltage doubler circuit is provided which is also suitable for use in loop powered level measurement and time of flight ranging systems.

Abstract: For a minimal electromagnetic radiation during transition between its states, a transmitter for a two-wire, differential databus on which a dominant state can be impressed by means of the transmitter in an active state of the transmitter, and which is in a recessive state when all transmitters connected to the databus are in a passive state, is characterized in that the transmitter is provided with a capacitance (6) and switching means (7, 8, 9, 10) by means of which the capacitance (6) can be alternatively coupled to an electric source (11) or between the two databus lines (1, 2), and in that the switching means (7, 8, 9, 10) charge the capacitance (6) by means of the electric source (11) during periods when the transmitter is in a passive state, and couple the capacitance (6) between the two databus lines (1, 2) during periods when the transmitter is in an active state.

Abstract: The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A circuit for producing an output signal at an output thereof in response to an input signal at an input thereof is comprised, in one embodiment, of a first switch for connecting the output to a first voltage source and a second switch for connecting the output to a second voltage source. A first control switch is provided for turning off the first switch in response to the logic level of the input signal while a second control switch is provided for turning off the second switch in response to the logic level of the input signal. An integrator is responsive to the input signal for turning on one of the first and second switches depending on the logic level of the input signal. A method of operating such a circuit is also disclosed.

Abstract: A step-up circuit is equipped with a plurality of serially connected rectification elements Q1, Q2, . . . between a first node and a second node, a plurality of capacitors C1, C2, . . . connected to connection points of the plurality of rectification elements, respectively, and an oscillation loop that is formed by circularly and serially connecting an odd number of inversion devices NAND, INV1, INV2, . . . , each inverting an input signal and outputting the same, and supplies an alternating current signal having a specified phase to the plurality of capacitors.

Abstract: In one aspect, a method for charge recovery in dynamic circuitry includes discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. The dynamic node is charged during a precharge interval by a voltage source and precharge timing circuitry coupled to the dynamic node responsive to a precharge signal. The charging includes transferring the charge from the capacitor back to the dynamic node.

Abstract: Disclosed is a voltage translation circuit 400 that can translate different voltage levels (transmit logics between circuits operating at different voltage levels) faster but consumes less energy than that of prior art. The voltage translation circuit 400 of the present invention utilizes two transistors (transmission NMOS transistor 160 and transmission PMOS transistor 200) in parallel and in combination with a bootstrap circuit 195 consisting of a pull-up control CMOS inverter 170, 180 and a pull-up PMOS transistor 190. When node 140 rises from 0V to 3V (LVDD, i.e. logic 1), transmission PMOS transistor 200 helps to raise the input voltage to pull-up control CMOS inverter 170, 180 faster and therefore helps to turn on pull-up PMOS transistor 190 faster and hence raise the voltage of node 155 faster. This in turn helps turn off PMOS transistor 170 sooner, and hence stop the transition current going through transistors 170 and 180 sooner.

Abstract: The present invention relates to a logic gate circuit capable of reducing sub-threshold leakage current by applying the reverse voltage to the gate of a turned-off MOS device. The logic gate circuit in accordance with the present invention includes a CMOS logic gate having PMOS devices and NMOS devices with a low threshold voltage, a first voltage generator applying a first reverse voltage to the PMOS device of the CMOS logic gate during a pull-down operation, and a second voltage generator outputting a second reverse voltage to the NMOS device of the CMOS logic gate during a pull-up operation. The first voltage generator outputs a voltage greater than the source voltage by the threshold voltage to the first MOS device when the second MOS device performs a pull-down operation, and the second voltage generator outputs a voltage smaller than the earth voltage by the threshold voltage when the first MOS device performs a pull-up operation.

Abstract: A semiconductor device capable of preventing malfunctions of instantaneous lighting, and comprises a drive circuit, a drive control circuit, and a power supply circuit. The power supply circuit has a boosting circuit which is provided with a first power supply potential VDD being a ground potential from an external power supply and a second power supply potential VSS, being a potential other than the ground potential, and raises the absolute value of the second power supply potential VSS and charges to the capacitor; and a bias generating circuit generating a potential to be supplied to the drive circuit and drive control circuit based on the output potential of the boosting circuit.