Abstract: A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

Abstract: An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit.

Abstract: An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS transistors of a transmission gate to turn on the transistors more strongly and speed the passage of data signals.

Abstract: A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.

Abstract: A voltage translator programmably converts signals generated from a first power-supply voltage to a second power-supply voltage, or vice-versa. In response to control signals, bootstrap switches connect either the first or second power supply to a first internal supply, and either the second or first power supply to a second internal supply. A pair of inverters are sourced by the first power supply and generate true and complement data signals. Cross-coupled p-channel load transistors are sourced by the second internal power supply. A differential pair of n-channel transistors have drains connected to the drains of the load transistors, and gates driven by the true and complement data signals. The bootstrap switches use boosted signals above the power-supply voltages to programmably connect full-voltage power supplies to the internal supplies.

Abstract: A buffer circuit includes a delay circuit which is interposed between a signal source and a following circuit. The delay circuit propagates a signal from an input to an output; the signal has associated desired timing relationships between its rising and falling edges. The delay circuit controls the propagation delays of the signal's rising and falling edges such that when the signal arrives at a selected downstream node, it has the desired timing relationships. The delay circuit adjusts the propagation delays in accordance with two correction signals: one which reduces errors induced by imperfections in the signal path through which the test signal propagates, and one to reduce errors due to thermal effects that arise when propagating a periodic test signal having a duty cycle other than 50% through the signal path.

Abstract: An output buffer includes a reference capacitor; a constant current source connected in series with the reference capacitor, for generating a reference voltage with a constant gradient by charging the reference capacitor; a first transistor having its source connected to a capacitive load, and its gate connected to the connecting point of the reference capacitor and the first constant current source to be supplied with the reference voltage; a second transistor connected between the drain of the first transistor and a voltage source; a third transistor connected between the capacitive load and the voltage source; and a fourth transistor connected to the control terminal of the second transistor and to the control terminal of the third transistor, for switching the second and third transistors from an OFF state to an ON state when the first transistor is turned on.

Abstract: A voltage-adder circuit, which adds the charge stored on a capacitor during a switch off-time, to the voltage of the input battery/power-supply, to provide an output voltage greater than the input voltage. The circuit is especially well-suited for use as an LED driver, and may be also used as a voltage booster for low-voltage electronic circuitry, such as electronic watches; as a back-bias generator for use inside integrated circuits; and, as a gate-bias-voltage generator, for use with depletion-mode GaAsFETs, such as are used in the transmitters of cellular telephones. The circuit obtains high efficiency operation by the use of inductors to charge a storage capacitor. Switches may be added. The invention includes a novel self-operating switch.

Abstract: An output driver includes multiple boot circuits to drive a pull-up signal of a data driver. A control circuit selects a fully precharged boot circuit when the data output by the output driver is a high signal. The remaining boot circuits not selected are allowed to fully precharge during this time in preparation for a subsequent data high signal. Consequently, any precharge delay time can be masked by selecting a fully precharged boot circuit when driving a subsequent pull-up signal.

Abstract: A semiconductor device capable of preventing malfunctions of instantaneous lighting, and comprises a drive circuit, a drive control circuit, and a power supply circuit. The power supply circuit has a boosting circuit which is provided with a first power supply potential VDD being a ground potential from an external power supply and a second power supply potential VSS, being a potential other than the ground potential, and raises the absolute value of the second power supply potential VSS and charges to the capacitor; and a bias generating circuit generating a potential to be supplied to the drive circuit and drive control circuit based on the output potential of the boosting circuit.

Abstract: A semiconductor integrated circuit includes a pass transistor logic circuit and an output buffer. The output buffer compensates for an output level of the pass transistor logic circuit. Preferably, the output buffer includes a bootstrap circuit with a capacitor. The capacitor is preferably connected between a gate of an output transistor and an output terminal. Such an arrangement allows for the obtaining of a high voltage at the output terminal.

Abstract: A pulse width modulation (PWM) amplifier of the type including power transistors connected in totem-pole fashion and a bootstrap capacitor used to bias at least one of the power transistors into the conductive state. The improvement wherein the bootstrap capacitor is refreshed only to the extent needed to provide a higher effective maximum duty cycle.

Abstract: An output-buffer circuit includes a first output transistor connected between a first power line and an output node, a second output transistor connected between the output node and a second power line, an output-transistor control circuit which controls an on/off state of the first and second output transistors, and a capacitor for controlling a through-rate of an output signal output to the output node, wherein the output-transistor circuit includes a pull-up circuit connected between the first power line and a given node, a pull-down circuit connected between the given node and the second power line, a first switch device connected between a gate of the first output transistor and the given node, a second switch device connected between the first power line and the gate of the first output transistor, a third switch device connected between a gate of the second output transistor and the given node, and a fourth switch device connected between the gate of the second output transistor and the second power li

Abstract: A series resonant circuit includes a series connected power source, inductor and capacitance. The resonant capacitance includes two separate capacitors, connected to form a voltage doubler. Two rectifiers clamp the resonant capacitors' voltage to the output voltage, so the voltage on the resonant capacitors is limited under overload conditions. Current control may be achieved by modulation of the power source frequency.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: The present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and is the type comprising a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage and a voltage regulator for the control terminals of said transistors. The regulator is a voltage booster using at least one bootstrap capacitor to increase the current flowing in the final stage by boosting the voltage applied to said control terminals.

Abstract: A deskew circuit for synchronizing output signals from a fanout buffer. The circuit includes one capacitive element coupled to each of the buffer's output nodes. Each capacitive element is also coupled to a common floating bus. The capacitive element is preferably a capacitor and the common floating bus is electrically isolated from any power rails. The bus may be formed of polysilicon or metal.

Abstract: A driving circuit supplied by a supply voltage and a reference voltage, generates an output signal and comprises a first circuit adapted to selectively couple the output signal to the reference voltage or to an internal voltage line internal to the driving circuit in response to a first control signal. The driving circuit also includes a switching circuit adapted to selectively couple the internal voltage line to the supply voltage. A boosting circuit is connected to the internal voltage line and is adapted to bring the internal voltage line to a boosted voltage. The switching circuit and the boosting circuit are controlled by a second control signal to be alternatively activatable, in such a way to bring the internal voltage line either to the supply voltage or to the boosted voltage.

Abstract: A programmable device has digital logic elements and a programmable interconnect structure employing antifuses, the antifuses being programmable to connect selected ones of the digital logic elements together. During normal circuit operation, a first power input terminal is used to power the digital logic elements with a first supply voltage received on the first power input terminal. During normal circuit operation, a second power input terminal is used to protect circuitry of the programmable device from high voltage signals that may be driven onto terminals of the programmable device by circuitry external to the programmable device. During antifuse programming, the second power input terminal is used to drive charge pumps of programming drivers and/or programming control drivers.

Abstract: An output driver includes multiple boot circuits to drive a pull-up signal of a data driver. A control circuit selects a fully precharged boot circuit when the data output by the output driver is a high signal. The remaining boot circuits not selected are allowed to fully precharge during this time in preparation for a subsequent data high signal. Consequently, any precharge delay time can be masked by selecting a fully precharged boot circuit when driving a subsequent pull-up signal.

Abstract: The tri-state logic gate circuit is preferably made up of a first inverter circuit which selectively outputs one of the power supply voltage and a ground potential, a second inverter circuit which selectively outputs one of the first inverter circuit output and the boosted power supply voltage, a resistor connected between the first and second inverter circuits, and a latch circuit. Accordingly, the tri-state logic gate circuit can avoid latch-up.

Abstract: A plurality of output transistors for an output buffer of a semiconductor device are provided in parallel. Potentials to be applied to gates of output transistors are set to different levels upon conduction of the output transistors. By sequentially rendering the transistors conductive in the order of increasing voltage during conduction, rapid flow of a large amount of current is prevented, thereby reducing ringing. More preferably, the transistors are increased in size according to the order of conduction of the output transistors.

Abstract: An integrated circuit I/O buffer has an output driver. The output driver includes first, second and third voltage supply terminals and a pad terminal. A pad pull-up transistor is coupled in series between the first voltage supply terminal and the pad terminal and has a pull-up control terminal. A pad pull-down transistor is coupled in series between the second voltage supply terminal and the pad terminal and has a pull-down control terminal. A voltage protection transistor is coupled between the pad terminal and the pad pull-down transistor. The voltage protection transistor has a control terminal and a capacitance between the control terminal and the pad terminal. A resistor is coupled in series between the control terminal of the voltage protection transistor and the third voltage supply terminal and forms a resistor-capacitor (RC) circuit with the capacitance.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: two transistors coupled together in the integrated circuit so that upon the application of complementary voltage signals, electrical charge is substantially evenly distributed between output nodes. Briefly, in accordance with one more embodiment of the invention, an integrated circuit includes: a charge recycle circuit including two transistors. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes: a charge recycle circuit including a first and second transistor coupled so as to respectively receive complementary voltage signals at the control voltage port of the first and second transistors. The transistors have a threshold voltage level different from the threshold voltage level of other transistors coupled to the charge recycle circuit.

Abstract: A bootstrap sample and hold circuit accurately acquires and holds values of a high frequency analog input signal, to avoid harmonic distortion of a signal representing the analog input signal in, for example, a pipeline ADC, includes a first sampling MOSFET coupling the analog input signal to a sampling capacitor. A bootstrap circuit includes a bootstrap capacitor. First and second MOSFETs couple the bootstrap capacitor between a first reference voltage and ground in response to pulses of a first clock signal. Third and fourth MOSFETs then couple the bootstrap capacitor between the gate and source of the sampling MOSFET in response to non-overlapping pulses of a second clock signal to apply a constant gate-to-source voltage to the sampling MOSFET, the gate-to-source voltage having a magnitude equal to the difference between a first reference voltage and ground during the pulses of the second clock signal.

Abstract: In a semiconductor device having a plurality of output circuits such as a semiconductor memory device, a drive signal having a boosted voltage level which is produced from a boosting circuit is applied to a gate of a low-level outputting MOS transistor in the output circuit. As a result, even when a potential at the ground wiring line is floated, a substantial decrease of a potential difference between the ground wiring line and the gate of the low-level outputting MOS transistor can be prevented. Also, a signal having a sufficiently high level can be supplied to a gate of a low-level outputting output MOS transistor. As a consequence, delays in the switching operation of the output MOS transistor can be suppressed, and the output circuit can be operated at high speed.

Abstract: A slew-rate limited output driver circuit that minimizes switching current while delivering sufficient peak load currents is disclosed. The circuit of the present invention includes fixed pull-up and pull-down transistors that are designed to dissipate minimum switching current while maintaining a predetermined slew rate. Additional pull-up and pull-down transistors are then switched in parallel to the fixed pull-up and pull-down transistors to drive the output all the way to full logic levels, after the output signal has made most of its transition. In a preferred embodiment, each switched transistor is controlled by a comparator that generates its output by comparing the level of the output signal to a predetermined reference voltage.

Abstract: In an input circuit of a semiconductor device, a CMOS inverter has first and second transistors connected in series between an external power supply and ground and complementarily operating in accordance with an input signal. The first and second transistors have a connection point connected to an output terminal. A first switching device is connected in parallel to the second transistor and turned on/off. A comparator compares a voltage from the external power supply with a predetermined reference voltage and outputs a reference signal representing a comparison result. A logic circuit performs a logical operation between the reference signal from the comparator and the input signal supplied to an input terminal of the CMOS inverter and ON/OFF-controls the first switching device on the basis of a logical operation result.

Abstract: The level converting circuit has first and second transistors of a first conductivity type. The control terminals of the transistors are connected to a first supply potential via the load path of the respective other transistor. A load path of a third transistor of a second conductivity type is connected between the control terminal of the first transistor and a reference-ground potential. The control terminal of the third transistor is coupled to the input of the level converting circuit. A node between the second and third transistors forms the output of the circuit. A fourth transistor of the second conductivity type has a load path connected between the control terminal of the second transistor and the control terminal of the third transistor. A capacitance is connected between the control terminals of third and fourth transistors. A limiter circuit is connected upstream of the control terminal of the fourth transistor.

Abstract: This invention presents an all-N-logic true-single-phase CMOS dynamic logic circuit for high speed operation with a low supply voltage, in which a bootstrapped circuit containing a bootstrap capacitor, an inverter and a PMOS transistor is incorporated to a conventional non-inverting N1-block.

Abstract: An interface circuit is disposed between a generator of control signals and a plurality of electronic switches in order to produce boosted voltage signals corresponding to the control signals for activating the electronic switches. To avoid the use of a capacitor with a high capacitance and thus to reduce an area of the integrated circuit, the interface circuit includes a generator of activation signals and a plurality of voltage multipliers each having an input connected to an output of the control signal generator, an output connected to at least one terminal for activating an electronic switch and two control terminals connected to an activation signal generator. Each voltage multiplier includes MOS transistors operatively coupled in series between the input and the output. The MOS transistors operate in response to the activation signals to produce a boosted voltage on the capacitor.

Abstract: A circuit for generating a boosted voltage includes a logic portion and a switching portion. The logic portion is coupled to receive a clock signal and, in response thereto, provides control signals to an associated switching circuit. During a first portion of the clock signal cycle, the switching circuit pulls an output terminal of the circuit to the supply voltage. During a second portion of the clock signal cycle, the switching circuit utilizes a bootstrap capacitor to boost the output terminal of the circuit to approximately twice the supply voltage, while isolating the output terminal from the supply voltage.

Abstract: A potential across an output terminal (OUT) is applied to a node N2 through a transistor (Tr66) even when a potential across a node N1 is higher than a power source voltage Vdd due to a bootstrap effect. Accordingly, the potentials between the drain and the source electrodes are not higher than the power source voltage Vdd for both a transistor (Tr62) and the transistor (Tr66). This allows circuit designing without setting the withstand voltage for the transistor over the power source voltage Vdd.

Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.

Abstract: A voltage-boosting circuit outputs a boosted voltage at different potentials in response to a mode signal. In a first aspect of the invention, the boosted voltage is produced by two capacitors, both of which are driven when the mode signal is in a first state, and only one of which is driven when the mode signal is in a second state. In second and third aspects of the invention, the boosted voltage is changed by switching a power-supply potential fed to a capacitor in the voltage-boosting circuit. In a fourth aspect of the invention, the boosted voltage is output through two parallel switching elements, both of which switch on when the mode signal is in the first state, and only one of which switches on when the mode signal is in the second state.

Abstract: This invention discloses a 1.5 V bootstrapped pass-transistor-based Manchester-carry-chain circuit suitable for CMOS VLSI using a low supply voltage, in which a bootstrapper circuit is incorporated to enhance the speed performance of the conventional Manchester-carry-chain circuit, which is composed. The bootstrapper circuit contains two P-type metal-oxide-semiconductor (PMOS) transistors, one N-type metal-oxide-semiconductor (NMOS) transistor; a capacitor device, and an inverter. The bootstrapper circuit provides an output having a voltage overshoot, as a carry propagation signal, to the gate of a pass transistor of the Manchester-carry-chain circuit.

Abstract: An augmentation circuit for use in connection with a self-bootstrap type output buffer having an n-channel pullup transistor is disclosed. The augmentation circuit includes a capacitor formed by a second n-channel transistor, connected as a capacitor, and disposed between first and second capacitor terminals. A non-overlapping signal generator is formed from a pair of NOR gates, and an inverter, to generate a pair of control signals CS1, and CS2 wherein when one of the control signals is active, the other control signal is inactive. Four n-channel transistors are provided in a switching matrix. One pair of the four n-channel transistors responds to control signal CS2 to connect the capacitor formed by the n-channel transistor across and between ground, and the output pad. In this switched configuration, a voltage level on the output pad is effectively impressed upon the capacitor, and is stored thereon.

Abstract: A buffer circuit for generating full-swing output is disclosed. The circuit includes a pull-up circuit for transferring a supply voltage to an output line in response to a first state of an input signal. A pull-down circuit is used to pull the output line down to a ground in response to a second state of the input signal. A control circuit is used to activate only one of the pull-up circuit and the pull-down circuit respectively in response to the first state and the second state of the input signal. Further, a charge-pump circuit responsive to the input signal and a clock signal is used to generate a charge-pump voltage to an input of the pull-up circuit so that the supply voltage is transferred to the output line.

Abstract: Integrated circuit output buffers and buffering methods are responsive to the input logic signal frequency to produce higher output voltages for lower frequency logic signals and lower output voltages for higher frequency logic signals. Stated differently, the output level is not raised when the data signal is provided at high speed so that power consumption and noise malfunctions may be reduced. An integrated circuit output buffer includes a driver circuit which is responsive to an input logic signal which is at a first input logic value, to drive an output terminal to a first output logic value. The driver circuit is responsive to the input logic signal at a second logic value which is logically complementary to the first input logic value, to drive the output terminal to a second output logic value at a first voltage level, where the second output logic value is logically complementary to the first output logic value.

Abstract: A logic circuit comprises an output line, a first switch having an end connected to the output line and another end connected to a power source potential, a second switch having an end connected to the output line and another end connected to a ground potential, and a switching/rectifying circuit, which has an end connected to the output line and another end connected to an intermediate power source potential, for switching/rectifying, in which said intermediate power source potential is higher than the ground potential and lower than the power source potential. With this configuration, said switching/rectifying circuit includes a third switch and a rectifier connected in series.

Abstract: Depletion mode pass gates utilized in a PLD to enable a gate voltage of Vcc to be applied for turn off, as opposed to a higher voltage required for enhancement type devices. With Vcc applied for turn off, gate oxide stress is reduced and chip reliability increased. A decoder utilizing PMOS transistors is further used to supply a negative gate voltage to enable turn off of the depletion mode pass gates. In one embodiment, to prevent pumping the power supply voltage above Vcc when supplying Vcc to gates of the pass gates, the decoder is an all PMOS device using PMOS transistors to connect Vcc to gates of the pass gates. In another embodiment both NMOS and PMOS transistors are utilized, with PMOS blocking transistors utilized to prevent a negative voltage from being applied to the NMOS transistors and causing current leakage. A negative voltage pump is further provided to supply a sufficient negative voltage.

Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply. One configuration using a switch to charge a capacitor using a first voltage supply and then providing additional voltage by a boot device and by switching in an elevated power supply to maintain an elevated voltage at the node.

Abstract: A 1.5V full-swing bootstrapped CMOS large capacitive-load driver circuit using two bootstrap capacitors to enhance the switching speed for low-voltage deep-submicron CMOS VLSI. For a supply voltage of 1.5V, the full-swing bootstrapped CMOS driver circuit shows a 2.2 times improvement in switching speed in driving a capacitive load of 10 pF as compared to the conventional CMOS driver circuit. Even for a supply voltage of 1V, this full-swing bootstrapped CMOS large capacitive-load driver circuit is still advantageous.

Abstract: When input signal IN rises to an "H" level, node N1 attain an "H" level, and output terminal OUT is charged to a level of VCC-V.sub.TH by n channel transistor. Capacitor is charged by the "H" level signal transmitted through inverters, and the charged potential is superimposed on output terminal OUT. When a short pulse is merged with input signal IN, RS flipflop is latched, and node N1 attains an "L" level, thereby discharging the voltage of the output terminal. When the output terminal attains an "L" level, NAND gate is opened and RS flipflop is reset, thereby raising the output terminal again to a boost voltage.

Abstract: A semiconductor device having at least first and second MIS transistors of a same P or N conductive type. The first MIS transistor has a first data terminal which receives a high potential Vdd, and the second MIS transistor has a first data terminal which receives a low potential GND lower than the high potential Vdd. An output terminal is coupled to second data terminals of the first and second MIS transistors. A first input terminal is connected to a gate of the first MIS transistor for supplying a non-inverted signal. A second input terminal is directly connected to a gate of one of the first and second MIS transistors for supplying an inverted signal having a reverse polarity to the non-inverted signal and which is synchronized with the non-inverted signal. An output voltage compensating circuit is connected between one of (i) the output terminal and the first input terminal and (ii) the output terminal and the second input terminal.

Abstract: A voltage boost circuit is provided which supplies a gate voltage to an insulated gate transistor. The voltage boost circuit has a voltage supply circuit, a supply line for connection to the gate of the insulated gate transistor and connected to the voltage supply circuit for precharge, a boost precharge circuit connected to the supply line and a capacitive element for boosting the voltage on the supply line. The circuit also has a facility for resetting the voltage on the supply line to its initial value after operation of the boost circuit.A memory array including such a voltage boost circuit is also provided, together with a method of boosting a gate voltage for insulating gate transistors in a memory array.

Abstract: A semiconductor device includes an increase voltage generation circuit generating an increased voltage having a higher potential than a high potential of a power-supply voltage externally supplied. In the device, an increased voltage stabilizing capacitor is connected between the increased voltage and the high potential of the power-supply voltage, and stabilizes the increased voltage.

Abstract: An integrated circuit data output buffer which may be used in an integrated circuit memory device, includes a data output circuit which is responsive to a data input signal to generate a data output signal, using a boosting data signal. A pulse generator generates a pulse in response to a control signal. A power supply sensing circuit is connected to the pulse generator, and generates a power supply voltage sensing signal in response to the pulse. A clamp circuit is connected to the power supply voltage sensing circuit and to the data output circuit, to clamp the boosting power signal after a predetermined time in response to the power supply voltage sensing signal. Accordingly, output data is buffered by generating a pulse in response to a control signal and generating a power supply voltage sensing signal in response to the pulse.

Abstract: Memory cells including at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS for transferring a potential to the word line. The word line drive circuit is controlled by a output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.

Abstract: This device for generating a reference voltage for a capacitive bootstrap circuit of an output stage can be easily integrated. The output stage comprises a driving block, a capacitive bootstrap circuit and a reference voltage generating block generating a floating reference voltage which is referred to the output voltage signal and switches in accordance thereto.