Abstract: The generation of a controlled voltage signal as a buffer control signal for an output driver provides for relatively less delay for a high output enable access for an output buffer. As the output buffer undergoes the transition from a deselected state to a selected state to generate an output signal corresponding to a high input signal, a first voltage level is generated at a node and output as the control signal for the output driver, providing for an initial pull-up transition for the output signal. A second voltage level is subsequently generated at the node and output as the control signal for the output driver, providing for a steady-state voltage level for the high output signal.

Abstract: An integrated circuit device is provided, in which optimization design can be made for a short term to suppress power consumption of the integrated circuit device and improve the maximum operation frequency. First basic cells and second basic cells are disposed in a first direction. The second basic cells are the same in circuit function other than load driving capability as the first basic cells and the same in the cell width in the first direction and relative positions of input and output terminals. The first and second basic cells preferably contain MOS transistors, respectively, whose gate widths in the direction perpendicular to the cell width are made different from each other.

Abstract: A bootstrap circuit comprising a capacitive device connected between an input line and an output line to boost a signal from the input line, a first voltage supply path being selectively driven in response to a voltage on the output line to transfer or block a supply voltage from a supply voltage source to the output line, a second voltage supply path connected in parallel to the first voltage supply path to transfer or block the supply voltage from the supply voltage source to the output line, and a controller for controlling the second voltage supply path in response to the signal from the input line. According to the present invention, the bootstrap circuit enhances a response speed of an output signal with respect to an input signal. Therefore, the bootstrap circuit can boost the input signal stably and accurately regardless of an impulse noise component.

Abstract: To compensate for leakage current resulting from parasitic resistance, an integrated circuit device includes a boosting current pump to continuously boost the input of an NMOS output circuit so long as the output circuit is providing a logic high output signal. The NMOS output circuit has an input for receiving an input signal and an output for driving at least one output signal line. An oscillation circuit provides an oscillating digital signal to the boosting current pump. The pump responds to the oscillating digital signal and to the input signal being in one of two predetermined states to provide additional current at the input of the NMOS output circuit to compensate for the leakage current.

Abstract: A voltage elevation circuit supplying additional voltage for gate switching having an elevated power supply connected to a first node of a capacitor using a transistor. The elevated power supply and booting circuit providing additional voltage for gate switching applications. One application is a MOSFET output driver application having a 3 Volt power supply where noise margin demands elevated switching voltages. One configuration using a long channel transistor to limit current sourced by the elevated power supply. An alternate configuration using a switched elevated power supply to minimize loading on the elevated power supply.

Abstract: Disclosed is an output circuit capable of improving the load driving performance of a semiconductor device. The output circuit has first and second N channel MOS transistors connected in series between a high-potential power supply and a low-potential power supply. Both transistors produce an output signal at a node therebetween in response to complementary input signals. The output circuit includes a booster circuit, connected to the first transistor. The booster circuit is supplied with power from the high-potential power supply. In response to a clock signal and an input signal for enabling the first transistor, the booster circuit produces a voltage higher than the potential level of the high-potential power supply and applies the higher voltage to the first transistor.

Abstract: Memory cells includes at least one memory cell having an n-channel MOS transistor and an n-channel MOS capacitor. A word line is connected to the memory cells. A word line drive circuit for driving the word line includes a p-channel MOS transistor for transferring a potential to the word line. The word line drive circuit is controlled by an output from a word line potential control circuit. The word line potential control circuit applies a power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are not selected, and the word line potential control circuit applies a potential higher than a potential obtained by adding a threshold voltage of the n-channel MOS transistor to the power source potential to the word line through the current path of the p-channel MOS transistor in the word line drive circuit when the memory cells are selected.

Abstract: A complementary metal oxide silicon (CMOS) data to emitter coupled logic (ECL) data translator system comprised of translator apparatus for receiving data signals from a CMOS circuit powered from a CMOS voltage power source, apparatus for powering an ECL circuit from the power source, a transmission line carrying output signals from the translator apparatus to the ECL circuit, having a predetermined characteristic, a load having the characteristic impedance connecting the transmission line to the power source, and the translator apparatus comprising apparatus for outputting a data signal on the transmission line which corresponds to the received data signals but having an amplitude compatible with the ECL circuit and referenced to a voltage of the power source.

Abstract: A word line driver circuit operable for receiving address signals from a decoder circuit and for gating these address signals to be outputted as a word line signal to one or more memory cells within a RAM. The driver circuit prevents oscillations of the outputted word line signal by not allowing any internal nodes between circuit elements to have a floating potential. This function is provided by a plurality of circuit elements arranged in a unique manner so that the internal nodes are not allowed to float.

Abstract: A line driver (10) includes a first p-channel FET (12) and two n-channel FETs (14-16), wherein one of the n-channel FETs functions as a blocking FET (16). The p-channel FET (12) is coupled to the supply voltage (26) and the blocking FET (16), while the other n-channel FET (14) is coupled to a supply return (28) and the blocking FET (16). An output (30) is provided between the n-channel FET (14) and the blocking FET (16), while inputs (20-22) are provided to the p-channel FET (12) and the n-channel FET (16). In operation, the inputs (20-22) are supplied to the FETs at a given rate such that either the p-channel or the n-channel FET is "on". To ensure a maximum output swing when the p-channel FET is on, the blocking FET (16) is sourced by a charge pump (18).

Abstract: A bootstrap circuit comprising an inverter for inverting an input signal from an input node, a delay stage for delaying the input signal from the input node for a predetermined time period, a first capacitor connected between an output terminal of the inverter and a junction node, a first NMOS transistor for transferring the input signal delayed by the delay stage to the junction node, the first NMOS transistor having a drain connected to an output terminal of the delay stage, a source connected to the junction node and a gate connected to a supply voltage source, a second capacitor connected between an output node and a ground voltage source, and a second NMOS transistor for transferring the input signal inverted by the inverter to the second capacitor connected to the output node in response to a signal charged on the first capacitor. According to the present invention, the bootstrap circuit bootstraps the input signal to a high voltage level at a high speed.

Abstract: In an output circuit for outputting an output signal having a given potential level in response to a potential level of an input signal wherein the output signal is permitted to be in high impedance state in response to a first potential level of a reset control signal having first and second potential levels, the output circuit comprises a second control circuit for outputting a second output control signal in response to the input signal at the time when the reset control signal has the second potential level and also for outputting a third output control signal at the time delayed by a first time counting from the outputting of the second output control signal, the second control circuit having a function to stop the outputting of the second output control signal in response to the change of the potential of the reset control signal from its second potential level to its first potential level and also a function to stop the outputting of the third output control signal substantially at the same time as the

Abstract: A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

Abstract: A word line driver circuit for use in a semiconductor memory device for driving a word line of the memory device to a word line driving voltage having a voltage level greater than that of a power supply voltage includes a control circuit and a word line driving circuit. The word line driving circuit includes a pull-up transistor which is connected in series between the word line driving voltage and the word line, a transfer transistor connected in series between a row decoding signal and the gate electrode of the pull-up transistor. The control circuit generates a transfer output signal which is applied to the gate electrode of the transfer transistor. In a first operating mode, the transfer output signal has a voltage level greater than the power supply voltage by an amount equal to the threshold voltage of the transfer transistor, and, in a second operating mode, the transfer output signal has a voltage level equal to the power supply voltage.

Abstract: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2V.sub.dd. Transistors in a boosting circuit are fully switched, eliminating the reduction of the boosting voltage by V.sub.tn as in the prior art. The boosting capacitors are charged by V.sub.dd, thus eliminating draft tracking problems associated with clock boosting sources and V.sub.dd. A regulator detects conduction current of a replica of a memory cell access transistor, shutting off the boosting circuit clock oscillator when the correct voltage to operate the access transistor has been reached.

Abstract: A high voltage charge pump (65) for operation at low power supply voltages includes a plurality of series connected pump stages (66), a predriver logic circuit (68), and two pump driver circuits (70 and 72). The predriver logic circuit (68) receives an external clock signal and provides internal clock signals to the pump driver circuits (70 and 72). The pump driver circuits (70 and 72) provided boosted clock signals to the series connected pump stages (66). The boosted clock signals are provided at a voltage greater than a magnitude of a power supply voltage. By using a boosted clock signal, the charge pump (65) is capable of operating in applications with low power supply voltages, such as 3.3 volts.

Abstract: An output buffer circuit comprises an input terminal for receiving an input signal, an output circuit coupled to a first node for outputting an output signal in response to a potential level appeared on the first node and a bootstrap circuit coupled between the first node and the input terminal. The bootstrap circuit comprises a delay circuit for delaying the input signal to provide a delayed input signal, a first transistor for receiving a signal inverted from the input signal, a second transistor coupled for receiving the delayed input signal and controlling a the first transistor, a third transistor connected in parallel to the second transistor, a fourth transistor coupled a gate of the third transistor for receiving the input signal and a charge circuit coupled between the delay circuit and the first node for supplying an electric charge to the first node. The charge circuit is activated in response to the potential level appeared on the first node and the delayed input signal.