Abstract: Methods and circuitry for driving a device are disclosed. An example of the circuitry includes a voltage sensing circuit coupled to an input of a transistor, the voltage sensing circuit having a first output at a node, the voltage sensing circuit comprising a capacitive voltage divider, and a current sensing circuit coupled to the input of the transistor and to the voltage sensing circuit, the current sensing circuit having a second output, the current sensing circuit comprising a resistive divider coupled to the input of the transistor.

Abstract: An output circuit includes first and second nodes, a regulator, a pre-driver, and an output driver. The regulator outputs a second voltage to the second node based on a first voltage applied to the first node. The output driver receives a signal from the pre-driver and outputs a second signal. The regulator short-circuits the first and second nodes while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.

Abstract: Provided is a switch drive circuit that drives a plurality of switches mutually connected in parallel including a charge unit allowing charge current to flow to the gate of the switch; an off switch connecting between the gate of the switch and the ground; a detection unit detecting whether charge state of the gate of the switch is in a predetermined state; and a changeover unit that changes a state of off switches when the charge units allow the charge current to flow to the gate. The changeover unit changes the state of the off switches to be ON when detection units do not detect the charge state of the gate being in the predetermined state, and to change the state of the off switches to be OFF when detection units detect the charge state of the gate being in the predetermined state.

Abstract: A level shifter causes a switch to open or close by selecting one of two stored logical values to generate a gate-drive voltage to cause a transition in the switch.

Abstract: A driving circuit for driving a power switch. The driving circuit and the power switch are collaboratively defined as an equivalent circuit. The equivalent circuit includes a first equivalent capacitor corresponding to an input capacitor of the power switch, an equivalent inductor, and a second equivalent capacitor corresponding to a parasitic parameter of at least one driving switch. In the charging procedure or the discharging of the first equivalent capacitor, a change amount of charges in the first equivalent capacitor while a voltage of the input capacitor is changed from a voltage corresponding to no inductor current to a set voltage is larger than or equal to a change amount of charges in the second equivalent capacitor while the voltage of the input capacitor is changed from the voltage corresponding to no inductor current to a steady voltage.

Abstract: A disclosed pre-driver includes multiple signal generation stages and a switching bias circuit with a first switch and a second switch. The first switch and primary inverters in each of the stages all receive the same input signal. When the input signal transitions, the first switch turns on the bias circuit to supply a bias voltage to each of the stages. However, the primary inverters do not concurrently turn on. Instead, due to the bias voltage and some additional circuitry within each stage, the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated and output by the different stages, respectively, transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the second switch turns off the switching bias circuit. Optionally, a selected one of multiple bias voltages could be used in order to tune delay and transition times.

Abstract: A signal processing system includes: a transmission channel; a common-mode signal transmitting circuit configured to output an uplink signal to the transmission channel in a common mode; a common-mode signal detecting circuit configured to detect a common-mode signal from the uplink signal transmitted by the transmission channel; a downlink reference clock signal generating circuit configured to generate a downlink reference clock signal at a second frequency with reference to the first clock edge of the common-mode signal detected by the common-mode signal detecting circuit; a downlink data generating circuit configured to generate downlink data; a differential signal transmitting circuit configured to output, as a downlink signal, the downlink data generated by the downlink data generating circuit to the transmission channel in a differential mode; and a differential signal receiving circuit configured to extract a differential signal from the downlink signal.

Abstract: According to one embodiment, an electronic circuit includes a plurality of first transistors, a control circuit, a sample hold circuit and a calculation circuit. The control circuit selectively performs a first operation and a second operation, the first operation supplying a driving control signal to a gate terminal of a semiconductor switching element using the plurality of first transistors, and the second operation supplying a pulse current for measurement to the gate terminal using part of the plurality of first transistors. The sample hold circuit samples a voltage of the gate terminal during a period in which the pulse current is supplied to the gate terminal in the second operation. The calculation circuit calculates a gate resistance of the semiconductor switching element based on the sampled voltage.

Abstract: A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

Abstract: The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28 nm complementary metal-oxide (CMOS) technology.

Abstract: According to one embodiment, a semiconductor device includes: a boost circuit configured to apply a first voltage to a gate terminal; a first switching element, a first resistor, and a second resistor that are coupled in parallel between the gate terminal and a source terminal; a second switching element coupled in series with the second resistor between the gate terminal and the source terminal; a switching element control circuit configured to switch, in response to a change of a voltage from the first voltage applied from the boost circuit to the gate terminal to being indeterminate, the first switching element to on state after switching the second switching element to on state. A resistance value of the second resistor is smaller than a resistance value of the first resistor.

Abstract: An organic light emitting display device may include a display panel, a power supply, and a display driver. The display panel may comprise a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the scan lines and to the data lines. The power supply may supply a first pixel voltage and a second pixel voltage to the pixels. The display driver may control the display panel. The display panel may display a first image in a first frame frequency during a first driving mode, and display a second image in a second frame frequency that is lower than the first frame frequency during a second driving mode, according to a control by the display driver.

Abstract: An open drain driver circuit includes an output terminal, an input terminal, a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal coupled to the output terminal, and a second terminal coupled to a reference voltage source. The second transistor includes a first terminal coupled to a third terminal of the first transistor, a second terminal coupled to a power supply rail, and a third terminal coupled to the reference voltage source. The third transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the reference voltage source, and a third terminal coupled to the third terminal of the first transistor.

Abstract: A power module which includes a power semiconductor chip that includes an IGBT and a freewheeling diode formed in the same chip, and the power module includes a drive circuit that is connected to the power semiconductor chip and drives the IGBT on/off. The power module is configured by packaging the power semiconductor chip and the drive circuit, and is characterized by further including a capacitor and a switch element disposed in series between the emitter of the IGBT and the ground of the drive circuit. The switch element connects the emitter and the ground in the case where the drive circuit has the IGBT perform a turn off switching operation.

Abstract: The invention relates to a method for operating a current converter, in particular of an electric machine, in which, for the or for each semiconductor switch of the current converter, a control signal (P?) for setting a switch-off speed (Anew) is generated, wherein an electric intermediate circuit voltage (Udc) of an intermediate circuit is measured and compared to a voltage threshold value (Uthresh), wherein an operating temperature (TB) of the respective semiconductor switch is measured and compared to a temperature threshold value (Tthresh), wherein a load current (Ic) switched by means of the respective semiconductor switch is measured and compared to a current threshold value (Ithresh), and wherein the control signal (P?) for setting the switch-off speed (Anew) is generated on the basis of the comparisons.

Abstract: A switching element driving device includes a main on switch that is connected to gates of a first and second IGBTs and that, when brought into a conductive state, turns on the first and second IGBTs, diodes each disposed between the main on switch and one of the gates of the first and second IGBTs, the diodes having a forward direction from the main on switch to the gates of the first and second IGBTs, an on sub-switch that is connected to the gate of the second IGBT and that, when brought into the conductive state, turns on the second IGBT, and a control circuit that controls the conductive state and a non-conductive state of the main on switch and the on sub-switch.

Abstract: A measurement system includes a signal bus, an electronic control unit, and an emulated sensor. The electronic control unit is coupled to the signal bus. The sensor with emulated line adaptation is also coupled to the signal bus. The emulated sensor is configured to adapt current consumption according to a selected impedance and a selected frequency range.

Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.

Abstract: A level translator translates signals between first and second voltage domains. An output buffer thereof includes a plurality of PFETs coupled in parallel between a second domain's output supply voltage and an output signal and a plurality of NFETs coupled in parallel between the output signal and the ground rail. Each gate of the plurality of PFETs is coupled to a respective first resistor; the first resistors are coupled in series and receive a first gate control signal. Each gate of the plurality of NFETs is coupled to a respective second resistor; the second resistors are coupled in series and receive a second gate control signal. A first booster NFET is coupled between the output supply voltage and the output signal and a second booster NFET is coupled between the output signal and the ground rail. The booster NFETs receive control signals that operate in the first voltage domain.

Abstract: Power electronics circuitry includes a pair of parallel switching elements. Each of the switching elements includes two power terminals, two control terminals, and an additional terminal. Corresponding ones of the two power terminals from each of the pair are connected via respective first and second power paths. Corresponding ones of the two control terminals from each of the pair are connected via respective first and second control paths. The additional terminals are connected via an additional path. The circuitry also includes a gate driver tapping the first and second control paths, and a magnet surrounding the additional terminals to couple inductance of the additional path.

Abstract: Some aspects of the disclosure provide for a circuit. In an example, the circuit includes an amplifier, a first transistor network, a second transistor network, a first resistor, a second resistor, and a third resistor. The amplifier has first and second inputs and first, second, third, and fourth outputs. The first transistor network is coupled to the first output of the amplifier and the second output of the amplifier. The second transistor network is coupled to the third output of the amplifier and the fourth output of the amplifier. The first resistor is coupled between the first transistor network and the second transistor network. The second resistor is coupled between the first transistor network and the first input of the amplifier. The third resistor is coupled between the second transistor network and the second input of the amplifier.

Abstract: Provided is a constant current drive circuit that can improve accuracy of a stop timing of quick charge and prevent an overshoot, an insufficient quick charge, and the like from occurring. The constant current drive circuit includes a resistor R5 connected between the output side of the gm amplifier 6 and the input side of the transistor M1. The comparator 9 serving as a charge stopping circuit includes a voltage Vof, and stops charging by the quick charge circuit 8 based on a comparison result of the voltage Vof and the voltage Vs2 generated in the resistor R5.

Abstract: A turn-off circuit for a semiconductor switch includes an element having a variable resistance coupled to a control input of the semiconductor switch, a circuit for generating a control-input reference signal, and a control circuit coupled to adjust a resistance of the element having a variable resistance in response to the control-input reference signal in a closed control loop in order to turn off the semiconductor switch.

Abstract: A controller circuit for controlling an insulated-gate bipolar transistor (IGBT) is configured to, in response to an IGBT turn off switching event, switch out a first switching element to prevent a pull-up signal from flowing to a gate of the IGBT, switch in a second switching element to create a channel to permit a first pull-down signal to flow to the gate of the IGBT, and switch in a third switching element to create a channel to permit a second pull-down signal to flow to the gate of the IGBT. In response to determining a collector to emitter voltage at the IGBT does not satisfy a threshold, the controller circuit is configured to switch out the third switching element to prevent the second pull-down signal from flowing to the gate of the IGBT.

Abstract: A control device for driving a bipolar switchable power semiconductor component is designed to apply an electrical voltage to a gate terminal of the power semiconductor component and to reduce the electrical voltage for turning off the power semiconductor component from a first voltage value to a second voltage value. The control device is designed, for turning off the power semiconductor component, firstly to reduce the electrical voltage from the first voltage value to a desaturation value and then to reduce the electrical voltage from the desaturation value to the second voltage value. The desaturation value is greater than a pinch-off voltage of the power semiconductor component.

Abstract: The present document describes a level-shifter circuit and method to transmit data from a high-voltage domain to a low-voltage domain. The level-shifter circuit has a first current path with a first current control unit to set a first current based on a high-voltage data signal in the high-voltage domain; and a second current path with a second current control unit to set a second current based on the high-voltage data signal. Furthermore, the circuit has an isolation unit to transfer the first current and the second current from the high-voltage domain to the low-voltage domain; and a current comparator unit to compare the first current with the second current to provide a low-voltage data signal in the low-voltage domain, which corresponds to the high-voltage data signal.

Abstract: A global coarse baseline correction charge injection circuit comprises: an output capacitor, a slew rate control circuit, a current generator, a first current mirror, and a second current mirror. The output capacitor is configured to store a global coarse baseline correction charge. The slew rate control circuit is configured to receive a modulated voltage, a positive input current, and a negative input current as inputs, and provide a proportional-to-supply-voltage slew-rate controlled voltage as an output voltage to charge the output capacitor. The current generator is configured to receive a supply voltage as an input and provide a proportional-to-supply-voltage (PTSV) current as an output. The first current mirror is configured to mirror the PTSV current to the slew rate control circuit as the positive input current. The second current mirror is configured to mirror the PTSV current to the slew rate control circuit as the negative input current.

Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.

Abstract: A device includes a failsafe circuit having a supply node configured to couple to a supply voltage source, a pad node configured to couple to an input/output (I/O) pin, and a bulk node configured to couple to a bulk of a transistor coupled to the I/O pin. The failsafe circuit is configured to assert a failsafe indicator signal when the supply node voltage falls below the pad node voltage by a threshold voltage, and couple the higher of the supply node voltage and the pad node voltage to the bulk node. The device also includes a pull-down stack coupled to the failsafe circuit and to a ground node, and a sub-circuit configured to turn off the pull-down stack in response to the supply node discharging to the threshold voltage below the pad node voltage.

Abstract: A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.

Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Abstract: In circuitry to capture differences between magnitudes of first and second comparator input signals in capture operations defined by a clock signal, first and second nodes are connectable to a tail node receiving a cock-signal-independent bias current along first and second paths. During each capture operation, switching circuitry controls connections between the tall node and the first and second nodes based on the input signals to divide the bias current between the first and second paths depending on the input signal magnitude difference. The switching circuitry comprises first and second transistors arranged such that conductivity of connections between the tail node and the first and second nodes Is controlled by the magnitudes of the input signals, and third and fourth non-clocked transistors controlled by a clock-signal independent gate bias signal.

Abstract: A strobe signal generation circuit includes a trigger circuit configured to generate a pull-up signal and a pull-down signal according to a clock signal; a first main driver configured to generate a differential data strobe signal in response to receiving the pull-up signal and the pull-down signal; and a second main driver configured to generate an other differential data strobe signal in response to receiving the pull-up signal and the pull-down signal from among the at least one pull-down signal through opposite terminals than the first main driver received the pull-up signal and the pull-down signal.

Abstract: An electronic circuit is provided, including, on one same substrate, an inverter branch formed by high side and low side transistors, and the drivers of the high side and the low side transistors. The drivers include logic gates configured to receive one same PWM input signal and to generate two alternated command signals sent to the high side and the low side transistors. An inverter system is also provided, including the electronic circuit and laser optocouplers configured to electrically insulate the electronic circuit of a controller delivering a pulse width modulation (PWM) input signal and a main supply electrically supplying the drivers.

Abstract: Radiofrequency energy that is captured by a radiofrequency power harvester is stored in a storage capacitance. One or more user circuits are supplied with energy stored in the storage capacitance. The harvester operates in alternated charge and burst phases with captured radiofrequency energy stored in the storage capacitance in the charge phases and supplied to the user circuits in the burst phases to perform user circuit tasks. In response to detection of completion of the user circuit tasks in a burst phase, the harvester causes operation to shift to the next charge phase.

Abstract: Disclosed in present invention is a clock driving circuit resistant to single-event transient. The clock driving circuit resistant to single-event transient consists of two kinds of inverters: double-input double-output (DIDO) inverter and double-input single-output (DISO) inverter, the specific number of the two kinds of inverters used, and the connection way thereof are determined by the complexity of a designed circuit and a clock design method used by the designed circuit. The DIDO inverter and DISO inverter both comprise two PMOS transistors and two NMOS transistors. In a clock distribution network based on double-input double-output and double-input single-output clock inverters, the probability that single-event transient pulses generated on the DIDO inverter are propagated to clock leaf nodes is zero.

Abstract: A differential charge pump circuit for use in a phase-locked loop (PLL) circuit is disclosed. The circuit includes a reference current, two sense amplifiers, a common mode control amplifier, and an h-bridge circuit. The h-bridge circuit is coupled to the reference current and the common mode control amplifier. The reference current drives a first portion of the h-bridge circuit and the common mode control amplifier controls a second portion of the h-bridge circuit. The h-bridge circuit also includes first and second nodes. The circuit controls a voltage at the first node so that it is substantially equal to a voltage at the second node for a plurality of voltages at the second node.

Abstract: A system is connected to a single-wire communication line to perform bidirectional communication between a master side and a slave side, and an input clock-side transistor connected between a GND level and the communication line performs switching according to an input clock. A first transistor is connected between a first potential and the communication line, a second transistor has one end connected to a second potential, and a master-side resistor is connected between the other end of the second transistor and the other end of a third transistor. A fourth transistor is connected between the communication line and a third potential equal to or higher than the first potential, and a slave-side resistor is connected between the communication line and the GND level.

Abstract: In recent years, it has been desired to further shorten the dead time. Provided is a driving device that drives on/off a main switching element to which a free wheeling diode is anti-parallel connected, wherein the driving device includes a determination unit configured to output a determination signal indicating whether free wheeling current is flowing from a source terminal to a drain terminal of the main switching element; and a drive control unit configured to reduce a switching speed when the main switching element is driven from an on-state to an off-state on condition that the determination signal indicating that the free wheeling current is flowing is output.

Abstract: A bi-state driver circuit for switching an output terminal between a first predetermined voltage level and a high impedance state, which involves a first string of transistors connected between the output terminal and the first predetermined voltage level at least a first transistor arranged closer to the first predetermined voltage level, a second transistor arranged closer to the output terminal, a voltage divider circuit connected between the output terminal and a voltage level of a control signal attaining voltage levels between the first predetermined voltage level and a second predetermined voltage level, including at least one intermediate node having an intermediate voltage level between a voltage level of the output terminal and the voltage level of the control signal, and a second string of transistors connected between the intermediate node of the voltage divider circuit and the second predetermined voltage level, and including at least a third transistor.

Abstract: The present disclosure provides a series-connected SiC MOSFET drive circuit based on multi-winding transformer coupling. The drive circuit is mainly composed of a transformer, an energy storage capacitor and a push-pull circuit. The transformer plays a role of constraining a relationship between gate-source voltages of series-connected SiC MOSFETs to ensure that a drive voltage of each SiC MOSET in series is synchronously increased and decreased, and to prevent the problem of a dynamic voltage imbalance at moments of conduction and cutoff due to the desynchrony of the drive voltages. Both the energy storage capacitor and the push-pull structure are used to ensure that the SiC MOSFETs have sufficient drive currents at the moment of conduction to achieve fast conduction of the SiC MOSFETs. Meanwhile, a discharge loop is constructed for the gate-source voltages at the moment of cutoff to ensure that the drive voltages drop in a short period of time.

Abstract: An integrated circuit and a transmission circuit thereof are provided. The transmission circuit includes an input buffer and a voltage holding circuit. The voltage holding circuit has a first end coupled to the input end of the input buffer, and a second end coupled to a reference voltage end. The voltage holding circuit includes a switch and a diode apparatus coupled in series between the first end and the second end of the voltage holding circuit. The switch is configured to receive a mode signal, and is turned on or cut off according to the mode signal.

Abstract: A diode according to the present invention includes a semiconductor layer of a first conductivity type having an impurity concentration of 1×1016 cm?3 to 2.4×1017 cm?3, a Zener diode region of a second conductivity type formed selectively in the semiconductor layer and forming a pn junction with the semiconductor layer, a Schottky metal disposed on the semiconductor layer, forming a Schottky junction with the semiconductor layer, and having a work function of 3 eV to 6 eV, and a JBS (junction barrier Schottky) structure including a plurality of second conductivity type regions formed selectively in the Schottky junction region of the semiconductor layer.

Abstract: A switching-mode power amplifier includes a driver circuit having an input for receiving a radio frequency (RF) signal, an output for outputting a digital output signal, and a bias port for receiving a bias signal, and a bias circuit having a first input coupled to the output of the driver circuit for receiving the digital output signal, a second input coupled to the input of the driver circuit for receiving the RF signal, and an output coupled to the bias port of the driver circuit for providing the bias signal to the driver circuit.

Abstract: A driving circuit that drives an insulated-gate semiconductor device. The driving circuit includes a constant-current generation circuit and a discharge circuit. The constant-current generation circuit has first and second transistors forming a current mirror, and a constant-current circuit connected to the drain of the first transistor for providing a constant current to the current mirror. The discharge circuit is connected to a gate of the insulated-gate semiconductor device and the drain of the second transistor, and includes a third transistor. The discharge circuit is configured to draw out a current injected into the gate of the insulated-gate semiconductor device by inputting a driving signal to the gate of the third transistor, and correct a metal-oxide-semiconductor (MOS) size of the third transistor so as to adjust an amount of a current that flows via the drain and the source of the third transistor to ground.

Abstract: The drive circuit for driving voltage controlled switches includes: charge path connected to gate of the switch, through which gate charge current flows to turn the switch ON; discharge path connected to the gate and output terminal of the switch, through which gate discharge current flows to turn the switch OFF; and at least either, a charging side element disposed on charging side loop path having the gate, a part of the charge path and the output terminal, restricting current flow to be in one direction and not disturbing current flow of charge current; or a discharging side element disposed on a discharging side loop path having the gate, a part of the discharge path and the output terminal, restricting a current flow to be in one direction and not disturbing a current flow of discharge current.

Abstract: Some demonstrative embodiments include an apparatus including a low-voltage detector to detect whether a voltage difference between a first voltage of a first voltage domain and a second voltage of the first voltage domain is lower than a predefined voltage.

Abstract: The invention provides a shift register unit, including a pull-up node, a pull-down node, a low-level signal terminal, a second clock signal terminal and a pull-down module, the second clock signal terminal supplies a high-level signal during an input sub-period and a pull-down sub-period, the pull-down module is connected to the pull-up node, the pull-down node, an output terminal of the shift register unit and the low-level signal terminal, the shift register unit further includes a discharging module, which is configured to make the pull-down node and the low-level signal terminal be connected in a conducting path during the input sub-period, and both the pull-up node and the output terminal of the shift register unit are connected with the low-level signal terminal in conducting paths during the input sub-period and the pull-down sub-period.

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.

Abstract: Disclosed herein is an apparatus that includes an output signal line, and first and second tristate buffer circuits each having an output node connected to the output signal line in common. The output signal line includes a first section having first and second connection points, a second section having third and fourth connection points, a third section connected between the first and third connection points, and a fourth section connected between second and fourth connection points. At least a part of the first section of the output signal line is located on the first tristate buffer circuit, and at least a part of the second section of the output signal line is located on the second tristate buffer circuit.