Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: Various implementations described herein are directed to a device having logic circuitry with multiple inversion stages. One or more of the multiple inversion stages may be configured to operate as first inversion logic with a first number of transistors. One or more of the multiple inversion stages may be configured to operate as second inversion logic with a second number of transistors that is greater than the first number of transistors.

Abstract: A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

Abstract: A pulse signal sending circuit that outputs pulse signals from an output terminal includes: an output transistor; an inverter circuit; and a delay circuit. The output transistor includes a drain terminal connected to the output terminal. The inverter circuit is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor. The delay circuit receives a pulse signal as an input and delays rising or falling of the input pulse signal. The pulse signal delayed by the delay circuit is input to the inverter circuit.

Abstract: A gate-driver-on-array type display panel having a display area includes a plurality of pixel units and a GOA circuit, wherein the pixel units and the GOA circuit are disposed in the display area. The GOA unit set and the GOA trace set are respectively disposed in the pixel units that are in two adjacent rows, and the GOA trace set is electrically connected to two ends of the GOA unit set through a plurality of first signal connecting traces.

Abstract: A circuit arrangement is provided, having a first circuit configured to receive an input signal, and a second circuit configured to provide an output signal, wherein the first circuit includes a first pull-up network having a first transistor of a first conductivity type and a second transistor of a second conductivity type electrically coupled to each other, and a first pull-down network having a first transistor of the first conductivity type and a second transistor of the second conductivity type electrically coupled to each other, wherein the second circuit includes a second pull-up network having a first transistor of the first conductivity type, and a second pull-down network having a second transistor of the second conductivity type, wherein the first pull-up network and the second pull-down network are electrically coupled to each other, and wherein the first pull-down network and the second pull-up network are electrically coupled to each other.

Abstract: A current-mode Schmitt Trigger includes a plurality of current output stages connected to a common supply voltage that powers the current-mode Schmitt Trigger, a main input on one of the current output stages that receives an input current, and a non-inverting output on a different one of the current output stages that is shorted to the main input to establish a positive closed-loop feedback and supplies a non-inverting output current as the input current. The current-mode Schmitt Trigger includes only active components.

Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.

Abstract: A power management integrated circuit comprises a modular interleaved clock generator comprising a plurality of interconnected modular elements, each element constructed to generate and output a clock signal, and each one comprising: a phase port high input; a phase port low input; a clock input; and a bypass switch coupled between the phase port high input and the phase port low input, wherein in response to the bypass switch of at least one of the plurality of elements in a closed state, the phase port high inputs or the phase port low inputs of the remaining elements absent the at least one interleaving controller having the bypass switch in the closed state each receives a voltage that interleaves the clock signals output from the remaining active elements to have an interleaving arrangement that includes equal phase delays.

Abstract: This invention introduces the negative feedback into the gate drive. It proposes a negative feedback active gate drive (NFAGD) for silicon carbide (SiC) and gallium nitride (GaN) semiconductor devices to fully utilize their potential of high switching-speed capability in a phase-leg configuration. An auxiliary P-channel MOSFET is introduced to construct a negative feedback control mechanism. Due to the negative feedback mechanism, the proposed drive can automatically attenuate the disturbance from the complementary device of the phase-leg. The negative feedback active gate drive (NFAGD) has a simple structure and easy to be realized using a push-pull drive circuit, a drive resistor, an auxiliary MOSFET and an auxiliary capacitor, without involving any additional logical circuits.

Abstract: Electronic circuits are disclosed. One electronic circuit includes: a transistor device having a load path and a drive input; a first drive circuit configured to receive a supply voltage and generate a drive signal for the transistor device based on the supply voltage; and a biasing circuit connected in parallel with the load path of the transistor device. The biasing circuit includes a bias voltage circuit configured to receive the supply voltage and generate a bias voltage higher than the supply voltage based on the supply voltage.

Abstract: A transmitter includes a driving circuitry configured to drive a channel coupled to an output node by controlling an output impedance of a pull-up path, an output impedance of a pull-down path, or both, according to one or more multi-bit data signals, a pull-up control signal, and a pull-down control signal; a driving control circuit configured to generate the pull-up control signal and the pull-down control signal according to one or more calibration signals and the multi-bit data signals or according to the calibration signals and one or more duplicate multi-bit data signals, the duplicate multi-bit data signals duplicating the multi-bit data signals; and a look-up table storing values of the calibration signals.

Abstract: The present invention provides a Miller clamp drive circuit, including a drive chip which includes an output terminal configured to output a driving signal, a clamp terminal, a power terminal and a controllable switch connected between the clamp terminal and the power terminal; a drive resistor, one terminal of which is connected to the output terminal of the drive chip and the other terminal of which is used to connect to a control electrode of a power switching transistor; and a Miller clamp circuit including a first voltage divider circuit which is connected between the other terminal of the drive resistor and the clamp terminal and configured to have a preset voltage drop, and a second voltage divider circuit connected between the clamp terminal and the power terminal. The Miller clamp drive circuit of the present invention increases the Miller clamp voltage and decreases the tailing time of the power switching transistor.

Abstract: A memory device includes a communication circuit configured to communicate a first signal and a second signal; and a selection mechanism coupled to the communication circuit and configured to select between operating the communication circuit the first signal and the second signal (1) independent signals for separate memory operations or (2) a complementary set for a memory operation.

Abstract: A method for operating an electrical circuit including at least one half-bridge formed from two transistors wherein the electrical circuit is switched over between a first switching state, in which the first transistor of the half-bridge is switched to conductive by a first voltage value of a first control voltage and the second transistor of the half-bridge is switched to blocking by a second voltage value of a second control voltage, and a second switching state, in which the first transistor is switched to blocking by a second voltage value of the first control voltage and the second transistor is switched to conductive by a first voltage value of the second control voltage, wherein a dead time state, in which both transistors are switched to blocking, is assumed chronologically between the first switching state and the second switching state.

Abstract: A low noise amplifier circuit includes an input stage circuit, a first output stage circuit, and a second output stage circuit. The input stage circuit is configured to receive an input signal and to generate a bias signal. The first output stage circuit corresponding to a first wireless communication and is configured to be biased according to the bias signal and a first control signal, in order to generate a first output signal, in which the first control signal is for setting a first gain of the first output stage circuit. The second output stage circuit corresponding to a second wireless communication and is configured to be biased according to the bias signal and a second control signal, in order to generate a second output signal, in which the second control signal is for setting a second gain of the second output stage circuit.

Abstract: An improved gate driver using a microcontroller (uC), a voltage selector (VS), an adjustable voltage regulator (AVR), and an auxiliary current sinking circuit (ACSC) to actively provide selectable drive signals either higher, lower or equal to the basic on voltage and off voltage drive signals for a selected semiconductor device thereby providing an active voltage-mode gate driver for actively speeding up or slowing both the on time and off time transitions of a semiconductor.

Abstract: In the actuator, the viscoelastic members are arranged at positions at which the support body and the movable body face each other in the first direction, and the magnetic drive circuit drives the movable body in the second direction which crosses the first direction. The viscoelastic members connect the movable body and the support body together while having the thickness direction thereof in the first direction and extending in the second direction. Therefore, resonance caused when the movable body is vibrated can be restricted. Reproducibility of vibration acceleration corresponding to the input signals can be improved by utilizing the spring elements of the viscoelastic members in the shearing direction, thus enabling the actuator to vibrate with delicate nuances. Further, the viscoelastic members can be prevented from being pressed in the thickness direction and greatly deformed, therefore, preventing the gap between the movable body and the support body from greatly varying.

Abstract: The present invention relates to an image sensor and to an imaging system comprising the same. The present invention particularly relates to X-ray image sensors and imaging systems. The image sensor according to the invention comprises a pixel array that includes a plurality of active pixels arranged in a matrix of rows and columns, and a plurality of column lines to which outputs of pixels in the same column are coupled for the purpose of outputting pixel signals. The image sensor further comprises readout circuitry that includes a plurality of readout units, each readout unit being configured for reading out a respective column line through an input node of the readout unit. The image sensor is characterized in that the image sensor further comprises capacitive units, such as capacitors, for capacitively coupling each input node to its corresponding column line.

Abstract: A DAC current steering circuit includes first and second transistors, respectively coupled to first and second outputs via first and second nodes at their drains, and source coupled to each other and to ground. A gate of the first transistor is coupled to a data input (D), and a gate of the second transistor coupled to a complement of the data input (DB). The circuit further includes first and second bleeder transistors, whose drains are respectively coupled to the first and second nodes, and whose sources are coupled together at a third node, the third node coupled to ground, and first and second bleeder switching transistors, whose drains and sources are each coupled to the third node, a gate of the first bleeder switching transistor coupled to a switching input (S) and a gate of the second bleeder switching transistor coupled to a complement of the switching input (SB).

Abstract: A single supply RF switch driver. The single supply RF switch driver includes an inverter, where a first resistor has been integrated within the inverter, and the resistor is connected to an RF switch. In one aspect, the integration of the first resistor within the inverter allows for the elimination of a negative power supply for the inverter, while maximizing the isolation achieved in the RF switch. In another aspect, the driver is a configured to have a second resistor integrated within the inverter. A third resistor is connected between the gate of the RF switch and the inverter. In an alternate aspect, the driver operates from a positive power supply and a negative power supply, thus increasing the isolation in the RF switch even further.

Abstract: A gate driver circuit comprises a gate-driver assembly, a transformer, first and second circuit voltage outputs, first and second switching devices, and a controller. The gate-driver assembly comprises a first and second voltage inputs and a first and second voltage outputs coupled to a primary winding of the transformer. The first and second switching devices are coupled to the secondary winding and respectively coupled to the first and second circuit voltage outputs. The controller is configured to cause the first circuit voltage output to supply a positive output voltage by supplying a higher first input voltage to the first voltage input than to the second voltage input and is also configured to cause the first circuit voltage output to supply a negative output voltage by supplying a higher second input voltage to the second voltage input than to the first voltage input.

Abstract: A circuit. In some embodiments, the circuit includes: a drive circuit having an output and including: a pre-emphasis circuit; and an output stage connected to an output of the pre-emphasis circuit. The pre-emphasis circuit may be configured to generate, during a first interval of time, a pre-emphasized signal. The output stage may be configured to produce, at the output of the drive circuit, a constant signal based on the pre-emphasized signal during the first interval of time, and to disconnect the pre-emphasis circuit from the output of the drive circuit during a second interval of time, the second interval of time beginning at the end of the first interval of time.

Abstract: In a power supply system, a high-side (HS) insulated-gate bipolar transistor (IGBT) has a first collector, a first gate, and a first emitter. A low-side (LS) IGBT has a second collector coupled to the first emitter, a second gate, and a second emitter. A gate drive circuit is coupled to the first gate of the HS IGBT and the second gate of the LS IGBT. A control circuit is coupled to the gate drive circuit. The control circuit is configured to control the gate drive circuit for biasing the HS IGBT to a HS saturation, and determine a HS degradation of the HS IGBT based on a HS digitized gate voltage of the HS IGBT in the HS saturation.

Abstract: A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

Abstract: In certain aspects, a driver includes a pull-down transistor coupled between an output and a ground, a pull-up n-type field effect transistor (NFET) coupled between a first voltage rail and the output, and a pull-up p-type field effect transistor (PFET) coupled between the first voltage rail and the output. The driver also includes a first switch coupled between a gate of the pull-up NFET and the ground, and a second switch coupled between a gate of the pull-up PFET and a second voltage rail.

Abstract: Provided are a shift register and display apparatus including the same. A shift register includes a plurality of stages, each of the plurality of stages including: a node controller configured to: periodically discharge a first node voltage generated from a first driving voltage during a first voltage level of a clock signal, and control a second node voltage opposite to the first node voltage based on a second driving voltage, and an output part configured to receive the clock signal to output an output signal based on the first node voltage.

Abstract: A signal receiver circuit includes a first amplification circuit and an offset compensation circuit. The first amplification circuit generates a first amplified signal and a second amplified signal by amplifying an input signal and a reference voltage. The offset compensation circuit adjusts voltage levels of the first and second amplified signals based on a DC level of the input signal and a voltage level of the reference voltage.

Abstract: A transmission device according to the disclosure includes a driver section that is able to transmit a data signal by using three or more predetermined number of voltage states and set voltages in each of the voltage states; and a control section that sets an emphasis voltage that is based on a transition among the predetermined number of the voltage states, and thereby causes the driver section to perform emphasis.

Abstract: A device includes: a capacitor having first and second terminals; a first switch; a second switch coupled to the second terminal; a first multiplier coupled between the first and second terminals; a second multiplier coupled between the first and second terminals; and a buffer having an input terminal and an output terminal. The first switch is coupled between the output terminal and the first terminal.

Abstract: A circuit to control a switching characteristic of a switching device. The circuit includes a driver circuit comprising an output port, where the driver circuit is configured to generate, at the output port, a control signal to actuate the switching device within a first time period. The control signal comprising at least one electrical pulse, where a pulse width of the at least one electrical pulse being shorter than the first time period. The circuit also includes a coupling circuit that is configured to use the control signal to actuate the switching device to establish a target switching characteristic of the switching device according to a modulation of the at least one electrical pulse. The control circuit is also configured to provide a greater impedance to the control signal than an impedance of the output terminal of the driver circuit.

Abstract: Magnetic sensing technology can be used to detect changes, or disturbances (e.g., changes in magnetic field strength), in magnetic fields and can be used to measure the precise location/positioning of an electronic device in proximity to a magnetic source. In order to avoid interference by earth's static magnetic field, a modulated magnetic field can be used for magnetic based proximity sensing. Received modulated magnetic field signals can be demodulated to determine a received magnetic field strength. A drive current of a magnetic transmitter coil can be varied to maintain the detected magnetic field strength at a target value or within a desirable range. The drive current can also be varied to remain below a burnout current level that can cause damage to the transmitter coil.

Abstract: A memory device may include a first data line driver circuit that generates a first reference voltage set based on a first code and a second code associated with a first data line, and determines bit values of the first input data received through the first data line, based on the first reference voltage set. A second data line driver circuit may similarly generate a second reference voltage set. The reference voltages may have levels based on a decision feedback equalization (DFE) technique to reduce bit errors otherwise caused by inter symbol interference.

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

Abstract: A Schmitt trigger voltage comparator circuit is provided including a voltage reference input, a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to a signal input for converting the signal input to a input current and the voltage reference input to a reference current, a current mirror having an input connected to the output of the first voltage controlled current source configured and arranged to invert the direction of the first current and an output of the current mirror connected to the output of the second voltage controlled current source, and a sequence controller for generating digital signals to control a first plurality of switches and a second plurality of switches. The first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.

Abstract: A signal buffer is disclosed. The signal buffer may include one or more bias signal generators to bias one or more transistors. The bias signal generators may generate power supply compensated or ground compensated bias signals. The bias signal generators may include a capacitor to provide a high frequency signal path.

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: A circuit for regenerative gate charging includes an inductor coupled to a gate of a FET. An output control circuit is coupled to a timing control circuit and a bridged inductor driver, which is coupled to the inductor. A sense circuit is coupled to the gate and to the timing control circuit, which receives a control signal, generates output control signals in accordance with a first switch timing profile, and transmits the output control signals to the output control circuit. In accordance with the first switch timing profile, the output control circuit holds switches of the bridged inductor driver in an ON state for a first period and holds all of the switches in an OFF state for a second period. Gate voltages are sampled during the second period and after the first period. The timing control circuit generates a second switch timing profile using the sampled voltages.

Abstract: A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter may filter the control signal. The second flipped voltage follower may generate the output voltage based on the filtered bias voltage and the filtered control signal.

Abstract: A driving circuit includes a plurality of differential amplifier circuits each electrically connected to a power supply line. Each differential amplifier circuit includes a differential pair circuit and a series resistance circuit. In the differential pair circuit, a first transistor and a second transistor are electrically connected to the power supply line through a first load resistor and a second load resistor, respectively. A center node is electrically connected between the first transistor and the second transistor. Each differential amplifier circuit generates a differential output signal in accordance with a differential incoming signal. The series resistance circuit includes a resistor and a line element. The line element includes a signal line which extends straight with a distance between the signal line and a ground line extending in parallel thereto. The resistor and the line element are connected in series between the center node and a static potential line.

Abstract: A sensor arrangement has a current mirror structure that is configured to provide respective base currents at each of a plurality of output current paths based on an input current. For each of the output current paths, a respective adjustment current source is provided that is digitally controllable and is connected to the respective output current path for adjusting the base current of said output current path. For each of the output current paths, a current biased sensor element is coupled in said output current path. The sensor arrangement further has a selection element for selectively connecting one of the output current paths to an evaluation block based on a selection signal. The evaluation block is configured to generate a sensing value corresponding to a resulting current in the connected output current path, to compare the sensing value with an average value, and to update the average value based on the sensing value.

Abstract: A semiconductor device includes a voltage input circuit node and a ground voltage node. A first transistor is coupled between the voltage input circuit node and the ground voltage node. A triggering circuit is coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor. The triggering circuit includes a trigger diode. An output of the triggering circuit is coupled to a control terminal of the first transistor. A load is powered by coupling the load between the voltage input circuit node and the ground voltage node.

Abstract: A ground overcurrent control system includes ground circuit with a first section and a second section. The first section is electrically connected to a ground member of an electrical connector and the second section is electrically connected to a ground reference. A switch element is positioned between the first section of the ground circuit and the second section of the ground circuit. A controller is configured to determine the current within the ground circuit while current is passing through the switch element and, upon the current exceeding a current threshold, the switch element is modified to an open condition. Upon determining that the voltage between the first section of the ground circuit and the ground reference is less than a voltage threshold, a command is generated to modify the switch element back to a closed condition.

Abstract: The disclosed bandgap circuit is configured to provide a temperature stable reference current and/or voltage that is also adjustable. The stability can be facilitated by an improved matching of current mirrors provided by a source degeneration topology. The source degeneration can reduce random mismatches without requiring increased size or complexity of the current mirrors and can facilitate operation of the current mirrors in a weak inversion condition, in which random mismatches may be most severe. Further, the source degeneration may be adjusted to adjust a level and/or a temperature coefficient of the generated reference current and/or voltage.

Abstract: A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.

Abstract: According to one embodiment, a memory device includes: a first and a second interconnects; a memory cell including a variable resistive element, the memory cell between the first and second interconnects; and a write circuit including a current source circuit and a voltage source circuit, the write circuit writing data to the memory cell by using a write pulse. The write circuit supplies the write pulse to the memory cell by using the current source circuit in a first period from a first time of a start of supply of the write pulse to a second time, and supplies the write pulse to the memory cell by using the voltage source circuit in a second period from a third time to a fourth time of an end of the supply of the write pulse.

Abstract: In an embodiment, a digital output driver circuit comprises an output stage having first and second transistors. A drive stage is configured to drive control terminals of the first and second transistors and comprising switching circuitry and current generator circuitry. In a first configuration, the driver circuit is configured to connect a control terminal of the second transistor to the reference node to turn off the second transistor; and connect a first capacitance to the current generator circuitry and to a control terminal of the first transistor to turn on the first transistor. In a second configuration, the driver circuit is configured to turn off the first transistor and connect the control terminal of the second transistor to the current generator circuitry and to the second capacitance to turn on the second transistor.

Abstract: A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

Abstract: An oscillation reduction unit for a bus system. The oscillation reduction unit has two transistors, which are situated anti-serially between a first bus wire of a bus of the bus system and a second bus wire of the bus, in which bus system an exclusive, collision-free access of a user station to the bus of the bus system is at least temporarily ensured, and a time control block for switching the two transistors and designed to switch on the two transistors while a signal on the first and/or second bus wire and/or a transmission signal, from which the signals on the first and/or second bus wire are generated, changes from a dominant state to a recessive state, and designed to switch off the two transistors if the signal on the first and/or second bus wire and/or the transmission signal is/are switched into the recessive state.