Abstract: An isolated gate driver including a driving control circuit, an isolated transformer, an anti-circuit and a secondary processing circuit is provided. The driving control circuit is configured to generate a driving PWM signal for driving a power switch tube. The isolated transformer has a primary winding and a secondary winding. The anti-circuit is connected between the driving control circuit and the primary winding of the isolated transformer, and is configured to suppress a variation of an induced voltage in the secondary winding of the isolated transformer when a duty cycle of the driving PWM signal is sharply decreased. The secondary processing circuit is connected in parallel with the secondary winding of the isolated transformer, and is configured to perform a voltage clamping action on a gate-source voltage of the power switch tube when the duty cycle of the driving PWM signal is sharply decreased.

Abstract: In one embodiment, a power switch driving circuit can include: (i) a first circuit configured receiving a control signal, and controlling a first transistor gate, where a first transistor source is coupled to a power supply, and a first transistor drain is coupled to a driving signal configured to control a power switch; (ii) a second circuit configured to receive the control signal, and to control a second transistor gate, where a second transistor source is coupled to ground, and a second transistor drain is coupled to the driving signal; and (iii) a driving enhancement circuit having a third transistor and a first inverter that is configured to invert an output of the first circuit to control a third transistor gate, where a third transistor source is coupled to the driving signal, and a third transistor drain is coupled to the power supply.

Abstract: The present invention relates to a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage. A second charging path is connectable between the gate terminal of the power transistor and a second supply voltage to charge the gate terminal from the first gate voltage to a second gate voltage larger or higher than the first gate voltage. A voltage of the second voltage supply is higher than a voltage of the first voltage supply.

Abstract: A drive circuit including a second switching element that is connected in series to a source of a first switching element, that is switched ON when the first switching element is switched ON, and that is switched OFF when the first switching element is switched OFF. The drive circuit includes a conduction element that is provided between a drain of the second switching element and a power line, and that connects the drain of the second switching element to the power line in accordance with a signal that switches the second switching element OFF.

Abstract: In one embodiment, a power switch driving circuit can include: (i) an upper switch having a first power terminal coupled to a voltage source, and a second power terminal coupled to a driving signal; (ii) a lower switch having a first power terminal coupled to the driving signal, and a second power terminal coupled to a first voltage level, where the first voltage level is higher than a first ground potential; (iii) an upper switch driving sub circuit configured to receive a control signal, and to drive the upper switch in response thereto; and (iii) a lower switch driving sub circuit configured to receive the control signal, and to drive the lower switch in response thereto, where the upper and lower switch driving sub circuits are coupled to a second ground potential.

Abstract: A multi-chip system may include a plurality of chips, and a channel shared by the plurality of chips. At least one of the plurality of chips includes a transmission circuit configured to transmit a signal to the channel. Drivability of the transmission circuit is adjusted based on a number of the plurality of chips.

Abstract: A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock.

Abstract: A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.

Abstract: An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power source and an output node; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power source and the output node; a first capacitive coupling part connected between a gate of the first PMOS transistor and gates of the second PMOS transistor and the second NMOS transistor; and a second capacitive coupling part connected between a gate of the first NMOS transistor and gates of the second NMOS transistor and the second PMOS transistor, a first bias voltage is applied to the gate terminal of the second PMOS transistor, and a second bias voltage is applied to the gate terminal of the second NMOS transistor.

Abstract: A driver circuit for a semiconductor switching device includes a drive power source, a capacitor and four switches, which form a bridge circuit. The capacitor is provided between the four switches. In one cycle of application of a voltage to a gate of the semiconductor switching device to turn on the semiconductor switch, the first and the second switches, which are diagonal, are turned off and the third and the fourth switches, which are diagonal, are turned on to charge the capacitor. Then only the first switch is turned on to apply the voltage to the gate, and lastly only the second switch is turned on to discharge the capacitor thereby to apply a negative voltage to the gate of the semiconductor switching device.

Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.

Abstract: Various apparatuses, methods and systems for damping a current driver are disclosed herein. For example, some embodiments provide an apparatus for supplying current, including an output transistor connected between a voltage supply and a current output, and an active clamp connected between the current output and a current sink. The active clamp is adapted to connect the current output to the current sink when a voltage at the current output reaches a predetermined state relative to a voltage at a control input of the output transistor.

Abstract: In a driver, a changing module changes a rate of discharging the control terminal of a switch at least between a first value and a second value lower than the first value. A measuring module measures a value of a parameter as a function of a current flowing through the conductive path of the switch during a drive signal being in an on state. A control module controls the changing module, as a function of the value of the parameter, to select the first value or the second value as the rate of discharging the control terminal of the switch upon the drive signal directing a change from the on state of the switch to an off state thereof. The control module discharges the control terminal of the switch using the selected value as the rate of discharging the control terminal of the switch.

Abstract: In accordance with an embodiment, a method of operating a gate driving circuit includes monitoring a signal integrity at an output of the gate driving circuit. If the signal integrity is poor based on the monitoring, output of the gate driving circuit is placed in a high impedance state and an external signal integrity failure signal is asserted.

Abstract: A switching control circuit controls a switching circuit based on decoded signals obtained by decoding several input signals. The switching control circuit is includes a decoder circuit that outputs decoded signals obtained by decoding coded input data signals. The switching control circuit includes a driver circuit that generates control signals for controlling the switching circuit based on the decoded signals. The switching control circuit is provided with a synchronous control circuit that synchronizes the input signals before outputting them for decoding.

Abstract: An electronic circuit for driving an electronic switch includes a first voltage terminal coupled to receive a first voltage from a power supply and a second voltage terminal coupled to receive a second voltage from the power supply. A driver circuit is configured to drive the voltage at a control terminal of the electronic switch to an intermediate voltage level in order to turn on the electronic switch during a high or normal voltage condition. A clamp circuit is configured to clamp the voltage at the control terminal of the electronic switch to the second voltage terminal in order to turn on the electronic switch during a low voltage condition, so that the electronic switch can enhance power provided to a load during the low voltage condition. A low voltage detection circuit detects the low voltage condition and provides a signal to activate the clamp circuit.

Abstract: A power drive apparatus is provided. The apparatus includes a first switch having a first plurality of power devices arranged in a back to back configuration within adjacent stacked rows of the first switch. The apparatus includes a second switch having a second plurality of power devices arranged in a back to back configuration within adjacent stacked rows of the second switch. A bus is shared with the first switch and the second switch. The apparatus includes a control drive device coupled to a gate of each power device of the first plurality of power devices and each power device of the second plurality of power devices.

Abstract: The present disclosure relates to methods and circuits to lowering the signal range of switching or logic circuits below supply range. The circuits may have one or more stages. The supply levels can be set individually for each stage. This may realize amplifiers/attenuators, both digitally and analogically controlled, based on progression and/or modulation in the supply range from stage to stage. A chain of stages can provide the desired power gain by setting the supply progression according to the nature of the incoming signals. The signal levels are lowered by generic device networks comprising voltage sources providing voltages independent of currents flowing through. Decoupling the signal amplitude from DC biasing allows for the signal swing to be lower than threshold voltages of the active devices.

Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.

Abstract: Systems and methods are provided for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. In one example, a power distribution network may supply power to components of an integrated circuit and data driver circuitry may draw first current to drive a data signal. Compensation circuitry may draw second current at times when the data driver circuitry is not drawing the first current, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device (e.g., the power distribution network).

Abstract: A signal transceiver includes a connector for receiving a signal, a band-pass filter coupled to the connector for filtering the signal, a front-end module for demodulating the signal and an adaptive impedance switch circuit coupled between the band-pass filter and the front-end module for switching an impedance value between the band-pass filter and the front-end module.

Abstract: A drive control apparatus for a semiconductor device having a diode and a transistor includes: a current detection device of a current flowing through the diode; and a control device, which applies a gate drive voltage to the semiconductor device when an on-instruction signal is input. The control device compares the current detection signal with a current threshold value during a first period, in which the on-instruction signal is input, after a second period has elapsed from gate drive voltage application time, or gate drive voltage shut-off time. A transient variation is generated on the current detection signal in the second period. The control device shuts off the gate drive voltage when the current detection signal is equal to or larger than the current threshold value. The control device applies the gate drive voltage when the current detection signal is smaller than the current threshold value.

Abstract: A floating gate driver uses a single-end level shifter to translate a set signal and a reset signal induced by a rising edge and a falling edge of a switch signal to a common output terminal to generate an output voltage for a bistable circuit to generate a level shifted switch signal. Under control of a well transient detect signal asserted by detecting noise in the output voltage, a masking circuit between the single-end level shifter and the bistable circuit masks noise in the output voltage. This configuration has lower area penalty and better noise immunity.

Abstract: A semi-metallic structure, comprising an LaAlO3—SrTiO3 heterostructure (19), said LaAlO3—SrTiO3 heterostructure comprising a two-dimensional hole gas (21) and a two-dimensional electron gas (23).

Abstract: A gate driving module includes a gate driver and a gate signal generator. The gate driver generates a vertical start signal, a plurality of gate clock signals and a plurality of inverse gate clock signals based on a vertical start control signal, a plurality of gate clock control signals, a gate on voltage, a first gate off voltage and a second gate off voltage. The number of the gate clock signals is P. The number of the inverse gate clock signals is P. The number of the gate clock control signals is P. P is a positive integer equal to or greater than two. The gate signal generator generates a gate signal based on the vertical start signal, the gate clock signals and the inverse gate clock signals.

Abstract: A gate drive circuit includes a power supply circuit that has an output switch function for switching a voltage value of a drive voltage between two levels, a gate-ON drive circuit that outputs a constant electric current toward a gate of an IGBT from an output terminal of the power supply circuit, and a control section performs a constant electric current drive of a gate of the IGBT at a time of a turn-ON by operating the gate-ON drive circuit. At a turn-ON start time, the control section sets the drive voltage to a relatively-high first set value, and then switches the drive voltage to a relatively-low second set value at a switch timing after a mirror period end time.

Abstract: Exemplary embodiments are directed to systems, devices, methods, and computer-readable media for reducing static and dynamic power consumption of a charge pump. In one embodiment, a device may include a plurality of switches, each switch of the plurality having a gate coupled to a dedicated driver of a plurality of drivers. The device may further include at least one clamp switch coupled to at least one driver of the plurality of drivers and configured to adjust a rail voltage of the at least one driver if an input voltage is greater than a threshold voltage. In another embodiment, the device may include a plurality of multiplexers, each multiplexer of the plurality of multiplexers coupled to a portion of an associated switch of the plurality of switches and configured to disable the portion of the associated switch if a clock frequency of the charge pump is below a threshold frequency.

Abstract: A hysteresis generator provides a hysteresis parameter V_hyst to a hysteresis comparator of a voltage regulator. The hysteresis parameter V_hyst is a function of circuit components of the hysteresis generator, a voltage output Vout of the regulator, a voltage input Vin of the regulator, and a signal that drives one of a plurality of switches of the regulator. A switch driver drives the switches based on the hysteresis parameter. One or more of the circuit components of the hysteresis generator that provide the hysteresis parameter also define a hysteresis time period T_hyst. The hysteresis time period T_hyst defines in combination with a delay time period T_Td of the regulator, a switching time period T for the regulator that is substantially constant.

Abstract: In a driver, a charging module stores negative charge on the gate of a switching element via a normal electrical path to charge the switching element upon a drive signal representing change of an on state to an off state. This shifts the on state of the switching element to the off state. An adjusting module changes a value of a parameter correlating with a charging rate of the switching element through the normal electrical path as a function of an input signal to the driver. The input signal represents a current flowing through the conductive path, a voltage across both ends of the conductive path, or a voltage at the gate. A disabling module disables the adjusting module from changing the value of the parameter if the drive signal represents the on state of the switching element.

Abstract: A driving circuit for at least one voltage controlled power switch device comprises a driver signal generating circuit and a trigger signal generating circuit adapted to generate trigger signals for said voltage controlled power switch device (PT). The trigger signal generating circuit includes a first driving transistor, and at least one energy buffer component coupled between the trigger signal generating circuit and the control electrode of said power switch device (PT).

Abstract: A drive circuit is provided for a target switching element and opens/closes a current path by controlling an absolute value of a potential difference between one end of the current path and an opening/closing control terminal. The drive circuit includes an integrated circuit connected to the control terminal. The integrated circuit includes an absolute value control circuit controlling the absolute value of the potential difference when the switching element is in an off-state, a stabilization circuit stabilizing the potential difference at a value for maintaining the switching element in an off-state when the switching element is in an off-state, a selection circuit selecting one of control of the absolute value of the potential difference by the control circuit and stabilization of the potential difference by the stabilization circuit, and an on-state terminal connected to the control circuit and the control terminal. The on-state terminal is connected to the stabilization circuit.

Abstract: A gate drive circuit of the present invention is a gate drive circuit for driving an insulated gate switching element, which comprises a control drive circuit for applying a driving voltage to a control terminal of the switching element at a predetermined timing, and a voltage monitoring circuit for monitoring both a first voltage which is a power supply voltage of the control drive circuit and a second voltage which negatively biases the control terminal of the switching element, and in the gate drive circuit, the control drive circuit cuts off an output when at least one of the first and second voltages monitored by the voltage monitoring circuit becomes lower than a threshold value. It is an object of the present invention to provide an insulated gate switching element which can suppress wrong ON.

Abstract: A Local Interconnect Network (LIN) driver circuit employs a charging/discharging current applied to the gate of a driver transistor coupled to an LIN bus. The charging current includes a constant charging current and an additional soft charging current, whereas the discharging current includes a constant discharging current and an additional soft discharging current. As a result of the soft charge/discharge components, there is a significant reduction in electromagnetic emission on the LIN bus.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract: Apparatus for a wireless tachometer receiver. The wireless tachometer receiver includes a receiver and a signal conditioner that drives a conventional tachometer. Conventional tachometers require an input consisting of pulses at the operating voltage of the vehicle, which is typically 12 Vdc. Conventional receivers have an alternating current output that is substantially less than the operating voltage of the vehicle, which is insufficient to trigger the tachometer reliably. The signal conditioner converts the receiver output to a signal that allows for reliable operation of the conventional tachometer. In one embodiment, the signal conditioner is an amplifier that has a gain to drive the amplifier output between zero and the operating voltage of the vehicle. In another embodiment, the signal conditioner is a step-up transformer that has a ratio sufficient to produce an output at the operating voltage of the vehicle.

Abstract: A pre-charging circuit, such as can be used to pre-charge a data bus, is presented that is largely process independent. A push-pull type of arrangement is used, where the output of the pre-charge circuit is initially connected to a supply level through one transistor, then connect to ground by another transistor. These transistors can be controlled by one or more comparators that have as inputs a reference level and feedback from the output. The reference level is generated by a circuit that tracks the threshold voltage of the other devices in the circuit in order to reduce process dependency of the output level. The circuit can also include a device to provide an extra VDD assist to the output.

Abstract: The invention concerns energy delivery system and method for a gate drive unit controlling a thyristor-based valve (19). The system comprises at least one current transformer (22) located in the main current path of the valve.

Abstract: A turn-on drive circuit for a power transistor comprising a first circuit comprising a resistor and capacitor in parallel and a second circuit comprising a resistor, the second circuit being in series in the drive path with the first circuit. A turn-off drive circuit for a power transistor comprising a first circuit comprising a first resistor and a second resistor in series in the drive path of the power resistor and a second circuit comprising a capacitor in parallel with one of the resistors of the first circuit.

Abstract: One of first and second switching devices turns on to flow a current along a current path between a potential reference output terminal of a drive-target switching device and a control terminal of the drive-target switching device to turn on the drive-target switching device. Thereby, a voltage changes between the control terminal of the drive-target switching device and the potential reference output terminal of the drive-target switching device to turn off the one of the first and second switching devices being turned on. Thereby, a potential of the control terminal of the drive-target switching device is clamped.

Abstract: A high voltage electrical switch including: a plurality of series connected semiconductor switches; a plurality of rectifiers wherein each rectifier is connected to a semiconductor switch control input of one of the semiconductor switches; a radio frequency signal generator; and a plurality of galvanic isolators, wherein each galvanic isolator connects the radio frequency signal generator to one of the plurality of rectifiers, wherein the plurality of semiconductor switches are isolated from one another.

Abstract: A sampling circuit comprising: an input node; a first signal path comprising a first sampling capacitor and a first signal path switch in a signal path between the input node and a first plate of the first sampling capacitor; a second signal path comprising a second sampling capacitor and a second signal path switch in a signal path between the input node and a first plate of the second sampling capacitor, and a signal processing circuit for forming a difference between a signal sampled onto the first sampling capacitor and a signal sampled onto the second sampling capacitor.

Abstract: A power semiconductor device driving circuit includes a gate control terminal, which is provided at a position separated from a drain terminal of a power semiconductor device by a predetermined distance so that electric discharge is generated between the drain terminal and the gate control terminal at the time of generation of surge. A surge voltage is applied to the gate control terminal due to this discharge, the gate of the power semiconductor device is charged to turn on and absorb the surge energy. Thus it becomes possible to suppress the surge voltage applied to the drain terminal and prevent breakdown of the power semiconductor device.

Abstract: A data converter can include a resistor network, a switch network connected to the resistor network and having a plurality of switch circuits, each with an NMOS and a PMOS switch transistor, and a voltage generator to generate a drive voltage for driving a gate of at least one of the NMOS or PMOS switch transistors of at least one of the switch circuits. The voltage generator can include first and second pairs of transistors, each pair having connected control terminals and being connected to a second NMOS or PMOS transistor, a first or second resistor, and the other pair of transistors. The first and second resistors can have substantially equal resistance values. A ratio of width-to-length ratios of the second NMOS to PMOS transistors can be substantially equal to such a ratio of the switch circuit NMOS to PMOS transistors.

Abstract: A driver includes a converter section 2 which includes a switching element Q1 and which is configured to output a desired DC voltage by switching the switching element Q1, a control section 1 configured to control the switching operation of the switching element Q1, capacitors C1A, C1B charged by the output of the converter section 2, turn-on circuits 31A, 31B configured to supply gates of a bidirectional switch element 4 using electric charges stored in the capacitors CIA, C1B with drive powers to turn-on the bidirectional switch element 4, and turn-off circuits 32A, 32B configured to discharge the capacitors CIA, C1B to turn-off the bidirectional switch element 4 in response to the halt of the switching operation of the switching element Q1 by the control section 1.

Abstract: There are provided a gate driving circuit and a battery management system including the same. The gate driving circuit is coupled to a gate of a charging switch through a charging pin. The gate driving circuit includes a first transistor for performing a switching operation in accordance with a gate control signal to control a connection between a power supply voltage and a charging pin, a second transistor having a switching operation controlled in synchronization with a switching state of the first transistor and coupled between the charging pin and the first transistor, and a diode coupled between the first transistor and the second transistor and positive biased by the power supply voltage.

Abstract: In the invention, a circuit control device controlling a semiconductor switching element having a control terminal and driven by voltage inputted to the control terminal, has an input voltage detector, a desired voltage setting portion and a control input generation portion. The input voltage detector detects inputted voltage to the switching element. The desired voltage setting portion sets a desired value of the voltage to be inputted to the switching element. The control input generation portion is connected to the control terminal of the switching element, the control input generation portion generating control input to the switching element such that the value to be detected by the input voltage detector closes to the set desired value. The desired voltage setting portion sets the desired value of the voltage on the basis of predetermined characteristics information and operating parameters of the switching element. The operating parameters include temperature of the switching element, Vce, Ice etc.

Abstract: Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.

Abstract: Recycling energy in a clock distribution network is provided. A circuit includes a clock driver associated with a clock signal and having an output connected to a first load capacitance. The circuit also includes a second load capacitance connected in parallel with the first load capacitance. The circuit further includes a power transfer circuit including an inductor and a transmission gate connected in series between the first load capacitance and the second load capacitance. The power transfer circuit controls a flow of energy between the first load capacitance and the second load capacitance based on the clock signal.

Abstract: A controller for a switch and a method of operating the same. In one embodiment, the controller is configured to measure a voltage of a control terminal of the switch and select a first mode of operation if the voltage of the control terminal is greater than a threshold voltage, and a second mode of operation if the voltage of the control terminal is less than the threshold voltage.