Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: In accordance with an embodiment, switch driver includes a first switch driver configured to be coupled to a control node of a first switch, a second driver configured to be coupled to a control node of a second switch, and a first terminal and a second terminal configured to be couple to a boot capacitor. The first terminal is coupled between a boot input of the first switch driver and the second terminal is configured to be coupled to outputs of the first switch and the second switch. The switch driver further includes a voltage measurement circuit coupled to the first terminal and the second terminal, and a control circuit configured to activate the second switch driver when the voltage measurement circuit indicates that a voltage across boot capacitor is below a first threshold.

Abstract: A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer is between the first gate electrode and the second gate electrode. The oxide semiconductor layer has a pair of side surfaces in contact with the source electrode and the drain electrode and includes a region surrounded by the first gate electrode and the second gate electrode without the source electrode and the drain electrode interposed therebetween.

Abstract: A circuit for a semiconductor switching element including a transformer. One embodiment provides a first voltage supply circuit having a first oscillator. A first transformer is connected downstream of the first oscillator. A first accumulation circuit for providing a first supply voltage is connected downstream of the first transformer. A driver circuit having input terminals for feeding in the first supply voltage and having output terminals for providing a drive voltage for the semiconductor switching element, designed to generate the drive voltage for the semiconductor switching element at least from the first supply voltage.

Abstract: Devices and methods are provided in which a driver is supplied via a first current path and a second current path which can comprise a switching element.

Abstract: A switch bias system is provided that includes a bipolar junction transistor (BJT) switch comprising a base, emitter, and collector; an energy storage circuit coupled to the collector of the BJT, the energy storage circuit supplying current flow to the collector of the BJT; a current transformer circuit coupled to the emitter, the current transformer circuit configured to sense current flow through the emitter of the BJT switch; and a proportional bias circuit configured to generate a bias current to the base of the BJT switch, the bias current set to a proportion of the sensed current flow through the emitter of the BJT switch.

Abstract: A switching circuit, comprising: a main switch having a control terminal; and a clock-path portion connected to the control terminal of the main switch to apply a driving clock signal thereto so as to drive the main switch, wherein the circuit is configured to controllably apply a biasing voltage to the clock-path portion so as to bias a voltage level of the driving clock signal as applied to the control terminal of the main switch.

Abstract: A gate driving circuit includes plural-stage output circuits, an Nth stage output circuit of the plural-stage output circuits includes an Nth stage shift register and a mixer. The Nth stage shift register is configured to output an Nth pulse signal. The mixer is coupled to the Nth stage shift register and an (N+M)th stage shift register, for respectively outputting a first clock signal and a predetermined pulse signal during different periods according to the Nth pulse signal and an (N+M)th pulse signal of the (N+M)th stage shift register. Wherein pulse widths or phases of the first clock signal and the predetermined pulse signal are different, and N and M are positive integers.

Abstract: Disclosed herein is a gate driver. The gate driver according to an exemplary embodiment of the present invention includes: a first power switch sourcing current according to voltage applied by a voltage source; a second power switch connected with the first power switch in series and sinking current according to the voltage applied by the voltage source; and a speed booster receiving a voltage pulse from the outside to output peak current so as to make a turn on/off operation of the first power switch fast. As set forth above, according to the exemplary embodiments of the present invention, it is possible to improve the driving speed of the gate driver without increasing the current of the current source by further including the speed booster configured of the plurality of MOSFETs and the capacitor.

Abstract: A driver circuit for a digital signal transmitting bus includes a main switch. The main switch is connected to the bus, is controllable by the digital signal to be transmitted, and has one on-switching state in which it has maximum electrical conductivity, one off-switching state in which it has minimum electrical conductivity and at least one intermediate switching state with an electrical conductivity between the minimum and maximum conductivity. The digital signal has a first logic state and a second logic state, the first logic state controls the main switch to be in the on-switching state and the second logic state controls the main switch to be in the off-switching state. The main switch is in the intermediate switching state during switching from the on-switching state to the off-switching state and/or vice versa.

Abstract: A driving circuit of the present invention drives a switching element connected to a main current circuit. The driving circuit includes a driving potion applying on/off-voltage to a gate of the switching element, a common inductor disposed in an interconnection part commonly connected to the driving circuit and a source side of the switching element in a loop formed of the main current circuit and the switching element, and a capacitor connected between the gate side and the source side on the driving portion side with respect to the common inductor.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A power module includes an IGBT; a MOSFET connected in parallel with the IGBT; a lead frame having a first frame portion on which the IGBT is mounted and a second frame portion on which the MOSFET is mounted, and having a step by which the first frame portion is located at a first height and the second frame portion is located at a second height larger than the first height; and an insulation sheet for a heat sink which is disposed on an underside of only the first frame portion of the lead frame.

Abstract: The present invention provides a safe circuit that can prevent an arm short, when a half-bridge circuit is configured by using a normally-on switching element, and the half-bridge circuit is used as a driver circuit or an inverter circuit. In a driver circuit configured by a half-bridge circuit in which one of input and output terminals of a first switching element 14 is connected to a first power-supply voltage V1 on a high-voltage side, and the first switching element 14 and a second switching element 15 are connected in series, a normally-off third switching element 16 is inserted between the second switching element 15 and a second power-supply voltage V2 on a low voltage side. The third switching element 16 is turned off, when an operating voltage VH or VL supplied from control-circuit power supplies 13a and 13b is insufficient for the operation of a control circuit 11.

Abstract: A semiconductor device driving unit to supply a drive signal to a gate of a semiconductor switching device, the semiconductor device driving unit comprising: a plurality of gate impedance circuits selectably connectable to the gate of the semiconductor switching device; and a selector to select one or more of the gate impedance circuits to connect to the semiconductor switching device. Also provided is a method of supplying a drive signal to a gate of a semiconductor switching device, the method comprising: selecting one or more of a plurality of gate impedance circuits to be connected to the gate of the semiconductor switching device based on one or more operating conditions and stored data relating to the one or more operating conditions; and connecting the selected one or more of the gate impedance circuits to the semiconductor switching device.

Abstract: A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: an line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.

Abstract: A power stage has a differential output stage 2 driven by one or more buffer stages 4. The buffer stages 4 are implemented as high and low side buffers 12,14, each of which is itself a differential buffer implemented using transistors formed in an isolated-well technology such as triple-well CMOS.

Abstract: A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch.

Abstract: An inverter device includes a rectifier circuit that rectifies alternating-current power supplied from a main power supply and generates direct-current power, a control power supply circuit that generates direct-current power for control using at least one of the generated direct-current power and direct-current power supplied from an external power supply, and a control unit that receives the generated direct-current power for control and performs a predetermined control operation. The control power supply circuit includes an insulation transformer including a primary side and second side winding wires, a first control power supply capacitor connected to the secondary side winding wire via a first diode, an external power supply capacitor connected to the first control power supply capacitor via a second diode and connected to a terminal, to which the external power supply is connected, via a third diode, and a second control power supply capacitor connected to the external power supply capacitor.

Abstract: An output buffer has a first transistor and a voltage mitigation second transistor. The first transistor is configured to generate a voltage value corresponding to the power-supply voltage in response to an input signal. The second transistor is provided between an output line and the first transistor. A gate terminal of the second transistor is applied with a power-supply bias voltage which turns the second transistor on and makes a voltage between gate and source terminals of the second transistor constant in accordance with a power-supply voltage.

Abstract: A power package is provided comprising a packaged transistor and a driving unit connected to the transistor and adapted to drive the transistor. A control terminal of the transistor is connected to a middle terminal pin of the housing of the transistor and outer terminal pins of the housing are connected to the driving unit and to a voltage level, respectively, wherein the connections are crossing free.

Abstract: Provided is a driver circuit of a semiconductor apparatus that is capable of operating with improved reliability and consuming less current. The driver circuit comprises a driver configured to generate an internal voltage using a power voltage in response to a control voltage and a controller configured to change the control voltage to a level higher than a level of the power voltage in response to a stand-by mode signal.

Abstract: A display and a gate driver are disclosed herein, in which the gate driver includes a number of gate driving units, and each of the gate driving units includes a control circuit, a boost circuit, a driver output circuit and a voltage stabilized circuit. The control circuit is electrically connected to a previous gate driving unit and a next gate driving unit. The boost circuit is electrically connected to the control circuit for driving the next gate driving unit. The driver output circuit is electrically connected to the boost circuit and a pixel array for driving at least one scan line in the pixel array. The voltage stabilizing circuit is electrically connected to the boost circuit and the driver output circuit.

Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: A voltage regulator includes a comparing circuit configured to compare a first voltage reference to a second voltage reference and to generate an output. A first circuit applies gain to the output of the comparing circuit and buffers the output of the comparing circuit. A first transistor includes a gate in communication with an output of the first circuit, a first terminal in communication with a first voltage reference and a second terminal in communication with an output of the voltage regulator. A second circuit applies gain and buffers the output of the first circuit. A latching circuit receives an output of the second circuit. A voltage reference circuit generates the second voltage reference based on the output of the voltage regulator. A reference adjusting circuit receives an output of the latching circuit and selectively adjusts the second voltage reference.

Abstract: A current generation circuit includes a mirroring circuit suitable for being charged by using a bias voltage, wherein a voltage level of the charged voltage varies corresponding to changes in a voltage level of a power voltage, a comparison circuit suitable for comparing the charged voltage with a feedback voltage, and a current driving circuit suitable for generating a current based on a voltage output from the comparison circuit.

Abstract: A circuit with a temperature detector includes a first FET and a second FET. Each of the first and second FETs has a channel structure having a non-planar structure. The second FET is in close proximity to the first FET. A gate of the second FET is separated from the first FET, and a source and drain of the second FET are shorted together. A resistance of the gate of the second FET between two terminals on the gate of the second FET varies with a temperature local to the first FET.

Abstract: A semiconductor element module includes a driving element and a voltage change detecting element each formed of a voltage driving semiconductor element. The voltage change detecting element detects a change of a voltage between a collector and an emitter or between a drain and a source of the driving element. A collector or a drain of the voltage change detecting element is connected to the collector or the drain of the driving element, and a gate of the voltage change detecting element is connected to an emitter or a source of the voltage change detecting element. The emitter or the source of the voltage change detecting element is provided as a detecting terminal.

Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

Abstract: System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch.

Abstract: A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

Abstract: An improved gate drive circuit is provided for a power device, such as a transistor. The gate driver circuit may include: a current control circuit; a first secondary current source that is used to control the switching transient during turn off of the power transistor and a second secondary current source that is used to control the switching transient during turn on of the power transistor. In operation, the current control circuit operates, during turn on of the power transistor, to source a gate drive current to a control node of the power transistor and, during turn off of the power transistor, to sink a gate drive current from the control node of the power transistor. The first and second secondary current sources adjust the gate drive current to control the voltage or current rate of change and thereby the overshoot during the switching transient.

Abstract: A methodology for controlling FET switch-on with VGS temperature compensation is based on establishing a VGS clamping voltage with PTAT and CTAT voltage references with complimentary temperature coefficients. In one embodiment, the methodology can include: (a) generating a PTAT current from a PTAT ?VBE current source including a ?VBE resistor; (b) supplying the PTAT current to the gate node to control FET switch-on; and (c) establishing a temperature compensated VGS clamping voltage at the gate node. The VGS clamping voltage can be established with gate control circuitry that includes the PTAT and CTAT voltage references. A PTAT voltage VPTAT is dropped across a PTAT resistor RPTAT characterized by a temperature coefficient substantially the same as the ?VBE resistor. The CTAT voltage VCTAT is dropped across one or more CTAT VBE component(s) each characterized by a VBE,CTAT voltage drop with a CTAT temperature coefficient.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A driver circuit is connected to a control terminal of a voltage-controlled switching element via a connection line. The drive circuit drives the switching element. The switching element is switched to an ON state by charging the control terminal of the switching element via the connection line. The switching element is switched to an OFF state by discharging the control terminal of the switching element via the connection line. A voltage at a predetermined position on the connection line is detected. An open circuit state between the control terminal and the predetermined position is detected based on a speed of change in the detected voltage at the predetermined position when the switching element is switched to the ON state or the OFF state.

Abstract: A method for controlling a circuit control system. Currents are sensed at outputs of transistors in the circuit control system. Levels are identified for the currents. A number of characteristics of the transistors are controlled while the currents flow out of the transistors such that the currents flowing out of the transistors have desired levels.

Abstract: A power semiconductor device includes an output transistor, a control circuit connected with a gate of the output transistor, a first discharge route from a first node to a ground terminal, and a second discharge route from the first node to the ground terminal. In a usual turn-off, only the first discharge route is used. When a load abnormality occurs, both of the first and second discharge routes are used. The second discharge route contains a discharge transistor and a countercurrent prevention device. The discharge transistor is connected between the first node and the second node. The countercurrent prevention device prevents a flow of current from the third node to the second node. At least, in an OFF period, the control circuit sets the gate voltage of the discharge transistor to a high level.

Abstract: An electronic circuit includes a reverse-conducting IGBT and a driver circuit. A first diode emitter efficiency of the reverse-conducting IGBT at a first off-state gate voltage differs from a second diode emitter efficiency at a second off-state gate voltage. A driver terminal of the driver circuit is electrically coupled to a gate terminal of the reverse-conducting IGBT. In a first state the driver circuit supplies an on-state gate voltage at the driver terminal. In a second state the driver circuit supplies the first off-state gate voltage, and in a third state the driver circuit supplies the second off-state gate voltage at the driver terminal. The reverse-conducting IGBT may be operated in different modes such that, for example, overall losses may be reduced.

Abstract: A dynamic voltage scaling system having time borrowing and local boosting capability, including: a time borrowing circuit and a local boost circuit. The time borrowing circuit connected electrically between a primary stage logic circuit and a secondary stage logic circuit is activated by an all-domain clock signal, and then generates an output data to the secondary stage logic circuit based on input data to the primary stage logic circuit. The local boost circuit is connected to a low working voltage line, when input data of the time borrowing circuit lags behind a positive level of said all-domain clock signal, the time borrowing circuit delays fetching data by a flip flop and changes state to produce a warning signal, so that the local boost circuit disconnects its connection with said low working voltage line, and is connected electrically to a high working voltage line.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: A signal transmission circuit includes an output transistor with a first terminal connected to an output terminal of an output signal; a driver circuit configured to drive a control terminal of the output transistor in response to an input signal; a voltage follower configured to generate a first voltage by buffering the output signal; a voltage divider configured to generate a second voltage by dividing the first voltage; and a capacitor connected between a supply terminal of the second voltage and the control terminal of the output transistor.

Abstract: Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information.

Abstract: According to one embodiment, there is provided an output circuit including a driver transistor and a pre-driver circuit. The driver transistor is connected to an output terminal. The pre-driver circuit is configured to turn ON/OFF the driver transistor. The pre-driver circuit includes a first transistor, a second transistor, a third transistor. The first transistor is configured to control ON speed of the driver transistor. The second transistor is connected in parallel with the first transistor. The second transistor is configured to control ON speed of the driver transistor. The third transistor is connected in parallel with the first transistor and in series with the second transistor. The third transistor is configured to activate or deactivate the second transistor.

Abstract: An impedance circuit coupled to a first power supply includes: an output node; a transistor coupled between the output node and the first power supply, wherein the transistor comprises a gate electrode; and a voltage source electrically coupled to the gate electrode of the transistor and configured to apply a gate voltage to the gate electrode of the transistor, wherein the voltage source includes: a plurality of impedance components electrically coupled in series between a circuit node and the first power supply, and a current source electrically coupled between the circuit node and a second power supply.