Abstract: Disclosed herein is a clock generator that comprises a master or first oscillator having an output terminal which provides a master clock signal and at least one slave or second oscillator having an output terminal which provides a slave clock signal, the master and slave oscillators comprising respective time delay stages and latches, the slave oscillator also comprising logic gates connected to the outputs of the latches and configured to logically combine said outputs to generate a slave clock signal having a different phase with respect to a master clock signal.

Abstract: A circuit includes a phase adjustment circuit and a dead zone detect circuit. The phase adjustment circuit is operable to receive periodic signals and is operable to provide one of the periodic signals as a selected periodic signal based on a phase comparison between a data signal and the selected periodic signal. Each of the periodic signals has a different phase. The dead zone detect circuit is operable to cause the phase adjustment circuit to shift a phase of the selected periodic signal if the dead zone detect circuit determines that the data signal is in a dead zone. The dead zone detect circuit defines the dead zone based on two of the periodic signals. The phase adjustment circuit is operable to adjust a phase range of the dead zone.

Abstract: In one embodiment, the present invention includes a de-serializer to receive serial data at a first rate and to output a parallel data frame corresponding to the serial data aligned to a frame alignment boundary in response to a phase control signal received from a feedback loop coupled between the de-serializer and a receiver logic coupled to an output of the de-serializer. Other embodiments are described and claimed.

Abstract: A first periodic signal generation circuit generates first periodic output signals. A second periodic signal generation circuit generates second periodic output signals. A first multiplexer circuit receives the first and the second periodic output signals. An interface circuit coupled to external pins generates a third periodic output signal based on a periodic signal selected by the first multiplexer circuit. A second multiplexer circuit receives the third periodic output signal at an input. A first periodic feedback signal provided to the first periodic signal generation circuit is based on a signal selected by the second multiplexer circuit. A third multiplexer circuit receives the third periodic output signal at an input. A second periodic feedback signal provided to the second periodic signal generation circuit is based on a signal selected by the third multiplexer circuit.

Abstract: A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is entered into a ForceSL (Force Shift Left) mode and an On1x mode (i.e., left shifting on each clock cycle). The feedback clock that tracks the phase of the reference clock (which, in turn, is derived from the system clock) is initially delayed in a coarse phase detector prior to applying it to the coarse phase detection window. Two delayed versions of the feedback clock are sampled by the reference clock to generate a pair of phase information signals, which are then used to establish an advanced phase equal (APHEQ) signal. The APHEQ signal advances onset of the PHEQ (phase equalization) phase and is used to terminate the ForceSL and On1x modes, thereby preventing wrong ForceSL exit due to clock jitter or feedback path overshooting during On1x exit.

Abstract: A clock regeneration circuit according to an exemplary embodiment of the present invention is characterized in that a phase comparison result of serial data being inputted and a clock signal is shaped with use of the clock signal or another clock signal having a predetermined phase difference from the clock signal, and a phase of the clock signal is controlled with use of the shaped phase comparison result.

Abstract: An electronic circuit for distributing a clock signal to several clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; loop filters for generating and transmitting respective DC voltage feedback signals; current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: A semiconductor device includes a clock input block to receive a system clock and a data clock, a clock frequency dividing block to generate a plurality of multi-phase data frequency division clocks each of which has the phase difference of a predetermined size by dividing a frequency of the data clock and to determine whether or not phases of the plurality of multi-phase data frequency division clocks are reversed in response to a frequency division control signal, and a first phase detecting block to detect a phase of the system clock based on a phase of a first selected clock that is predetermined among the plurality of multi-phase data frequency division clocks and to determine a logic level of the frequency division control signal in response to the detected result.

Abstract: A semiconductor device for applying an auto clock alignment training mode to reduce the time required for a clock alignment training operation. The semiconductor device adjusts the entry time of the auto clock alignment training mode to prevent the clock alignment training operation from malfunctioning. The semiconductor device includes a clock division block configured to divide a data clock to generate a data division clock, a phase multiplex block configured to generate a plurality of multiple data division clocks in response to the data division clock, a logic level control block configured to set a period, in which a division control signal is changeable, depending on the data division clock, and a first phase detection block configured to detect a phase of a system clock on the basis of the multiple data division clocks in the period, and to generate the division control signal corresponding to a detection result.

Abstract: One or two Serializer/Deserializer (SerDes) modules are used to measure the time between two pulses with high resolution. A PLL inside a SerDes block is locked to a reference clock and an input signal is passed through a storage element to create a serial data stream that is converted into a parallel data stream by a demultiplexer inside the SerDes. The parallel data is stored in a bit logic unit that compares the parallel data to a second parallel data obtained in similar fashion in another SerDes from a second input signal. The time between the two pulses is then calculated as the number of cycles in the serial data stream that corresponds to the number of bits between the positions of the two events.

Abstract: In a reception apparatus 1, a multiphase sampling clock signal is generated by a sampling clock signal generation circuit 40, based on a clock signal which has been phase-adjusted by a phase adjustment circuit 50. The data of each of the bits of a serial data signal is sampled and output by a sampler block circuit 30n, with timing indicated by the sampling clock signal. The amount of phase adjustment of the clock signal in the phase adjustment circuit 50 is set such that the delay time from generation of the multiphase sampling clock signal in the sampling clock signal generation circuit 40 until indication of the sampling timing by the sampling clock signal in the sampler block circuit 30n is canceled.

Abstract: A phase-locked loop arranged to generate an output signal having a first frequency that is a static value times the frequency of a reference signal, the phase-locked loop comprising a signal generator arranged to generate the output signal, a divider arranged to receive the output signal and divide the output signal to form a feedback signal, the divider being arranged to vary the divisor by which the output signal is divided to cause the output signal to have a frequency that is said static value times the frequency of the reference signal, a comparison unit arranged to compare the feedback signal with the reference signal, one or more current generators arranged to output current pulses in dependence on said comparison, a summation unit arranged to receive the current pulses output by the current generator(s) and form a single current pulse therefrom and a loop filter arranged to filter the single current pulse to form a control signal for controlling the signal generator, the phase-locked loop being arrang

Abstract: An electronic circuit for distributing a clock signal to a plurality of clock destinations includes phase adjustment circuits for adjusting phase shifts of the clock at the respective one of the clock destinations responsive to a respective DC voltage feedback signal receive from the respective one of the clock destinations; phase detectors for detecting a phase shift of the clock signal at the respective one of the clock destinations according to a nearest neighbor clock destination; and loop filters for generating and transmitting respective DC voltage feedback signals. The circuit further includes current sources, each configured to receive the respective DC voltage feedback signal and output a respective current to a respective one of the phase adjustment circuits according to said respective DC voltage feedback signals to adjust the phase shift of the clock signal for the respective one of the clock destinations.

Abstract: Method and apparatus for detecting clock loss in clock circuit. An example of the invention relates to detecting loss of a feedback clock signal input to a digital clock manager, where the feedback clock signal is derived from the reference clock signal. A clock divider is provided to produce a divided feedback clock signal from the feedback clock signal. A first pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of the reference clock signal. A second pair of flip-flops is configured to store samples of the divided feedback clock signal on consecutive edges of an inversion of the reference clock signal. Detection logic is configured to detect whether each of the first pair of flip-flops and each of the second pair of flip-flops store the same value.

Abstract: Disparate clock domains are resynchronized after circuits in one of the clock domains awake from a reduced power state. Parallel test data is routed from a core circuit to a parallel-to-serial converter in an input/output (I/O) circuit. The parallel-to-serial converter clocks the parallel test data in response to a load signal. The load signal is varied until the clock domains are synchronized.

Abstract: A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.

Abstract: Provided is an oscillation circuit for generating an oscillation signal synchronized with a supplied reference clock, including: a voltage control oscillation section that, when triggered by each edge of the reference clock, stops oscillation of the oscillation signal having a frequency in accordance with a supplied control voltage to start new oscillation; a phase comparing section that compares a phase of a comparison signal that is in accordance with the oscillation signal outputted from the voltage control oscillation section and a phase of a signal that is in accordance with the reference clock; and a voltage control section that supplies the control voltage in accordance with a comparison result of the phase comparing section, to the voltage control oscillation section.

Abstract: Clock signals are supplied, with a phase shift of 1/n cycles between adjacent clock signals. A data acquisition unit acquires serial data at a timing of each of the clock signals. A phase detection unit detects the phase of the transition edge of the serial data using n bits of data. An effective bit number determination unit determines the effective bit number, which is the number of bits to be acquired, based upon the phase of the transition edge of the serial data in the current data-bit acquisition step and the phase of the transition edge of the serial data in the previous data-bit acquisition step. A data-bit output unit outputs the effective bit number of the bits of data acquired at a timing of each clock signal having a predetermined phase relation with the transition edge of the serial data.

Abstract: A programmable delay clock buffer circuit, preferably implemented in a single IC, includes a clock circuit and a plurality of variable delay lines. The clock circuit receives an input clock and is clock feedback signal and generates an intermediate clock. Each of the delay lines is configured to receive the intermediate clock and to receive at least one delay control input. A first variable delay line of the plurality is configured to generate, based on a first delay control input, a first delay from the intermediate clock to produce a clock output signal. A second variable delay line of the plurality is configured to generate, based on a second delay control input, a second delay from the intermediate clock to produce a clock feedback signal. A method of distributing clock with through programmable delay lines is also presented.

Abstract: A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter ? and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on ?, i and j. The discrete analogue ri,j is based on a respective si,j. Examples are given of ? = 2 B - A 2 B and D>i?0 and 2C>j?0, where B?0, 2B>A>0, C?1 and D?1, and magnitude s i , j = 1 - ? i + ? i · 1 - ? 2 C · j ? ? or ? ? s D - 1 , j = 1 - ? D - 1 + ? D - 1 · 1 2 C · j . In some embodiments, a segment is defined based on ? and i. The segment is divided into points based on respective values of j, and the magnitude is calculated for each point of the segment. The defining and dividing segments and calculating the magnitude is iteratively repeated for each value of i.

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source includes of a controllable digital fractional divider receiving a control value from digital comparator and a clock input from a digital clock synthesizer driven by a fixed oscillator.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: Methods and apparatus are provided for generating a frequency with a predefined offset from a reference frequency. A spread spectrum generator circuit is disclosed that comprises a voltage controlled delay loop for generating a plurality of signals having a different phase; and at least one interpolator for processing at least two of the signals to generate an output signal having a phase between a phase of the at least two of the signals, wherein the output is varied between a phase of the at least two of the signals to generate the spread spectrum. A spread spectrum having a frequency lower than an applied clock signal is generated using a continuous phase delay increase and a spread spectrum having a frequency higher than the clock signal is generated using a continuous phase delay decrease.

Abstract: A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another.

Abstract: Disclosed is a clock and data recover circuit including N flip-flops (F/Fs) for sampling an input data signal using N-phase clocks, a phase comparison circuit for performing phase comparison based on outputs of the F/Fs, a filter or smoothing a result of the phase comparison and outputting an up/down signal, up/down counters, each for receiving an output of the filter and counting up or down a count value thereof, a phase shift circuit for adjustably controlling phases of the clocks for edge detection and the clocks for data sampling according to phase control signals from an up/down counter and an up/down counter, respectively, and an up/down control circuit for receiving a control signal for controlling maximum and minimum values of count values of the up/down counter, generating a signal for controlling counting up and down of the up/down counter based on the count value of the up/down counter, and supplying the generated signal to the up/down counter.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.

Abstract: A multi-phase clock generator circuit receives an input clock signal and produces multiple output clock signal, each from a respective delay stage of a multi-stage voltage-controlled delay line (VCDL). The rising edges of the multiple output clock signals produced by the circuit are substantially equidistant in time from one another and have substantially equal phase spacing.

Abstract: A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.

Abstract: Techniques are provided for compensating for phase and timing delays in clock signals generated by phase-locked loops and delay-locked loops on integrated circuits. Circuit elements coupled in a feedback loop of a locked circuit can compensate for the timing and phase delays between an input pin and an output pin. Other circuit elements coupled in the feedback loop of a locked circuit can compensate for the delay between an input pin and a destination circuit element. Still other circuit elements coupled in an input reference path of a locked circuit preserve a timing relationship between input clock and input data signals. A clock signal and a data signal received at a destination circuit element have the same phase and timing relationship that exists between the input clock and input data signals at input pins.

Abstract: A clock and data recovery circuit includes a phase detector configured to compare a phase of a data signal to a phase of a sampling clock to provide a phase error signal, a gain stage configured to apply a gain to the phase error signal to provide an amplified phase error signal, and a filter configured to filter the amplified phase error signal to provide a phase correction signal. The circuit includes a gain controller configured to adjust the gain of the gain stage in response to the phase correction signal, and a clock generator configured to provide the sampling clock based on the phase correction signal.

Abstract: A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a multiplexer. The comparator with hysteresis receives the input signal and generates a comparison signal. The counter receives the comparison signal, calculates the pulse number of the comparison signal in one period, and outputs a pulse value. The frequency determiner receives the pulse value, calculates the frequency of the input signal, and generates a frequency value. The multi-phase clock generator receives the frequency value and generates multi-phase reference clocks according to the frequency value. The transition detector receives the comparison signal and generates a transition signal.

Abstract: An automatic frequency correction phase-locked loop (PLL) circuit includes an analog control circuit and a digital control circuit. The digital control circuit includes a High-side comparator and a Low-side comparator which receive an analog control voltage, a state monitor circuit, and a counter and decoder circuit. At least one of the High-side comparator and the Low-side comparator includes a threshold switching circuit which selectively provides a first threshold voltage and a second threshold voltage, the first and second threshold voltages having different magnitudes. When the analog control voltage remains stable between the High-side threshold voltage and the Low-side threshold voltage and the threshold switching circuit is providing the first threshold voltage, the state monitor circuit switches the threshold switching circuit from the first threshold voltage to the second threshold voltage, thereby expanding the interval between the High-side threshold voltage and the Low-side threshold voltage.

Abstract: A signal output circuit for outputting an output signal in accordance with a predetermined system timing is provided. The signal output circuit includes a shift register that delays an input signal in accordance with the system timing, a flip-flop that receives the input signal delayed by the shift register in response to a clock signal supplied thereto, and outputs the input signal as the output signal, and an initializing section that measures a delay amount achieved by the shift register and judges whether the measured delay amount is in accordance with the system timing.

Abstract: A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first domain control signal pulse is generated in response to the first domain clock signal for controlling the target. Each assertion the first domain control signal pulse is detected and used to form a second domain control signal pulse synchronized to the second domain clock signal. The target is controlled using the second domain control signal pulse. If the target is a clear-on-read register, contents of the clear-on-read register are latched in a feedback register in response to the first domain control signal pulse and provided to the controller. Each bit of the clear-on-read register is reset in response to the second domain control signal pulse only if the corresponding latched content of each bit in the feedback register is a logical one.

Abstract: A clock generator (622) includes a first circuit (812) and a second circuit (814). The first circuit (812) includes a first clock input configured to receive a first clock signal at a first frequency, a second clock input configured to receive a second clock signal at the first frequency, and an output. The second clock signal is out-of-phase with the first clock signal. The second circuit (814) is coupled to the first circuit (812) and includes a mode signal input configured to receive a mode signal. The output of the first circuit (812) is configured to provide a generated clock signal whose effective frequency is based on the first and second clock signals and the mode signal.

Abstract: An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable.

Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract: A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output.

Abstract: A data signal is generated in a pattern generation logic built in a TX port and given to a serializer, and a path is provided for looping an output of the serializer back to a deserializer and a CDR circuit of an RX port, whereby a BIST configuration enabling jitter measurement inside a high-speed serial transmission input/output section is adopted.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

Abstract: A ballast according to the present invention operates in an ignition state, a warm-up state, and a steady state for igniting and powering a lamp. The ballast comprises an igniter that ignites the lamp during the ignition state and a switching power inverter, for example, a full bridge DC-AC inverter implemented with MOSFET switching transistors, that powers the lamp during the warm-up and steady states. The switching power inverter, which drives the igniter, operates at a first switching frequency during the ignition state and operates at a second switching frequency during the steady state. Preferably, the first switching frequency, which in one exemplary embodiment is in the kHz range, is higher than the second switching frequency.

Abstract: A phase alignment circuit having a phase selection circuit, a synchronizer, and a counter form a feedback loop for aligning a local clock signal with a received reference clock of a synchronous communications system. The phase selection circuit is configured for outputting the local clock signal as a phase-adjusted local clock having a selected phase based on a phase selection value specified by the counter. The synchronizer is configured for digitally sampling the received reference clock relative to the phase-adjusted local clock, and outputting a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock. The counter selectively increments or decrements a counted value based on the digital phase bit, and outputs to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: In a method and system for controlling a device coupled to an information handling system, an object is defined to include a hardware and software component having a corresponding hardware operating state and a software operating state. The hardware component is operable to receive at least one hardware input, which is indicative of a target hardware operating state. The software component is operable to receive at least one software input, which is indicative of a target software operating state. A coordination component is included in the software component to receive the hardware and software inputs, and control the operating state of the device in response to the target hardware operating state and the target software operating state.

Abstract: In a PLL circuit including a voltage-controlled oscillator, a phase detector and a final control element, the final control element contains two separate channels, between the phase detector and the voltage controlled oscillator, wherein one channel processes the useful signal components and the other channel processes the disturbance signal components of the synchronization pulses. Each channel has two tracks, for generation of a potential difference, wherein each track is connected to a capacitor plate.