Abstract: A first pulse selector outputs an output signal of a variable frequency divider to phase frequency detectors in a time division manner. A second pulse selector outputs a reference signal from a reference signal source to the phase frequency detectors in a time division manner. Outputs of the phase frequency detectors are provided, respectively, for multiple disposed charge pump circuits.

Abstract: There is provided a semiconductor device including an oscillation circuit that includes a plurality of capacitors provided on a semiconductor substrate, a conversion circuit that converts an analog signal into a digital signal, and a switch circuit that switches the capacitors on the basis of the digital signal. Further, an oscillation frequency linearly varies with respect to a variation in the analog signal.

Abstract: A phase locked loop circuit includes a voltage controlled oscillator configured to output a clock signal having a predetermined frequency based in a control voltage, a phase frequency detector configured to compare the clock signal with a reference signal to output a first control signal and a second control signal, a charge pump configured to output the control voltage based on the first control signal and the second control signal, a voltage supply including an output terminal connected to an output terminal of the charge pump by a transmission switch, and a leakage remover circuit connected to the transmission switch and configured to remove a leakage current flowing through the transmission switch while the transmission switch is turned-off.

Abstract: An apparatus is disclosed that includes a phase detector circuit for generating a first pulse signal based on first and second input clock signals. A first circuit adjusts the first pulse signal by delaying transmission of a leading edge of the first pulse signal, but not a trailing edge of the first pulse signal. A charge pump circuit charges or discharges a capacitor based on the adjusted first pulse signal, and a voltage controlled oscillator (VCO) circuit generates an output clock signal with a frequency that depends on a voltage on the capacitor.

Abstract: Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.

Abstract: Aspects of the disclosure provide for a circuit comprising a transmitter. In at least some examples, the transmitter is configured to receive an input signal and a loss of signal indication signal. The transmitter is further configured to dynamically modify processing of the input signal based on the loss of signal indication signal. The transmitter modifies processing of the input signal based on the loss of signal indication signal by processing the input signal via a limiting driver signal path to generate an output signal when the loss of signal indication signal has a first value and processing the input signal via a linear driver signal path to generate the output signal when the loss of signal indication signal has a second value.

Abstract: In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

Abstract: A current generating circuit generating a current relevant to a reference voltage. The current generating circuit has a reference clock generating circuit generating a reference clock signal which has a frequency relevant to the reference voltage. The current generating circuit has a phase locked loop circuit generating a calibration clock signal. The phase clocked loop circuit regulates the calibration clock signal so that the phase difference between the calibration clock signal and the reference clock signal is reduced. The current generating circuit has also an output circuit generating an output current according to the phase difference between the calibration clock signal and the reference clock signal.

Abstract: A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.

Abstract: Methods and apparatuses are provided for fractional-N frequency synthesis using a phase-locked loop (PLL). A phase detector (PD) of the PLL determines a phase difference between a clock and a feedback clock (CLKFB). A low-pass loop filter of the PLL detects a control voltage based on the phase difference. A voltage-controlled oscillator (VCO) of the PLL generates a periodic signal based on the control voltage. A sigma-delta modulator (SDM) of the PLL generates a division sequence ratio and a selection control signal based on a frequency command word. A multi-modulus divider (MMDIV) generates a first CLKFB and a second CLKFB based on the division sequence ratio and differential inputs of the periodic signal. The MMDIV outputs one of the first CLKFB and the second CLKFB as the CLKFB to the PD based on the selection control signal.

Abstract: A phase-locked loop is provided. The phase-locked loop includes a first loop including a con-trolled oscillator and a phase detector. The controlled oscillator is configured to generate an oscillation signal. The phase detector is configured to generate first signal indicative of a timing difference between a reference signal and the oscillation signal. Further, the phase-locked-loop includes a second loop configured to generate a second signal indicative of a timing error of the oscillation signal's cycle time, and to generate a correction signal based on the second signal. The phase-locked loop additionally includes a combiner configured to generate a control signal for the controlled oscillator by combining the correction signal and a third signal derived from the first signal.

Abstract: An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (??) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order ?? TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order ?? TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order ?? TDC, wherein the MASH type high-order ?? TDC is configured to measure the phase noise of a device under text (DUT).

Abstract: The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Abstract: Disclosed herein are embodiments of an apparatus and a method for generating a quadrature clock signal. In one aspect, the apparatus includes a first delay circuitry to delay a clock signal according to a first control signal to generate a first delayed clock signal. In one aspect, the apparatus includes a second delay circuitry to delay the clock signal according to a second control signal to generate a second delayed clock signal. In one aspect, the apparatus includes a delay controller forming a first feedback loop with the first delay circuitry, and forming a second feedback loop with the second delay circuitry, where the delay controller determines a difference between the first delayed clock signal and the second delayed clock signal and modifies the first control signal and the second control signal according to the determined difference.

Abstract: A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle greater than 1/r, where r is the frequency ratio.

Abstract: A PLL includes a phase frequency detector (PFD) receiving an input signal and feedback signal, and producing a control signal. A charge pump receives the control signal and produces an initial VCO control. A loop filter generates a fine VCO control and intermediate output based upon the initial VCO control. A coarse control circuit includes an integrator having a first input receiving the intermediate output, a second input, and generating a coarse VCO control, a first switch coupling a reference voltage to the second input, a buffer buffering output of the integrator, and a second switch coupling output of the integrator to the second input of the integrator. A VCO receives the fine VCO control and the coarse VCO control, and generates an output signal having a frequency based thereupon. A feedback path receives the output signal and produces the feedback signal.

Abstract: The present disclosure provides a transmitter and a corresponding method. The method includes: pre-processing a signal to be transmitter, the signals being across a plurality of sub-bands; filtering the signal to generate a universal-filtered orthogonal frequency division multiplexing (UF-OFDM) signal, where two or more sub-bands of the plurality of sub-bands are filtered by a common filter; and transmitting the generated UF-OFDM signal.

Abstract: A semiconductor integrated circuit on a rectangular semiconductor substrate includes timing generation circuits having the same functions of generating control clock signals to corresponding input buffer circuits based on a control reference clock signal, and a parallel processing circuit unit divided into circuit blocks having equal areas and corresponding to the timing generation circuits. Each circuit block includes clock distribution networks corresponding to the control clock signals. The parallel processing circuit unit carries out processes in parallel for each clock distribution network. Each clock distribution network includes the input buffer circuit; a clock buffer circuit connected to the input buffer circuit and placed approximately in a central position of the corresponding circuit block relative to the semiconductor substrate longitudinal direction; and end devices. The clock buffer circuit outputs a control output clock signal to be distributed and supplied to the end devices.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for data synchronization. One of the methods includes that a first terminal device establishes a data channel to a specified carrier through near field communication. The first terminal device obtains an account identifier of a first account and first streaming data corresponding to the first account through the data channel, where the account identifier of the first account and the first streaming data are stored in the specified carrier. The first terminal device determines second streaming data corresponding to a second account associated with the first account, and performs data synchronization between the first account and the second account based on the first streaming data and the second streaming data.

Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signal, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.

Abstract: Systems, circuitries, and methods are described for phase-continuous shifting of a reference clock frequency from fREF to NREF for a DPLL that includes a DCO and a feedback loop that generates a feedback signal. The DPLL generates a local oscillator signal based on an analog reference signal having a reference clock frequency fREF and a digital reference signal having the reference clock frequency fREF. In one example, the method includes receiving a target time and at expiration of a first nonzero interval after the target time, generating a subsequent feedback signal having the target reference clock frequency NfREF; at expiration of a second nonzero interval after the target time, generating a subsequent analog reference signal having the target reference clock frequency NfREF; and at expiration of a third nonzero interval after the target time, generating a subsequent digital reference clock signal having the target reference clock frequency NfREF.

Abstract: Embodiments are disclosed for timing recovery used in conjunction with a phase detector embedded in a receiver of a communication system. An example method includes receiving, via a receiver of a communication system, an input signal. The input signal encodes a plurality of bits in a number of amplitude levels. The method further includes using an analog to digital converter to generate a sampled signal based on the input signal. The method further includes using a first interpolation filter to filter the sampled signal. The method further includes using a second interpolation filter to filter the sampled signal. The method further includes using a first non-linear device to process an output of the first interpolation filter. The method further includes using a second non-linear device to process an output of the second interpolation filter.

Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.

Abstract: A method of operating a relaxation oscillator includes determining a measure of a propagation delay of a detection device of a relaxation oscillator and increasing a charging rate of a capacitor device of the relaxation oscillator for a time duration based on the determined measure of the propagation delay.

Abstract: In a computer system, a phase-locked loop circuit may generate a clock signal using a reference signal. The phase-locked loop circuit may include a programmable divider stage that includes multiple divider stages. When a frequency calibration is initiated on the phase-locked loop circuit, a control circuit may generate a pause signal in response to one or more of the divider stages reaching a particular logic state. The programmable divider stage may hold the one or more of the divider stages in the particular logic state using the pause signal.

Abstract: According to certain aspects, the present embodiments are directed generally to data communication systems, and more particularly to generating multi-phase clocks in a SerDes system. Embodiments provide SerDes components and methods that are capable of generating multiple different sampling frequencies for parallelizing serial data from a single high speed clock. These and other embodiments can be implemented with circuits that are relatively small and low-power as compared to conventional approaches.

Abstract: AFCI and/or GFCI units (10) with onboard trip monitoring and/or wiring error monitoring circuit (100) with an opto-isolator (50) and a controller (60) in electrical communication with the opto-isolator (50). The controller (60) monitors the opto-isolator (50) to identify a TRIP or RESET state of the circuit (100) such as one associated with a receptacle and/or a wiring error of the unit (10), e.g., receptacle.

Abstract: An apparatus and associated method are provided involving one or more registers configured to store a plurality of values including a first value corresponding with a first capacitance, and a second value corresponding with a second capacitance. Further included is a decoder configured to decode the values into corresponding capacitive settings. Also included is one or more capacitive elements in electrical communication with the decoder. Such one or more capacitive elements are configured to exhibit different capacitances, based on the capacitive settings. Also included is control circuitry in electrical communication with the decoder and the one or more registers. Such control circuitry is configured to control a transition of the capacitance of the one or more capacitive elements from the first capacitance to the second capacitance, by creating a plurality of additional values between the first value and the second value for being decoded by the decoder.

Abstract: Described is a digital fractional phase locked loop (DFPLL) with a current mode low pass filter. The DFPLL includes a binary phase frequency detector (BPFD) configured to output a directional pulse based on comparison of a reference clock and a feedback clock, a current mode low pass filter connected to the BPFD, and a current controlled oscillator (CCO) connected to the current mode low pass filter. The current mode low pass filter configured to output a control current based on at least the directional pulse when a current steering switch directly controlled by the directional pulse switches to the CCO. The CCO configured to adjust a frequency of the CCO based on the control current to generate an output clock. The feedback clock based on the output clock and the reference clock aligned with the feedback clock by adjusting the frequency of the output clock until frequency and phase lock.

Abstract: Aspects of present disclosure of multiplying delay lock loop (MDLL) circuitry and communication devices are generally described herein. The MDLL circuitry may comprise a multiplexer and a ring oscillator. The ring oscillator may comprise a cascade of delay elements. The multiplexer may receive a reference clock signal and may receive a ring oscillator output signal from a final delay element of the cascade of delay elements. The multiplexer may select, as a ring oscillator input signal, either the reference clock signal or the ring oscillator output signal. The ring oscillator may determine a jitter estimate based at least partly on a comparison between output signals of two particular delay elements of the cascade. The ring oscillator may compensate delay responses of the delay elements of the cascade based at least partly on the jitter estimate.

Abstract: In accordance with an embodiment, a method of operating an RF system includes filtering a wideband RF signal using an adjustable center frequency bandpass filter to produce a filtered RF signal; amplifying the filtered RF signal to produce an amplified RF signal; and band stop filtering the amplified RF signal to produce a band stopped RF signal.

Abstract: A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibration signal based on the digital phase error signal.

Abstract: In an embodiment, an integrated circuit includes: a switched capacitor coupled between a supply voltage node and a divider node, where a thermistor external to the integrated circuit is to couple to the divider node; an analog-to-digital converter (ADC) coupled to the divider node to receive a voltage at the divider node and generate a digital value based thereon; and a controller coupled to the ADC to determine a temperature associated with the thermistor based at least in part on the digital value.

Abstract: Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.

Abstract: A phase detection circuit is configured to receive an input clock signal and a reference clock signal. The phase detection circuit is configured to generate a divided clock signal from the reference clock signal. The phase detection circuit is configured to generate a phase detection signal after comparing the phase of the input clock signal with the divided clock signal.

Abstract: Examples provide a system, a phase locked loop, an apparatus, a method and a computer program for generating a clock signal, a transceiver, and a mobile terminal. A system comprises clock generator (10) configured to output provide a clock signal having a predefined average clock rate, a reference signal generator (14) configured to provide a reference signal, and a clock divider (16) configured to divide the reference signal to generate the clock signal, wherein a time difference between a clock cycles and a subsequent clock cycle of the clock signal is irregular.

Abstract: A locking detecting circuit of a Phase Locked Loop (PLL) circuit includes an output signal counter performing an output signal counting operation of counting an output signal of the PLL circuit during a counting time period, a period determiner performing a period changing operation of decreasing the counting time period until a difference between a current period counting value and a preceding period counting value becomes smaller than a threshold value, and a locking detector detecting a locking of the PLL circuit when the difference between the current period counting value and the preceding period counting value becomes smaller than the threshold value.

Abstract: A divider and buffer circuit uses a receive command to initiate a reset of buffer circuitry prior to restarting to avoid a metastable state. For example, the divider and buffer circuit includes a first buffer circuit, a second buffer circuit, and a reset circuit. The reset circuit receives a command and provide a pulse on a reset signal in response to the command. In response to the reset pulse, the first buffer circuit provides a first divided clock signal having a first logical value based on respective logical values of received complementary clock signals and the second buffer circuit provides a second divided clock signal having a second logical value based on the respective logical values of the complementary clock signals. The command is a CAS SYNC command, in some examples.

Abstract: A feedback divider in a mixed-signal circuit is modulated by a frequency control word controlling a delta-sigma modulator. An accumulated quantization error from the delta-sigma modulator is compared to a residual error in the circuit by a Least-Mean Square (LMS) correlator for gain calibration to adjust for linear errors. Upper bits of the accumulated quantization error access a lookup table to find two outputs of the compensation function that are interpolated between using lower bits of the accumulated quantization error. The interpolated result is an adjustment subtracted from the loop to compensate for non-linear errors. A set of orthogonal kernels is generated from the accumulated quantization error and calibrated using another LMS correlator and inverse transformed to generate updates to the non-linear compensation function in the lookup table. The kernels can be Walsh Hadamard (WH) and the inverse transformer an inverse WH transformer.

Abstract: A non-linear spread spectrum clock generator using a linear combination may include a phase locked loop configured to receive a reference signal and generate an output signal according to the reference signal and a feedback signal that compensates for the output signal. The phase locked loop may include a divider configured to generate the feedback signal by dividing the output signal by a divisional ratio. The non-linear spread spectrum clock generator may include a non-linear profile generator configured to generate a non-linear signal by selectively outputting selected ones of a plurality of signals according to the absolute magnitudes of the signals and a delta-sigma modulator configured to receive the outputted linear ramp function and to change the divisional ratio. The signals may vary according to different linear ramp functions. The different ramp functions may include different slopes and initiation time values.

Abstract: Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.

Abstract: Implementations provide a phase locked loop (PLL) device that includes: a phase and frequency detector (PFD) and charge pump (CP) portion; a low pass filter; a voltage controlled oscillator (VCO) driven by the low pass filter to generate a VCO clock signal, multiple divider configured to receive the VCO clock signal and frequency divide the VCO clock signal in stages to generate a series statically divided VCO clock signals and a dynamically divided VCO clock signal; a feedback portion including a first component configured to receive the dynamically divided VCO clock signal and generate indicator signals; and a second component configured to multiplex from the indicator signals to generate the feedback clock signal set for the PFD and CP portion; and a master phase/frequency control engine configured to assert a division control over at least one divider and a multiplex control over the multiplex network.

Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: An adaptive feedback method for use in a memory device is provided. The memory device includes a first input-receiver circuit and a plurality of second input-receiver circuits. The method includes the steps of: providing a clock signal and an inverted clock signal to the first input-receiver circuit; generating an enable control signal by the first input-receiver circuit to control a first feedback path in the first input-receiver circuit; in response to the frequency of the clock signal and the inverted clock signal being higher than or equal to a predetermined frequency, activating the first feedback path in the first input-receiver circuit according to the enable control signal; and in response to the frequency of the clock signal and the inverted clock signal being lower than the predetermined frequency, deactivating the first feedback path in the first input-receiver circuit according to the enable control signal.

Abstract: A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Abstract: An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

Abstract: Provided are systems and methods for generating program code for an integrated circuit, where instructions in the code synchronize computation engines that support non-blocking instructions. In various examples, a computing device can receiving an input data set including operations to be performed by an integrated circuit device and dependencies between the operations. The input data set can include a non-blocking instruction, and an operation that requires that the non-blocking instruction be completed. The computing device can generate instructions for performing the operation including a particular instruction to wait for a value to be set in a register of the integrated circuit device. The computing device can further generate program code including the non-blocking instruction and the instructions for performing the operation, wherein the non-blocking instruction is configured to set the value in the register.

Abstract: An apparatus includes a slicer circuit, a frequency acquisition circuit, a phase acquisition circuit and an oscillator circuit. The slicer circuit may be configured to (i) generate an output signal by slicing a data signal in response to a clock signal and (ii) generate a crossing signal in response to the data signal and the clock signal. The frequency acquisition circuit may be configured to generate a first control signal and a second control signal in response to the data signal and the clock signal. The phase acquisition circuit may be configured to generate a third control signal in response to the first control signal and the data crossing signal. The oscillator circuit may be configured to generate the clock signal in response to the second control signal and the third control signal. The second control signal may shift an adjustable frequency range of the clock signal.

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.