Abstract: A calibration system operates to calibrate or correct a digital-to-time converter (DTC) that comprises a detector component and a distortion correction component. The DTC can receive one or more signals and a digital code to generate a modulation signal by controlling an offset of the one or more signals based on the digital code. The detector component can comprise a TDC or another DTC that operates to measure a dynamic behavior in response to detecting nonlinearities of the modulation signal. The distortion correction component can generate a set of distortion data that removes the dynamic behavior from an output of the DTC based on the measurement.

Abstract: A structure is provided for sensing an analyte in an environment. The structure may include a ring oscillator on a semiconductor substrate, the ring oscillator includes an AND gate, an odd number of inverters, and a carbon device connected in series, the carbon device is exposed to an environment such that a frequency of the ring oscillator changes when the carbon device is exposed to the analyte in the environment.

Abstract: A radio frequency (RF) signal can be produced with an RF frequency that is responsive to a frequency reference (FREF) clock. An inductive-capacitive (LC) tank oscillator circuit can generate the RF signal. A digital to time converter (DTC) circuit can operate, for a first edge of the FREF clock, in a baseline mode that has a first delay, and for a subsequent edge of the FREF clock, in a delay mode that introduces a second delay value to the FREF clock. A controller circuit can enable the LC-tank oscillator circuit in response to a first edge of the FREF clock and to set or increase the second delay value of the delay mode as a function of the frequency of the RF signal. A phase detector circuit can detect, for the subsequent edge of the FREF clock, a phase difference between the FREF clock and the RF signal.

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract: An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.

Abstract: The invention relates to a method for calibrating a multiphase, in particular three-phase, inverter (1) having a respective switching element (T1, T2, T3) on the high-voltage side and a respective switching element (T4, T5, T6) on the low-voltage side for each of the phases thereof as well as a respective current sensor for at least some of the phases (I, II, III). The following steps are proposed: (f) switching off all switching elements (T1-T6), (g) switching on a switching element (T1) on the high-voltage side for a first phase (I) and a switching element (T5) on the low-voltage side for a second phase (II), (h) measuring the currents flowing through the first phase (I) and the second phase (II), (i) forming an average value from the measured currents, and (j) calibrating the inverter (1) on the basis of the formed average value. The invention also relates to an apparatus, a computer program and a computer program product.

Abstract: A modulated signal is demodulated to obtain a modulation signal. The modulated signal is contained within an input signal. A periodic time segment sequence is defined having a plurality of ordered time segments. Signal values are acquired, from the input signal, during each ordered time segment. Signal values acquired during each ordered time segment are combined with signal values acquired during the same ordered time segment over multiple periods of the periodic time segment sequence. A local clock is generating. The modulated signal is demodulated by weighting the combined signal values by the local clock to obtain the modulation signal. the modulation signal is low-pass filtered to obtain a control signal. The generation of the local clock is controlled with the control signal.

Abstract: A semiconductor device includes a data input/output circuit that has an ODT function and a DLL circuit that generates an internal clock for determining an operation timing of the data input/output circuit. The DLL circuit has a first mode for controlling a phase of the internal clock in a precise manner and a second mode for operating with low power consumption. When the data input/output circuit does not perform an ODT operation, the DLL circuit operates in the first mode, and when the data input/output circuit performs the ODT operation, the DLL circuit operates in the second mode. In this manner, the operation mode of the DLL circuit is switched over depending on the ODT operation, so that the power consumption in the ODT operation in which strict phase control is not required can be reduced.

Abstract: Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.

Abstract: Embodiments of the invention disclose a signal processing device and a signal processing method and a device and a method for signal processing. The signal processing device includes a sampling module, a first segmentation module, a second segmentation module, and a detection module. The sampling module samples an input signal to generate a sample signal. The first segmentation module calculates a first segment value according to the sample signal during a first time interval. The second segmentation module calculates a second segment value according to the sample signal during a second time interval different in length from the first time interval. The detection module generates a detection signal according to the determination of whether the first segment value lies out of a first range, and whether the second segment value lies out of a second range.

Abstract: A PLL-VCO based integrated circuit aging monitor, including: a control circuit, a monitoring circuit, and an output circuit. The monitoring circuit includes a reference circuit, an aging generation circuit, and a comparison circuit. The reference circuit is a PLL circuit insensitive to a parameter error caused by the aging of circuit. The aging generation circuit is a VCO circuit sensitive to the parameter error. The control circuit is connected to the PLL circuit, the VCO circuit, the comparison circuit, and the output circuit. The output end of the PLL circuit is connected to a first input end of the comparison circuit, and the output end of the VCO circuit is connected to a second input end of the comparison circuit. The output end of the comparison circuit is connected to the input end of the output circuit. The input end of the PLL circuit inputs a reference clock signal.

Abstract: A fractional N-frequency divider having a reduced fractional spurious output signal, which utilizes a multi-modulus frequency divider and an accumulator to generate a calibration-timing window that is used to calibrate two oscillator circuits and a phase compensation circuit. The calibrated phase compensation circuit is then used to mitigate the fractional spurs in the output signal of the fractional N-frequency divider. The fractional N-frequency divider may be implemented into a fractional N-frequency synthesizer.

Abstract: Settling time may be reduced or eliminated for a phase-locked loop (ADPLL). An oscillator model provides proper settings that are applied to compensate both the frequency response and the phase response. A hardware device may include a Digital Controlled Oscillator (DCO); and a DCO model device with a processor, wherein the processor is configured to calculate a frequency for the DCO by searching for the frequency based upon operational parameters of the DCO, compare the calculated frequency to a measured frequency, and compensate, based upon the comparison, an ADPLL to decrease a settling time.

Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency. The integrated circuit includes a voltage regulator that provides a power-supply voltage to the second DCO. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage. Furthermore, the AFLL adjusts a gain of the selected DCO in the first sub-frequency-locked loop based on the instantaneous value of the power-supply voltage and the average power-supply voltage. In this way, an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced.

Abstract: A frequency synthesizer includes a digitally controlled oscillator, a sigma-delta modulation circuit and a controller. The digitally controlled oscillator is arranged to generate an oscillating clock. The sigma-delta modulation circuit is arranged to generate an SDM input to the digitally controlled oscillator. The controller is arranged to adjust an operating frequency of the SDM circuit in response to a transmit power level of a transmitter using the oscillating clock.

Abstract: An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.

Abstract: A re-circulating time-to-digital converter (TDC) can include a triggered reference ring oscillator (TRRO) and a delay module. The triggered reference ring oscillator can, when triggered by a reference signal edge, generate a periodic ring oscillator signal with a ring oscillator period that is a selected ratio of a voltage-controlled oscillator (VCO) period. The delay module can store, in a plurality of latches, samples of a VCO signal docked by the periodic ring oscillator signal. Each latch can generate an output of the sample, and each latch output can represent a time difference polarity between VCO signal and TRRO signal. In another example, the re-circulating TDC can include the triggered reference ring oscillator, a digital frequency lock module, and a TDC post-process module. The digital frequency lock module can generate a ring oscillator control signal, which sets the ring oscillator period for the triggered reference ring oscillator.

Abstract: A system for assigning a characterization and calibrating a parameter is disclosed. The system includes a frequency measurement circuit and a finite state machine. The frequency measurement circuit is configured to measure frequencies of an oscillatory signal and to generate a measurement signal including measured frequencies. The finite state machine is configured to control measurements by the frequency measurement circuit, to assign a characterization to a parameter based on the measurement signal, and to generate a calibration signal based on the characterized parameter.

Abstract: A light emitting diode (LED) backlight system and a driving apparatus and a driving method thereof are provided. The driving apparatus is suitable for an LED backlight system with N LED strings, where N is a positive integer greater than 1, and which includes an LED driver and a switching unit. The LED driver is configured to receive a dimming signal and time-divisionally generate N control signals in response to a counting clock and an enabling time and a period time both related to the dimming signal. The switching unit is coupled to the LED driver and the N LED strings, and is configured to respectively control an on-off time ratio of a current flowing through each of the LED strings in response to the N control signals.

Abstract: A DDS achieved in size and cost reductions by removing a ROM for storing a table and the like and suppressing an operation amount is provided. A DDS includes an NCO, a DAC, and a BPF. The NCO outputs a sawtooth wave. The DAC converts either one of the sawtooth wave outputted from the NCO and a triangle wave signal converted by a waveform converting circuit based on the sawtooth wave, from a digital signal into an analog signal. The BPF receives the signal converted into the analog signal by the DAC and extracts a sine wave at a predetermined frequency from the inputted signal, by allowing a signal at a frequency within a fixed range to pass therethrough.

Abstract: Exemplary embodiments of the present invention relate to an internal jitter tolerance tester. The internal jitter tolerance tester may include a digital loop filter consisting of a cyclic accumulator which accumulates a phase detector's output, a gain multiplier, an internal accumulated jitter generator (or an internal sinusoid jitter generator), and a phase rotator (or DCO) controller. The internal accumulated jitter generator may include a PRBS generator, a digital loop filter, an accumulator, and a gain controller. The accumulated jitter generator also may be replaced with the internal sinusoid jitter generator. The internal sinusoid jitter generator may include a counter, a sinusoid jitter profile lookup table, and a gain controller.

Abstract: An apparatus and method is provided to enable precision and fast laser frequency tuning. For instance, a fast tunable slave laser may be dynamically offset-locked to a reference laser line using an optical phase-locked loop. The slave laser is heterodyned against a reference laser line to generate a beatnote that is subsequently frequency divided. The phase difference between the divided beatnote and a reference signal may be detected to generate an error signal proportional to the phase difference. The error signal is converted into appropriate feedback signals to phase lock the divided beatnote to the reference signal. The slave laser frequency target may be rapidly changed based on a combination of a dynamically changing frequency of the reference signal, the frequency dividing factor, and an effective polarity of the error signal. Feed-forward signals may be generated to accelerate the slave laser frequency switching through laser tuning ports.

Abstract: A time-to-digital converter (TDC) that has high resolution, excellent linearity, and a widerange. The TDC includes a first oscillator unit that generates and outputs a pair of first oscillation signals based on a pair of predetermined clock signals that have a predetermined phase difference, a second oscillator unit that generates and outputs a second oscillation signal that have a predetermined frequency based on the pair of first oscillation signals outputted from the first oscillator unit, and a quantizer that calculates a quantized value based on a number of edges of the second oscillation signal outputted from the second oscillator unit.

Abstract: A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.

Abstract: A hybrid analog/digital control approach for a digitally controlled oscillator augments a digital control path with an analog control path that acts to center the digital control path control signal within its range. The digital control path controls a first group of varactors within an oscillator tank circuit using a digital filter and a delta sigma modulator, which generates a dithered control signal for at least one of the first group of varactors. The analog control path controls a second group of varactors in the tank circuit but actively tunes only one varactor at a time. The analog control path performs relatively low bandwidth centering of the digital control signal resulting in negligible impact on PLL bandwidth, stability, and noise performance. Instead, the digital control path dominates in setting the PLL dynamic and noise behavior, and has reduced range requirements due to the centering action.

Abstract: A phase-locked loop (PLL) includes a time to voltage converter to convert a phase error between a reference signal and a feedback signal of the PLL to one or more voltage signals. An oscillator-based analog to digital converter (ADC) receives the one or more voltage signals and controls one or more oscillators according to the voltages. The oscillator-based ADC determines a digital value corresponding to the phase error based on the frequencies of the one or more oscillators.

Abstract: A method of generating a correlation function for a CBOC(6,1,1/11) signal according to the present invention includes generating a delayed signal delayed based on a phase delay, with respect to a signal pulse train of a CBOC(6,1,1/11)-modulated received signal, generating first to twelfth partial correlation functions by performing an autocorrelation operation of the received signal and the delayed signal with respect to a total time, generating a basic intermediate correlation function by performing an elimination operation on sixth and seventh partial correlation functions, acquiring first to fifth and eighth to twelfth additional intermediate correlation functions by performing an elimination operation on each of partial correlation functions, excluding the sixth and seventh partial correlation functions from the first to twelfth partial correlation functions, and a basic intermediate correlation function, and acquiring the main correlation function by simply summing the basic intermediate correlation func

Abstract: Disclosed herein is a circuit for controlling a variation in the frequency of a clock signal for blocking an unwanted variation in the frequency of the clock signal. When a frequency variation out of a set range is generated in a reference clock signal in the state in which the phases of the reference clock signal and a feedback clock signal have been locked, a control voltage for generating the feedback clock signal remains constant so that an abrupt variation generated in the frequency of the feedback clock signal is blocked.

Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.

Abstract: A clock generation circuit of a semiconductor apparatus includes a first clock generation unit configured to output a first signal which swings between a level of a power supply voltage and a level of a set voltage; a second clock generation unit configured to output a second signal which swings between the level of the set voltage and a level of a ground voltage; and a regulator configured to supply the set voltage to the first clock generation unit and the second clock generation unit.

Abstract: Disclosed are a phase locked loop (PLL) of a digital scheme and a method thereof. More specifically, disclosed are a digital phase locked loop having a time-to-digital converter (TDC), a digital loop filter (DLF), and a digitally controlled oscillator (DCO), and that is designed to have a constant jitter characteristic at all times even though an operating condition of a circuit varies according to a process, voltage, temperature (PVT) change, and a method thereof.

Abstract: A phase-locked loop circuit, a phase converter module thereof and a phase-locked controlling method are disclosed herein. The phase converter module is suitable for a phase-locked loop circuit including a digitally-controlled oscillator (DCO) for generating an oscillator output signal and a divider for converting the oscillator output signal into N-phased oscillator output signals. The phase converter module includes a period extender, a phase finder and a time-to-digital converter. The period extender is configured for extending the N-phased oscillator output signals into M*N-phased oscillator output signals corresponding to M oscillation period of the digitally-controlled oscillator. The phase finder is configured for sampling the oscillator output signal with the M*N-phased oscillator output signals to calculate an estimated value of the fractional phase part. The time-to-digital converter is configured to calculate a precise value of the fractional phase part within one sub-period.

Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.

Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.

Abstract: This disclosure describes techniques for generating signals that have relatively steep frequency profiles with a phase-locked loop (PLL) circuit architecture. In some examples, the techniques for generating signals that have relatively steep frequency profiles may include modulating an amplitude of a forward path signal in a PLL circuit at a location in a forward circuit path of the PLL circuit based on a control signal. The control signal may have an amplitude profile that is determined based on a target frequency profile to be generated by the PLL circuit. Modulating the forward circuit path of the PLL circuit with a signal that is determined based on a target frequency profile may allow a PLL-based frequency synthesizer to generate signals with relatively steep frequency profiles while still maintaining acceptable levels of phase noise.

Abstract: There are provided an accumulator-type fractional N-PLL synthesizer for suppressing the fractional spurious caused by periodically switching a frequency division number of a fractional frequency divider, and a control method thereof. In an accumulator-type fractional N-PLL synthesizer (100), a pulse signal proportional to a fractional phase error occurring between a reference signal and an output signal of a fractional divider (112) for feeding back an output of a VCO (115) of an output stage to a preceding stage is generated using an error signal from an accumulator (120). Through the use of the pulse signal, pulse widths of a UP signal and a DN signal output from a phase detector (140) are controlled so as to reduce a fractional phase error occurring between the UP signal and the DN signal. Thus, the fractional spurious caused by periodically switching the frequency division number of the fractional divider (112) is suppressed.

Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.

Abstract: A loop filter for a phase locked loop (PLL) having fast tuning capability while limiting phase noise. The filter includes a fine tune input port to receive a fine tune signal from the phase detector and a coarse tune input port to receive a coarse tune signal from the coarse tuner. The external coarse tuner provides the majority of the voltage slew on the loop filter while a fine tune control, thus reducing tune time. in one embodiment, the loop filter includes a voltage divider to limit the effective tuning sensitivity and thus control noise induced on a voltage-controlled oscillator from the loop filter. An elliptical filter may be employed to attenuate fractional spurs within the filter output signal.

Abstract: Embodiments are described for a method of continuously measuring the ratio of frequencies between the transmit and receive clock domains of a heterochronous system using an array of digital frequency measurement circuits that provide overlapping frequency and detection interval measurements within single counter periods required for a single frequency measurement circuit to complete a frequency measurement. Embodiments may be used in a predictive synchronizer to provide low latency, continuous frequency measurements for system-on-chip (SOC) devices that employ frequency drift or ramping to reduce power consumption and overheating conditions.

Abstract: A circuit includes a phase locked loop and a logic IC. The phase locked loop is coupled to the logic IC. The logic IC is configured for generating an adaptive residue according to a first parameter and a second parameter. The phase locked loop is configured for providing the first parameter and the second parameter, and the phase locked loop generates an oscillator signal based on the adaptive residue.

Abstract: A system and method are provided for frequency multiplication jitter correction. The method accepts an analog reference signal having a first frequency, and using the analog reference signal, derives a system clock signal having a second frequency, greater than the first frequency. A PLL using a voltage controlled oscillator (VCO) is one example of a frequency multiplier. The method samples the amplitude of the analog reference signal using the system clock signal and converts the sampled analog reference signal into a digitized reference signal. In response to comparing the digitized reference signal to an ideal digitized reference signal, the phase error correction for the system clock signal is derived. The phase error correction at a first instance of time can be applied to the digitized data signal, previously converted from an analog data signal sampled at a first instance of time with the system clock signal.

Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.

Abstract: A PLL includes an oscillator, multiple time-to-digital converters (TDCs) and a system for the remaining functionality. The TDCs measure the oscillator's phase against respective multiple reference clocks. The system compares the respective measured phases with respective desired phases to obtain phase error signals. One is selected to close the loop. The others are monitored and adjusted when not equal to zero. When a new reference clock must be used, the loop is changed from including the old phase error signal to the new. The old phase error was zero because the loop was in lock, the new phase error is zero because it was monitored and adjusted. Therefore, upon switching the loop from the old to the new phase error signal, the loop remains locked and switching is hitless.

Abstract: A frequency measuring and control apparatus includes a plurality of synchronized oscillators integrated in parallel into one programmable logic device.

Abstract: A method and an arrangement for generating a clock signal by a phase locked loop in which the time for adjusting to a prescribed frequency and phase of a clock signal is reduced by virtue of the fact that a plurality of selection signals respectively shifted by a time difference delta t are generated from the divided clock signal. A comparison signal (capture) is generated under control by an edge of the reference clock and a comparison is started in the case of which what is selected is that selection signal shifted by delta t which exhibits with its edge the least possible time deviation from the edge of the comparison signal, and the selected selection signal is output.

Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.

Abstract: A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.

Abstract: A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency.

Abstract: A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.

Abstract: To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.