Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: A phase detector, which forms a semiconductor device, detects a phase difference between a reference signal and a feedback signal obtained by feeding back an output signal of an oscillator, and generates a phase difference value indicating a value in accordance with the phase difference. An amplifier amplifies the phase difference value at a gain determined in accordance with a control signal from outside the device. A filter smoothes an output value of the amplifier. The oscillator controls a frequency of the output signal in accordance with an output value of the filter.

Abstract: A Phase-to-Digital Converter (PDC) within a Phase-Locked Loop (PLL) includes a PDC portion and a PDC decoder portion. The PDC portion receives a reference signal FR and a feedback signal FV and generates therefrom a stream of multi-bit digital values. Each multi-bit value is indicative of a time difference between an edge of FR and a corresponding edge of FV. The PDC decoder portion includes sequential logic elements that are clocked to capture the multi-bit digital values. In order to prevent metastability, the timing of when the sequential logic elements are clocked to capture the multi-bit digital values is adjusted as a function of the phase difference between FR and FV. In one specific example, if the phase difference is small then the falling edge of FR is used to clock the sequential logic elements, whereas if the phase difference is large then the rising edge of FR is used.

Abstract: One embodiment relates to a lock detection circuit. The lock detection circuit includes at least a dither detection circuit and a lock filter. The dither detection circuit maintains a bi-directional count based on early and late signals from a sampler circuit and asserts a non-lock signal if the bi-directional count reaches either a positive non-lock assertion threshold or a negative non-lock assertion threshold. The lock filter increments a lock filter count for each sample and outputs a lock-initiated signal when the lock filter count reaches a pre-set maximum value. The maximum value of the lock filter count is greater than the non-lock assertion thresholds. Other embodiments and features are also disclosed.

Abstract: A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock haying a frequency depending on an input code; phase comparison section configured to output a phase differences signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.

Abstract: Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.

Abstract: A frequency synthesizer includes a frequency generator configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent code. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent code in response to the temperature measurement signal and a plurality of clocks having unequal frequencies. The control circuit can include a cascaded arrangement of an oversampled data converter and a digital filter, which are sequentially responsive to first and second ones of the plurality of clocks during generation of the periodic output signal by the frequency generator.

Abstract: In an integrated circuit that provides a clock signal, an asymmetric frequency-locked loop (AFLL) includes a first digitally controlled oscillator (DCO) that outputs a first signal having a first fundamental frequency, and a second DCO that outputs a second signal having a second fundamental frequency that is less than the first fundamental frequency. Moreover, the AFLL includes control logic that selects one of the first DCO and the second DCO based on an instantaneous value of a power-supply voltage and an average power-supply voltage so that an impact of power-supply voltage variations on a time-critical path in the integrated circuit is reduced. For example, the control logic may select the first DCO if the instantaneous value of the power-supply voltage is greater than the average power-supply voltage; otherwise, the control logic may select the second DCO.

Abstract: A Micro Electrical Mechanical System (MEMS) oscillator supplies a MEMS clock signal to a digital locked loop that generates an output clock signal having a frequency that corresponds to a desired frequency ratio between the MEMS oscillator output signal and the digital locked loop output signal. The frequency ratio may be determined, at least in part, as a function of temperature.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.

Abstract: A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Abstract: LC tank and ring-based VCOs are disclosed that each include a differential pair of transistors for steering a tail current generated by a current source responsive to a bias voltage. A biasing circuit generates the bias voltage such that a transconductance for the transistors in the differential pairs is inversely proportional to a resistance.

Abstract: An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone.

Abstract: A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit.

Abstract: A frequency synthesizer is configured to generate a periodic output signal in response to a periodic input signal and a temperature-dependent frequency adjusting control signal. A temperature sensor is provided, which is configured to generate a temperature measurement signal in response to detecting a temperature of at least a portion of the frequency synthesizer. A control circuit is provided, which is configured to generate the temperature-dependent frequency adjusting control signal in response to the temperature measurement signal. This control circuit includes a cascaded arrangement of an oversampled data converter and a multi-stage digital filter, which is configured to generate a plurality of codes from respective ones of the digital filter stages, and a selection circuit, which is configured to use at least first and second ones of the plurality of codes in sequence during first and second consecutive time intervals to generate the temperature-dependent frequency adjusting control signal.

Abstract: A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock.

Abstract: The present invention relates to a method and device for phase-frequency detection in a phase-lock loop circuit. The method comprises receiving compare edge of a reference clock signal and compare edge of a feedback clock signal, maintaining a phase/frequency detector, PFD, state machine with three PFD states, UP, DOWN, and IDLE, based on the received compare edges of the reference and feedback clock signals, recording current and previous time the state machine stays in UP or DOWN states, generating an UP or DOWN signal based on transition of PFD states and the comparison between recorded current time and recorded previous time; and outputting a digital control signal to a feedback frequency control device based on the UP or DOWN signal. A device and system is arranged to execute the method according to the present invention.

Abstract: Embodiments of the present disclosure provide methods, systems, and apparatuses related to an open-loop digital delay-locked loop having a drift sensor. Other embodiments may be described and claimed.

Abstract: A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.

Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.

Abstract: A semiconductor device includes: a frequency setting information storage unit that stores sets of frequency information indicating setting of a frequency supplied by an oscillation unit and frequency identification information identifying the frequency information and outputs one of a plurality of pieces of the frequency information to the oscillation unit based on frequency identification information inputted thereinto; a speed setting information storage unit that stores speed identification information indicating a speed of the semiconductor device and frequency identification information corresponding to the speed identification information; a frequency identification information count unit that holds a value of the frequency identification information inputted into the frequency setting information storage unit; and a control unit that causes the frequency identification information count unit to increment or decrement the held value of the frequency identification information to approach a value of the

Abstract: Disclosed is an oscillation circuit. The oscillation circuit supplies predetermined oscillation signals to a generating circuit having a divider, a phase comparator, and a generator. A clock signal generating section generates clock signals in a cycle based on the comparison results from the phase comparator. A clock signal mask section masks a part of the clock signals generated by the clock signal generating section to generate the predetermined oscillation signals and supplies the predetermined oscillation signals to the divider. The clock signal mask section masks a part of the clock signals such that the cycle of sampling signals generated by the generator is the same as a predetermined cycle which is the cycle of a clock for use in generating image signals.

Abstract: A stepper motor driver system includes: a digital signal controller configured to digitally synthesize synthesized analog voltage signals that will induce a desired velocity of a stepper motor when applied to a pair of stepper motor windings; and voltage amplifiers, communicatively coupled to the digital signal controller, configured to amplify the synthesized analog voltage signals to produce amplified analog voltage signals and to output the amplified analog voltage signals; where the digital signal controller is configured to synthesize the analog voltage signals by affecting at least one of a phase or an amplitude of each of the analog voltage signals as a function of the desired velocity of the stepper motor.

Abstract: Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.

Abstract: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a reference clock signal. The method includes generating the output clock signal during an absence of the reference clock signal and based, at least in part, on an average digital control word indicating an average value of a number of samples of the digital control value during the presence of the reference clock signal, the number of samples preceding the absence of the reference clock signal by a delay period. The number of samples is selected from a plurality of numbers of samples and the delay period is selected from a plurality of delay periods.

Abstract: A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit.

Abstract: An electronic circuit operating on a first clock signal includes a clock frequency overshoot detection circuit for detecting frequency overshoots in the first clock signal. The clock frequency overshoot detection circuit includes a shift register having an even number plurality of flip-flops. The flip-flops toggle to generate output bit patterns indicative of a frequency overshoot condition. A comparator connected to the shift register generates a comparison signal on detecting the frequency overshoot condition. A latch circuit connected to the comparator generates a frequency overshoot indication signal and the electronic circuit is shifted to a second (or safe) clock signal until the frequency of the first clock signal is rectified.

Abstract: Embodiments of the invention relate to apparatus and method for reducing electromagnetic interference (EMI) and radio frequency interference (RFI) in computer systems via a chaotic frequency modulation. In one embodiment, an apparatus comprises a first cell comprising a chaotic signal generator to generate a chaotic signal and a phase-locked loop (PLL) to generate a modulated output signal based at least on an un-modulated reference signal and the chaotic signal.

Abstract: A phase difference detecting circuit 3 includes a sync detecting circuit 21 for detecting establishment of phase sync from phase difference signals D and U generated by a D-type flip-flop 13, and a switch 22 for supplying, unless the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage Vt1 generated by the current-output-matching loop filter 15 to a voltage-controlled oscillator 4, and for supplying, when the sync detecting circuit 21 detects the establishment of the phase sync, the control voltage Vt2 generated by the voltage-output-matching loop filter 20 to the voltage-controlled oscillator 4.

Abstract: System and method providing multiple circuit paths to control characteristics of periodic signals. In one embodiment first and second detector signals are indicative of a phase and frequency differences between the output signal and a reference signal. A first input signal based on the first detector signal adjusts the phase difference. A first control signal based on the second detector signal has frequency content in high and low frequency ranges. A second input signal based on the control signal reduces the frequency difference. A second control signal based on the second detector signal has relatively low frequency content in the high frequency range. A third input signal based on the second control signal reduces the frequency difference.

Abstract: A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module.

Abstract: Circuits and methods for controlling a VCO output signal. A filtered version of an integral path input signal controls current flow through a proportional path. An exemplary embodiment generates an integral path input signal from a digital to analog converter. First integral path circuitry includes a first transistor device and a low pass filter which provides a filtered version of the integral path input signal to a first transistor device to control conduction through the device, providing a first VCO input signal for frequency adjustment of the output signal. Proportional path switching circuitry between a supply terminal and VCO input terminal includes a second transistor device which receives the first VCO input signals to control conduction between the supply terminal and the first VCO input terminal to provide a second signal for adjustment of the phase of the VCO output signal relative to the reference signal.

Abstract: A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, an indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device.

Abstract: A phase locked loop that includes a signal generator arranged to output a feedback signal, a first phase detector arranged to detect a phase difference between the feedback signal and a reference signal and to output a first phase detect signal in dependence on that detection, a second phase detector arranged to detect a phase difference between the feedback signal and a delayed version of the reference signal or between the reference signal and a delayed version of the feedback signal and to output a second phase detect signal in dependence on that detection, and an adjustor. The adjustor is arranged to determine which of the first and second phase detect signals commutes first and to alter the frequency of the feedback signal in dependence on the result of the determination.

Abstract: A semiconductor device includes: an internal clock signal generation unit configured to receive an external clock signal and to generate an internal clock signal in response to a control signal; and a monitoring unit configured to monitor environmental elements reflected in a circuit response to the control signal.

Abstract: In some embodiments, a digital PLL (DPLL) is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error.

Abstract: A reconstruction circuit for the pixel clock in digital display units receiving analog display data uses a multi-phase reference clock and an all digital PLL for clock generation and synchronization to an external sync signal. A phase/frequency detector in the digital PLL uses a multi-phase reference clock to achieve a high resolution of the phase error. The digital PLL control algorithm can be implemented with a single loop and can achieved arbitrary large, externally controlled, phase difference between the generated pixel clock and the input sync signal.

Abstract: The present invention provides a full-digital clock duty cycle correction circuit and a method thereof. The circuit comprises a sampling unit, a duty cycle correcting module, and a phase-lock module. The duty cycle correcting module produces a first clock signal according to an input clock signal. The phase-lock module produces a second clock signal according to the first clock signal and is used for aligning the positive edges of the clock signals. The duty cycle correcting module adjusts the pulse width of the first clock signal according to the clock signals. In addition, after the pulse width is adjusted, the positive edges of the clock signals are re-aligned. When the pulse width is not equal to zero, the pulse width is re-adjusted and the positive edges are re-aligned until the pulse widths of the clock signals are identical. Finally, the second clock signal is outputted and thus producing a clock signal having 50% duty cycle.

Abstract: Disclosed herein is a digital re-sampling apparatus. The digital re-sampling apparatus includes a sample buffer, a sample buffer control unit, a filter bank, a first delay bank, a fractional delay constant table, a combiner bank, and a second delay bank. The sample buffer temporarily stores an input sample in synchronization with an input sampling frequency. The sample buffer control unit controls writing and reading operations. The filter bank includes a number of digital filters equal to the number of stages, and filters the input sample. The first delay bank differentially delays a filter output value. The fractional delay constant table stores information about re-sampling time. The combiner bank includes a number of adders and multipliers, performs an operation, and outputs a re-sampled value. The second delay bank causes a delay so that output of each combiner can be synchronized with each output of the fractional delay constant table.

Abstract: A signal processing apparatus of the present invention includes an input unit configured to receive a reference signal supplied from an external device, a phase detection unit configured to detect a phase difference between the reference signal received from the input unit and a clock signal, a generation unit configured to generate the clock signal with a frequency corresponding to an output of the phase detection unit, and a control unit configured to detect an error between a frequency of the reference signal received from the input unit and the frequency of the clock signal based on an output of the phase detection unit and to output information, which indicates the status of a frequency change in the reference signal, to a display device based on the detected error.

Abstract: A phase locked loop (PLL) circuit and a system including such a PLL that may at least compensate for leakage current in a loop filter. The PLL circuit may include a voltage adjusting unit configured to pump charges based on a phase difference between an oscillation clock signal and a reference clock signal, a loop filter configured to generate a frequency control voltage, a level of which is shifted by the charge pumping of the voltage adjusting unit, a voltage controlled oscillator (VCO) configured to output the oscillation clock signal having a frequency corresponding to the frequency control voltage, and a current control circuit configured to generate a compensation current corresponding to a leakage current generated by the loop filter and allow the compensation current and the leakage current to substantially and/or completely counterbalance each other.

Abstract: A method and a device for processing a signal determine a timing phase over an observation interval of an input signal. A frequency estimation is determined based on the timing phase. A phase correction is determined for the observation interval based on the timing phase and the frequency offset. Then the phase correction is used to adjust the timing of the input signal. Also, a communication system with at least one such device is described.

Abstract: An object is to provide a method for preventing the occurrence of variations in time resolution by providing a calibration process to a TDC at the time of start up and further preventing the increase in circuit scale by reducing the redundancy of delay elements. A calibration of a multiphase oscillator TDC and a vernier TDC is carried out at the time of power-on. In the calibration, a timing input to be input to the vernier TDC is selected from output signals of DCCO based on a reference clock. Also, data is defined as an output signal which is adjacent to the output signal of DCCO mentioned above and proceeds in phase, and the delay therebetween is derived. By repeating it to all of the output signals, the one cycle of the output signal of DCCO is derived.

Abstract: The present invention discloses a frequency synthesizer which includes: a PLL including an oscillator for generating an oscillator signal and a first frequency divider for dividing a frequency of the oscillator signal to generate a first frequency-divided signal; a switching unit for switching the PLL to either an open loop status or a closed loop status; a second frequency divider, for dividing a frequency of a reference clock to generate a second frequency-divided signal; a counter, for counting according to the first frequency-divided signal and the second frequency-divided signal to generate a counter value when the PLL is in the open loop status; a comparator, for comparing the counter value with a predetermined value to generate a comparing result; and a determining unit, for adjusting an oscillator frequency of the oscillator according to the comparing result.

Abstract: Phase profile generator systems and methods are disclosed. A system includes a signal generator, a target phase trajectory module, an error detector and a control loop filter. The signal generator is configured to generate an output signal. In addition, the target phase trajectory module is configured to track a target phase trajectory and determine a next adjustment of the output signal to conform the output signal to a portion of the target phase trajectory. Further, the error detector is configured to determine an error between the output signal and a current target phase trajectory value that precedes the portion of the target phase trajectory, where the determination of the error is independent of the next adjustment of the output signal. Moreover, the control loop filter is configured to control the signal generator in accordance with both the next adjustment and the error to generate a phase profile.

Abstract: An automatically calibrating time to digital conversion circuit. The circuit includes a first circuit node for switchably receiving a first calibration signal and a second circuit node coupled with the first circuit node via a first delay path. A third circuit node for switchably receiving a second calibration signal the same as the first calibration signal is coupled with a fourth circuit node via a second delay path. A calibration portion has a third delay path switchably connected with the fourth circuit node and a fourth delay path switchably connected with the second circuit node. The calibration portion generates a delay adjustment signal for adjusting a time delay of the first delay path such that the first time delay combined with the fourth time delay equals the second time delay combined with the third time delay. The calibration portion is disconnected when calibration is not desired for conserving power.

Abstract: A phase detection and decision feedback equalization circuit is provided. A first latch and a second latch are coupled to an input of the circuit. A third latch and a fourth latch are respectively coupled in series to outputs of the first latch and second latch. The first and fourth latches are enabled by a clock signal, and the second and third latches are enabled by a complement of the clock signal. A first feedback circuit is configured to provide a signal output from the first latch and a first feedback signal derived from the output of the fourth latch to an input of the third latch. A second feedback circuit is configured to provide a signal output from the second latch and a second feedback signal derived from the output of the third latch to an input of the fourth latch.

Abstract: One embodiment of the invention relates to a communication system having an amplitude modulation path, a frequency deviation component, a characterization component, a peak cancellation component and a compensation unit. The amplitude modulation path is configured to provide an amplitude modulation signal. The frequency deviation component is configured to generate a frequency deviation signal. The characterization component is configured to generate characterization coefficients according to the amplitude modulation signal and the frequency deviation signal. The peak cancellation component is configured to identify peaks according to the amplitude modulation signal and generate a peak cancellation signal to compensate for peak distortion by the identified peaks.