With Digital Element Patents (Class 327/159)
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Publication number: 20140266354Abstract: Disclosed is a digital phase-locked-loop including: a time-to-digital converter (TDC) configured to output a digital bit based on an input clock and a reference clock, in which the TDC includes: a first arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a first average offset and output a first logic value; a second arbiter group configured to compensate for a phase difference between the input clock and the reference clock with a second average offset and output a second logic value; and a signal processor configured to output the digital bit based on the first and second logic values.Type: ApplicationFiled: September 17, 2013Publication date: September 18, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Hyun Ho BOO, Byung Hun MIN, Duong Quoc HOANG, Cheon Soo KIM, Hyun Kyu YU
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Publication number: 20140266353Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Yi Tang, Bo Sun
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Patent number: 8836434Abstract: A digital frequency synthesizer with an automatic calibration system. The digital frequency synthesizer is calibrated by initiating a coarse tuning operation to rapidly reach a preliminary frequency that is proximate to the desired final frequency. A calibration procedure is then executed for adjusting gain in the frequency synthesizer based on the preliminary frequency. This test involves applying one or more test signals to the frequency synthesizer and measuring a signal generated in the frequency synthesizer. This measured signal corresponds to a gain response of the circuit at the preliminary frequency. When the expected gain is known, any difference relative to the gain of the measured signal is used to adjust the gain in a circuit of the frequency synthesizer such that the actual gain substantially matches the expected gain.Type: GrantFiled: September 8, 2009Date of Patent: September 16, 2014Assignee: Icera Inc.Inventors: Abdellatif Bellaouar, Ahmed R. Fridi, Sher Jiun Fang, Hamid Safiri
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Patent number: 8816724Abstract: Methods and systems are disclosed that provide a radio frequency synthesizer that generates precise frequencies over a large radio frequency range. The radio frequency synthesizer can provide a high resolution of frequency generation and still provide precise frequencies over a range of radio frequencies. The precision and resolution while maintaining a large operating range come from the ability of the frequency synthesizer to generate frequencies as a product of a plurality of moduli. For example, the frequency can be generated from a reference frequency using a first modulus and a second modulus. The plurality of modulo can be implemented using nested digital delta-sigma modulators in a fractional-N frequency synthesizer.Type: GrantFiled: December 14, 2012Date of Patent: August 26, 2014Assignee: University College Cork—National University of Ireland, CorkInventor: Michael Peter Kennedy
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Patent number: 8816781Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.Type: GrantFiled: September 20, 2012Date of Patent: August 26, 2014Inventor: Phuong Huynh
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Patent number: 8810440Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.Type: GrantFiled: May 29, 2012Date of Patent: August 19, 2014Assignee: Southeast UniversityInventors: Jianhui Wu, Zixuan Wang, Xiao Shi, Meng Zhang, Cheng Huang, Chao Chen, Fuqing Huang, Xincun Ji, Ping Jiang
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Patent number: 8810321Abstract: An oscillator auto-trimming method is provided. The oscillator auto-trimming method includes receiving, by a subtractor, a first count result and second count result to output a difference between the first count result and the second count result as an offset frequency, receiving, by a divider, the offset frequency to output a divided signal corresponding to a result of dividing the offset frequency by a reference offset frequency output from a micro control unit, and receiving, by the micro control unit, the divided signal and determine whether to change an oscillator frequency.Type: GrantFiled: September 12, 2012Date of Patent: August 19, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Kwang Ho Choi
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Publication number: 20140225653Abstract: A cascaded phase-locked loop (PLL) clock generation technique reduces frequency drift of a low-jitter clock signal in a holdover mode. An apparatus includes a first PLL circuit configured to generate a control signal based on a first clock signal and a first divider value. The apparatus includes a second PLL circuit configured to generate the first clock signal based on a low-jitter clock signal and a second divider value. The apparatus includes a third PLL circuit configured to generate the second divider value based on the first clock signal, a third divider value, and a second clock signal. The low-jitter clock signal may have a greater temperature dependence than the second clock signal and the second clock signal may have a higher jitter than the low-jitter clock signal.Type: ApplicationFiled: February 13, 2013Publication date: August 14, 2014Applicant: SILICON LABORATORIES INC.Inventors: Susumu Hara, Adam B. Eldredge, Jeffrey S. Batchelor, Daniel Gallant
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Publication number: 20140225654Abstract: A phase-lock loop having a reduced lock time in comparison with the conventional art. The phase-lock loop compares an output signal thereof with a reference signal, and alters a control signal in response thereto such that the output signal may have a desired frequency.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Chin Yeong KOH, Kar Ming YONG
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Publication number: 20140218085Abstract: Fast phase coordinating systems and methods are disclosed. An example system includes a phase locator configured to detect a first phase of a reference signal and a first phase of a coordinating signal after the first phase of the reference signal. An integrator is configured to integrate from the first phase of the reference signal to a location phase of the coordinating signal and integrate oppositely from the first phase of the coordinating signal to a time-shifted phase of the reference signal and output the result. A control function is configured to shift the phase of the coordinating signal in response to output from the integrator.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicant: GAIN ICS LLCInventor: Jed Griffin
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Publication number: 20140218086Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.Type: ApplicationFiled: April 3, 2014Publication date: August 7, 2014Applicant: MARVELL WORLD TRADE LTD.Inventors: Olivier Burg, Cao-Thong Tu
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Patent number: 8797081Abstract: The circuit for the clocking of an FPGA comprises an FLL-circuit; a reference clock of a first frequency, or a reference clock input for the reception of a signal of a reference clock of a first frequency; and a digitally controlled oscillator, which outputs a clocking signal for the FPGA, wherein the FLL-circuit is designed in order to register a first number of clocking signals from the digitally controlled oscillator during a second number of periods of the reference clock, the first number is larger than the second number, and, in order to give out a feedback signal to control the ratio between the first number and the second number, as the feedback signal acts on the frequency of the digitally controlled oscillator.Type: GrantFiled: April 14, 2011Date of Patent: August 5, 2014Assignee: Endress + Hauser GmbH + Co. KGInventors: Marc Schlachter, Romuald Girardey
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Patent number: 8797075Abstract: In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock signal. The apparatus further includes a controller unit to generate a delay signal based on the phase difference. The apparatus further includes a set of voltage-controlled delay lines to generate phase outputs based on the delay signal, where the phase outputs are provided by the apparatus to a clock generator unit to generate an oversampled clock signal for data recovery by a receiver.Type: GrantFiled: June 25, 2012Date of Patent: August 5, 2014Assignee: Intel CorporationInventor: Wei-Lien Yang
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Publication number: 20140210532Abstract: A PLL includes an oscillator, a time-to-digital converter (TDC) and a system for the remaining functionality. The TDC measures the oscillator's phase against a reference clock. The measured phase has an integer part obtained from a modulus-K counter, and a fractional part measured by a fine TDC. The system compares the measured phase with a desired phase, and filters it to obtain a parameter that controls the oscillator frequency. The TDC may also include a synchronization block to align the fine TDC and a pulse hider to reduce the power used by the fine TDC. The system may include an integrator to calculate the integer part of the desired phase, a second integrator to calculate the fractional part, and an interpolator for an even finer fraction. A method to obtain fast lock includes using the phase error rate of change to control the oscillator frequency.Type: ApplicationFiled: January 29, 2014Publication date: July 31, 2014Applicant: PERCEPTIA DEVICES AUSTRALIA PTY LTD.Inventor: Julian Jenkins
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Patent number: 8786341Abstract: A digital frequency synthesizer provides absolute phase lock and shorter settling time through the use of a digital filter with a phase and frequency path. Control logic control disables the frequency path during the frequency acquisition and sets a wide bandwidth. After frequency acquisition, a counter with digital phase information is reset using the input clock signal to bring the output phase closer to lock with the input signal and the control logic enables the phase path in the digital loop filter to achieve phase lock with a narrower bandwidth than the initial bandwidth.Type: GrantFiled: March 15, 2013Date of Patent: July 22, 2014Assignee: Silicon Laboratories Inc.Inventors: Colin Weltin-Wu, Yunteng Huang
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Patent number: 8779817Abstract: An apparatus and method for reducing effects of spurs in a phased-locked loop having a sigma-delta modulator and digital circuits. The apparatus includes a clock dithering circuit coupled to each of the sigma-delta modulator and the digital circuits. Each clock dithering circuit is configured to dither flanks of a respective first and second clock input signal, and generate a dithered clock output signal, one for each of the sigma-delta modulator and digital circuits. A frequency of each dithered clock output signal follows a frequency of the respective first and second clock input signals, and a phase between each dithered clock output signal and the respective first and second clock input signal is shifted and constantly changing.Type: GrantFiled: December 2, 2013Date of Patent: July 15, 2014Assignee: Huawei Technologies Co., Ltd.Inventor: Anders Jakobsson
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Patent number: 8773181Abstract: The present invention provides a locked loop circuit in which the input clock signal is delayed according to a saw-tooth signal in order to output a range of frequencies not necessarily equal to an integer multiple of the input clock signal. The absolute value of the delay (i.e. the difference between the maximum and minimum values of the saw-tooth delay) can be calibrated by detecting the value of the circuit phase detector at the wrap point of the saw-tooth.Type: GrantFiled: November 30, 2012Date of Patent: July 8, 2014Assignee: Cambridge Silicon Radio, Ltd.Inventors: Duncan Mcleod, Farshid Nowshadi, David Chappaz
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Patent number: 8766729Abstract: An apparatus, and an associated method, for synthesizing a discrete-valued oscillating signal. Input parameters are provided that are determinative of the frequency, gain, and phase characteristics of the resultant, oscillating signal. The discrete-valued, oscillating signal is combinable with another signal to form a mixed signal of a desired frequency, gain, and phase characteristic using a single complex multiplication operation.Type: GrantFiled: October 5, 2011Date of Patent: July 1, 2014Assignee: BlackBerry LimitedInventors: Nebu John Mathai, Stephen Arnold Devison, Oleksiy Kravets
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Patent number: 8760176Abstract: Systems provide for a test system for capacitors in a digitally controllable oscillator (DCO). The system includes: capacitor toggling logic configured to switch on and off a selected one of the capacitors at a modulation frequency; a tone generator configured to generate a tone; a mixer configured to receive the tone and an output carrier signal from the DCO while the capacitor toggling logic is switching the selected one of the capacitors on and off and to output an intermediate frequency signal having FM sidebands based on the modulation frequency and relative capacitor size; and an evaluation circuit configured to evaluate a frequency deviation associated with the selected one of the capacitors based on at least one of the FM sidebands.Type: GrantFiled: May 19, 2011Date of Patent: June 24, 2014Assignee: St-Ericsson SAInventor: Jeroen Kuenen
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Patent number: 8761688Abstract: A radio frequency circuit and a signal transmission method are provided. The radio frequency circuit comprises a primary antenna, a secondary antenna and a radio frequency integrated circuit. The primary antenna is electrically coupled to the radio frequency integrated circuit to transmit and receive at least one transmission/reception signal. The secondary antenna is electrically coupled to the radio frequency integrated circuit to receive at least one diversity reception signal. The radio frequency integrated circuit is configured to receive a specific diversity reception signal via the primary antenna and to transmit and receive a specific transmission/reception signal via the secondary antenna.Type: GrantFiled: June 8, 2011Date of Patent: June 24, 2014Assignee: HTC CorporationInventors: Wei-Yang Wu, Wei-Chien Chen, Chien-Hua Ma
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Patent number: 8754713Abstract: In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.Type: GrantFiled: November 23, 2010Date of Patent: June 17, 2014Assignees: Renesas Electronics Corporation, Epoch Microelectronics, Inc.Inventors: Toshiya Uozumi, Keisuke Ueda, Mitsunori Samata, Satoru Yamamoto, Russell P Mohn, Aleksander Dec, Ken Suyama
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Publication number: 20140159790Abstract: A digital phase-locked loop is provided. The digital phase-locked loop includes: a phase-locked loop, for generating an output frequency according to a reference frequency; and a numerically-controlled oscillator, coupled to the phase-locked loop, for generating the reference frequency, in which the numerically-controlled oscillator includes: a phase accumulator (PA), for outputting a sawtooth signal according to a clock signal and a frequency control word; and a most significant bit (MSB) detector, coupled to the phase accumulator, for detecting a most significant bit of the sawtooth signal outputted from the phase accumulator, thereby generating the reference frequency with a square waveform.Type: ApplicationFiled: June 18, 2013Publication date: June 12, 2014Inventor: Wen-Jan LEE
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Patent number: 8750448Abstract: A frequency calibration apparatus and method are provided. A frequency calibration method includes determining a frequency band according to results of frequency comparisons between a synchronized reference signal whose phase is synchronized to a phase of a prescale signal and a divided signal, and performing a Phase Locked Loop (PLL) operation on a reference signal and the divided signal at the determined frequency band to lock the divided signal.Type: GrantFiled: April 8, 2008Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dzmitry Mazkou, Hyun-su Chae
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Patent number: 8742862Abstract: A current reuse voltage controlled oscillator with improved differential output is disclosed. In an exemplary embodiment, an apparatus includes a PMOS transistor and an NMOS transistor coupled together for current reuse and configured to provide differential oscillator outputs. The apparatus also includes a common mode rejection (CMR) circuit coupled between the PMOS and the NMOS transistors, the CMR circuit includes an inductor having a least one tap that can be selectively coupled to a ground to reduce common mode signals at the differential oscillator outputs.Type: GrantFiled: November 13, 2012Date of Patent: June 3, 2014Assignee: QUALCOMM IncorporatedInventor: Mazhareddin Taghivand
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Publication number: 20140145771Abstract: A circuit includes a delay line and a delay locked loop. The circuit is configured to receive a delay parameter and a clock signal. The delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop. The delay locked loop is configured to determine a difference between the frequency of the clock signal and the frequency of the oscillator based on a phase of an output of the oscillator and a phase of the clock signal after the output of the oscillator and the clock signal are aligned. The delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter.Type: ApplicationFiled: November 28, 2012Publication date: May 29, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Muhammad NUMMER, Dirk PFAFF
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Patent number: 8736384Abstract: In some embodiments, provided are calibration techniques for measuring mismatches between TDL delay stage elements, and in some cases, then compensating for the mismatches to minimize performance degradation.Type: GrantFiled: April 29, 2010Date of Patent: May 27, 2014Assignee: Intel CorporationInventors: Ashoke Ravi, Ofir Degani, Hasnain Lakdawala, Masoud Sajadieh
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Publication number: 20140132320Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: LSI CorporationInventors: Vladimir Sindalovsky, Mohammad S. Mobin, Lane A. Smith
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Publication number: 20140132321Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.Type: ApplicationFiled: November 13, 2012Publication date: May 15, 2014Applicant: International Business Machines CorporationInventors: Grant P. Kesselring, James D. Strom, Kenneth A. Van Goor, Kennedy K. Cheruiyot
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Patent number: 8723571Abstract: Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.Type: GrantFiled: February 22, 2011Date of Patent: May 13, 2014Assignee: Nvidia Technology UK LimitedInventor: Steve Felix
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Patent number: 8723607Abstract: A phase locked loop comprising: an oscillator for generating an output signal of a frequency that is dependent on an input to the oscillator; sampling means for generating a sequence of digital values representing the output of the oscillator at moments synchronized with a reference frequency; a difference unit for generating a feedback signal representing the difference between successive values in the sequence; and an integrator for integrating the difference between the feedback signal and a signal of a desired output frequency; the signal input to the oscillator being dependent on the output of the integrator.Type: GrantFiled: August 19, 2008Date of Patent: May 13, 2014Assignee: Cambridge Silicon Radio LimitedInventors: Michael Story, Nicolas Sornin
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Patent number: 8710884Abstract: Methods and devices provide for determining whether to operate a radio frequency synthesizer in a first mode of operation or a second mode of operation based on a reference frequency signal. The radio frequency synthesizer includes a digitally-controlled oscillator configured to generate an oscillator signal having an output frequency. A digital frequency locked-loop is configured to control the output frequency of the oscillator signal in a first mode of operation based on a first control signal. A digital phase locked-loop is configured to control the output frequency of the oscillator signal in a second mode of operation based on a second control signal. A controller determines whether to operate in the first mode or second mode based on a reference frequency signal. The controller generates the first or second control signal based on the determination of operating in the first or second mode, respectively.Type: GrantFiled: February 27, 2012Date of Patent: April 29, 2014Assignee: Marvell World Trade Ltd.Inventors: Olivier Burg, Cao-Thong Tu
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Patent number: 8704569Abstract: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.Type: GrantFiled: December 18, 2012Date of Patent: April 22, 2014Assignee: MOSAID Technologies IncorporatedInventors: Dieter Haerle, Tony Mai, Peter Vlasenko
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Patent number: 8704571Abstract: Methods and systems for synchronizing an electric grid having unbalanced voltages are provided. A voltage vector may be filtered in a quadrature tracking filter (QTF) to generate a quadrature signal. A phase-locked-loop (PLL) operation may be performed on the quadrature signal to monitor a voltage vector between the grid and a connected power converter. The QTF and PLL methods are suitable for either single-phase applications or n-phase (any number of phases) applications. A frequency estimator estimates the grid frequency of the electric grid and outputs the estimated frequency to the QTF algorithms. The frequency estimator may include a three-phase phase-locked-loop (three-phase PLL) suitable for estimating the center frequencies of multiple phases of the electric grid. The frequency estimator may also include means for reducing the harmonics in the grid system.Type: GrantFiled: May 10, 2012Date of Patent: April 22, 2014Assignee: Rockwell Automation Technologies, Inc.Inventors: Russel J. Kerkman, Ahmed Mohamed Sayed Ahmed, Brian J. Seibel, Carlos Rodriguez Valdez
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Publication number: 20140103977Abstract: A method and system is disclosed in which the phase detector in a phase-locked loop is able to run at the fastest speed appropriate for a reference signal. A frequency offset is added, to the output frequency of the phase-locked loop, to alter the frequency fed to the frequency divider which would receive the output frequency in a conventional PLL to an intermediate frequency. The frequency offset is selected so that the ratio of the intermediate frequency to the reference frequency is a simple fraction, and preferably an integer, i.e., the intermediate frequency is a multiple of the reference frequency. In cases where the relationship between the output frequency and the reference frequency is largely relatively prime, the phase detector is thus able to receive signals at the frequency of the reference signal and operate at the fastest speed appropriate for the reference signal.Type: ApplicationFiled: October 16, 2013Publication date: April 17, 2014Applicant: ESS Technology, Inc.Inventors: Hu Jing Yao, Dustin Dale Forman, A. Martin Mallinson
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Patent number: 8692621Abstract: In one general aspect, an apparatus can include a phase frequency detector configured to produce a plurality of indicators of relative differences between a frequency of a target oscillator signal and a frequency of a reference oscillator signal. The apparatus can also include a pulse generator configured to produce a plurality of pulses based on the plurality of indicators. The plurality of pulses can include a first portion configured to trigger an increase in the frequency of the target oscillator signal and the plurality of pulses including a second portion configured to trigger a decrease in the frequency of the target oscillator signal.Type: GrantFiled: December 21, 2011Date of Patent: April 8, 2014Assignee: Fairchild Semiconductor CorporationInventors: Kenneth P. Snowdon, Jeffrey S. Martin
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Patent number: 8692599Abstract: A flexible clock synthesizer technique includes generating a phase interpolator calibration signal to adjust a phase interpolator output signal generated by a phase interpolator of an interpolative divider. The phase interpolator is responsive to a phase interpolator control code and an output signal of a fractional-N divider of the interpolative divider. The phase interpolator calibration signal is based on an error signal indicative of a phase interpolator error. The error signal may indicate a phase relationship between a reference clock signal and a feedback clock signal of a PLL. The interpolative divider may be coupled in a feedback path of the PLL. The PLL may receive a reference clock signal and the feedback clock signal may be an adjusted phase interpolator output signal. The phase interpolator calibration signal may be a phase interpolator offset code corresponding to the phase interpolator control code or a phase interpolator gain signal.Type: GrantFiled: August 22, 2012Date of Patent: April 8, 2014Assignee: Silicon Laboratories Inc.Inventors: Xue-Mei Gong, Adam B. Eldredge, Susumu Hara
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Patent number: 8692598Abstract: An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal.Type: GrantFiled: February 23, 2012Date of Patent: April 8, 2014Assignee: LSI CorporationInventor: Joseph H. Havens
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Patent number: 8686771Abstract: The present disclosure is directed to digital phase-locked loops (DPLLs) and hybrid phase-locked loops (HPLL) for establishing and maintaining a phase relationship between a generated output signal and a reference input signal. The DPLLs use a counter based loop to initially bring the DPLL into lock. Thereafter, the DPLLs disable the counter based loop and switch to a loop with a multi-modulus divider (MMD). The DPLLs can implement a cancellation technique to reduce phase noise introduced by the MMD. The HPLLs further include a loop with a MMD. The HPLLs can implement a similar cancellation technique to reduce phase noise introduced by the MMD.Type: GrantFiled: May 31, 2012Date of Patent: April 1, 2014Assignee: Broadcom CorporationInventors: Emmanouil Frantzeskakis, Ioannis L. Syllaios, Georgios Sfikas, Henrik Jensen, Stephen Wu, Padmanava Sen
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Publication number: 20140084978Abstract: Systems and methods for generating a thermometer sigma delta encoded frequency control word for controlling a digitally controlled oscillator in accordance with embodiments of the invention are disclosed. In one embodiment, an all digital phase locked loop for generating an output clock signal includes a thermometer pulse coder configured to generate a frequency control word (FCW) that includes thermometer coded signals and a pulse modulated dither signal, and transmit the pulse modulated dither signal over a selected FCW signal line and transmit the thermometer coded signals over other FCW signal lines, and a digitally controlled oscillator to receive a FCW comprising a combined thermometer and pulse modulated signal and generate an output clock signal.Type: ApplicationFiled: September 16, 2013Publication date: March 27, 2014Applicant: Entropic Communications, Inc.Inventors: Josephus A. van Engelen, Hairong Yu, Howard A. Baumer
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Publication number: 20140077852Abstract: A method and apparatus is provided for controlling a delay line for achieving power reduction. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal, said delay lock loop comprising at least one delay circuit comprising a plurality of logic gates configured to provide for substantially uniform degradation of a plurality of NAND gates in a static state.Type: ApplicationFiled: November 19, 2013Publication date: March 20, 2014Applicant: Micron Technology, Inc.Inventors: Tyler J. Gomm, Debra Bell
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Patent number: 8674773Abstract: In one embodiment, one or more circuits convert an n-bit control code of a phase interpolator to a coupling control signal of k-bit wide. The one or more circuits couple one or more output signals of the phase interpolator to a reference clock of the phase interpolator based on the coupling control signal.Type: GrantFiled: January 31, 2012Date of Patent: March 18, 2014Assignee: Fujitsu LimitedInventor: Nikola Nedovic
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Patent number: 8675800Abstract: Disclosed herein is a synchronizing circuit including: a first PLL circuit; a second PLL circuit; a first output circuit; a second output circuit; a first detection circuit; a second detection circuit; a control circuit; and a holding section.Type: GrantFiled: September 21, 2011Date of Patent: March 18, 2014Assignee: Sony CorporationInventors: Tetsuhiro Futami, Ikko Okamoto
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Patent number: 8669890Abstract: A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.Type: GrantFiled: September 11, 2012Date of Patent: March 11, 2014Assignee: Mediatek Inc.Inventors: Chi-Hsueh Wang, Robert Bogdan Staszewski, Yi-Hsien Cho
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Patent number: 8664985Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.Type: GrantFiled: July 12, 2012Date of Patent: March 4, 2014Assignee: Mediatek Inc.Inventors: Yu-Li Hsueh, Jing-Hong Conan Zhan
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Publication number: 20140055183Abstract: A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.Type: ApplicationFiled: February 1, 2013Publication date: February 27, 2014Applicant: SK HYNIX INC.Inventor: Jong Ho JUNG
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Patent number: 8653869Abstract: A Fractional-N PLL includes a phase frequency detector module receiving a first clock and a second clock that is associated with a feedback path arrangement. A coarse phase adjustment module receives a coarse phase component and an output signal associated with a divider module used in the feedback path arrangement and performs a coarse phase adjustment. A fine phase adjustment module performs fine phase adjustment using a fine phase component and the coarse phase adjustment as input to produce the second clock. The fine phase adjustment module nominally cancels most or all of the quantization noise present during the coarse phase adjustment, thereby greatly reducing the net phase noise of the divider module. A segmentation module receives a control signal and generates the coarse phase component and the fine phase component that are provided to the fine phase adjustment module and the coarse phase adjustment module for processing.Type: GrantFiled: September 13, 2012Date of Patent: February 18, 2014Assignee: Media Tek Singapore Pte. Ltd.Inventors: Tsung-Kai Kao, Che-Fu Liang, Michael A. Ashburn, Jr.
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Patent number: 8648626Abstract: A clock generator and generating method, and a mobile communication device using the clock generator. A clock generator comprises a first accumulator, an oscillating signal generating circuit and a frequency adjustment circuit. The oscillating signal generating circuit generates a first oscillating signal and adjusts a frequency of the first oscillating signal according to a first overflow output signal of the first accumulator. The frequency adjustment circuit generates a frequency control value according to the first oscillating signal and a reference oscillating signal. The first accumulator accumulates the frequency control value according to the first oscillating signal to generate the first overflow output signal.Type: GrantFiled: October 18, 2010Date of Patent: February 11, 2014Assignee: Via Telecom Co., Ltd.Inventor: Yu-Hong Lin
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Publication number: 20140035641Abstract: A method of measuring a phase difference for use in a phase locked loop (PLL) that includes a binary phase detector (BPD), a time-to-digital converter (TDC) and a signal generator, the phase difference being that between a reference signal and a generated signal output from the signal generator. The method includes inputting the reference signal and the generated signal into the TDC; measuring the magnitude of the phase difference at the TDC; if the measured magnitude of the phase difference is less than a threshold value, operating the PLL according to a first operational mode in which the output of the BPD controls the signal generator; and if the measured magnitude of the phase difference is greater than the threshold value, operating the PLL according to a second operational mode in which the output of the TDC and the BPD controls the signal generator.Type: ApplicationFiled: July 31, 2012Publication date: February 6, 2014Applicant: CAMBRIDGE SILICON RADIO LIMITEDInventors: Pasquale Lamanna, Davide Orifiamma
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Patent number: 8638139Abstract: A phase locked loop (PLL) based frequency sweep generator and methods for performing a frequency sweep are disclosed. In one implementation, the frequency sweep generator includes a circuit configured to generate a signal having a saw-tooth wave frequency ramp. The saw-tooth wave frequency ramp includes a rising portion and a resetting portion. The resetting portion has a shorter duration than the rising portion and includes a plurality of steps for decrementing the frequency of the signal.Type: GrantFiled: September 9, 2011Date of Patent: January 28, 2014Assignee: Analog Devices, Inc.Inventors: Michael Keaveney, Patrick Walsh
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Patent number: 8638147Abstract: A clock generator includes a digitally controlled oscillator configured to generate an output clock having a frequency depending on an input code; a phase comparison section configured to output a phase difference signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; a low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.Type: GrantFiled: August 12, 2013Date of Patent: January 28, 2014Assignee: Fujitsu LimitedInventor: Atsushi Matsuda