Abstract: Embodiments of the invention include an apparatus and method for continuously calibrating the frequency of a clock and data recovery (CDR) circuit. The apparatus includes a delay arrangement that generates a gating signal, and a gated voltage-controlled oscillator that is enabled by the gating signal. The gated voltage-controlled oscillator generates a recovered clock signal that is based on the data signal input to the CDR circuit. The apparatus also includes a frequency control loop that continuously calibrates the gated voltage-controlled oscillator in such a way that the frequency of the clock signal generated by the gated voltage-controlled oscillator continues to be one half of the period of the data bits in the input data signal and the clock signal remains synchronized to the center of the data state transitions of the input data signal. Alternatively, a secondary frequency control loop adjusts the amount of delay in the frequency control loop.

Abstract: A method and system for decision feedback equalization for digital transmission systems is provided. Low-power integrating decision feedback equalization with fast switched-capacitor paths are used, for suppressing intersymbol interference (ISI) due to past data symbols. The decision feedback equalization involves performing current-integrating decision feedback equalization at low-power employing a fast capacitively coupled feed-forward path at the output of a current-integrating buffer and inducing voltage changes by charge redistribution via coupled switching capacitors, and performing a voltage digital-to-analog conversation to determine a feedback coefficient as a coupling voltage. Then switches are reset to a pre-charge coupling voltage in the buffers to eliminate residual ISI caused by signal history, thereby achieving current integrating buffering with switched-capacitor feedback during the integration, and the capacitive switches are triggered by previous symbols.

Abstract: The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble.

Abstract: A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

Abstract: In order to monitor various types of noises which are to be introduced on signals through signal lines on a circuit board and automatically adjust the thresholds for signal state discriminations to make it possible to surely make a signal state discrimination without being affected by these noises even if the amplitude of a signal is reduced for higher-speed transmission and lowered electric power, there is provided a configuration comprising a signal generation unit generating a noise monitor signal; a noise monitor signal line receiving and propagating the noise monitor signal; a noise detection unit detecting a noise which has been introduced into that noise monitor signal propagated through the noise monitor signal line and which affects a state discrimination using a threshold; and a threshold adjustment unit, if the noise detection unit detects the noise, adjusting the threshold such that the state discrimination is not affected by the noise.

Abstract: The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption.

Abstract: A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.

Abstract: An oscillator includes an oscillating block for generating a control signal in response to an enable signal, wherein the control signal is periodically toggled and a feedback block for receiving the control signal to generate the enable signal in response to an oscillator enable signal wherein the enable signal operates so that the control signal is maintained to complete a last cycle period after an inactivation timing of the oscillator enable signal.

Abstract: A display device includes a timing controller and a display unit. The timing controller receives an external clock signal, reads signal generation information, and generates and outputs an internal clock signal based on the read signal generation information. The display unit receives the internal clock signal and displays an image. When the internal clock signal is abnormal, the timing controller rereads the signal generation information and generates and outputs the internal clock signal based on the reread signal generation information.

Abstract: A digital-to-analog converter adapted for use as a feedback converter in a continuous time sigma delta analog-to-digital converter. The digital-to-analog converter has a discrete time digital signal input accepting digital signal samples that are synchronized with an assertion of a first data clock signal and a discrete time clock generator that generates an output pulse in response to receiving an assertion of the first data clock. The output pulse is asserted for a fixed duration that is independent of a jitter of the first data clock. The digital-to-analog converter also includes a continuous time analog output that produces, during assertion of the output pulse, a continuous time analog output signal having a magnitude corresponding to the digital signal samples.

Abstract: A variable power supply voltage generator generates a variable power supply voltage Vvar and supplies it to other circuits. A transmitting circuit 130 (or 140), operative at the variable power supply voltage Vvar, generates multi-value analog signals Smulti and transmits them to other circuits. A receiving circuit 140 (or 130), operative at the variable power supply voltage Vvar, receives the multi-value analog signals Smulti and subjects them to A/D conversion to generate multi-value digital signals. The threshold voltage generator generates threshold voltages used for A/D conversion from the variable power supply voltage Vvar or from a signal having a voltage value proportional to that of the variable power supply voltage Vvar and supplies them to the receiving circuit. An analog clock generator 120 generates an analog clock signal having a cyclical analog waveform.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: An HDMI cable carries high speed encoded data which are transmitted differentially over data channels, along with a clock. High-frequency loss and differential skew within a differential signal may be compensated by analog circuits embedded in the cable. These embedded circuits are tuned at production for best performance by observing the quality of the recovered analog signal. The embedded circuits are powered by a combination of power sources, both carried within the cable, and harvested from the high-speed signals themselves.

Abstract: There is disclosed a clock regeneration circuit having a PCR buffer including a register which buffers a PCR extracted from a transmission signal, a counter which counts a reception side reference clock CKr, an STC buffer including a register which buffers a counted value of the counter, and a CPU which generates a signal indicating a difference between a transmission side reference clock and the reception side reference clock CKr based on values held in the PCR buffer and the STC buffer. If, at this point, a new PCR is input before the values held in the PCR buffer and the STC buffer are read by the CPU, the PCR buffer and the STC buffer are not updated.

Abstract: There are provided an apparatus and method for recovering a clock signal from a burst mode signal. A first delay delays an input data signal for half of a time period of the input data signal, and produces a first delay signal. An XOR gate adds the input data signal and the first delay signal provided from the first delay, and provides an inverted signal of the added signal. An OR gate adds an output signal of the XOR gate and a second delay signal, and provides the added signal as a recovered clock signal. A second delay delays the added signal provided from the OR gate for an integer multiple of a time period of the input data signal, and produces the second delay signal that is provided to the OR gate. The frequency of the recovered clock signal is not limited by any delay in the gate elements due to a phase transition of the input data signal occurring when every other packet is provided.

Abstract: An oversampling delay is provided between clock and data signals by steering a current between first and second nodes. The first node is coupled to an input differential pair of a clock interpolator and a delayed differential pair of a data interpolator. The second node is coupled to an input differential pair of the data interpolator and a delayed differential pair of the clock interpolator. First clock and data signals are provided to a first data sampling element and, respectively, to the clock and data interpolators. Second clock and data signals, respectively output from the clock and data interpolators, are provided to a second data sampling element. Additional data sampling elements may be linked to form a longer chain of data sampling elements.

Abstract: Example embodiments are directed to a receiver for reducing ISI of at least one data transmission channel and compensating for signal gain loss, and method thereof. A receiver may include a high pass filter and a Schmitt trigger controlled by a plurality of first control signals and a plurality of second control signals. The plurality of first control signals and the plurality of second control signals may be used to shift a first trigger voltage and a second trigger voltage of the Schmitt trigger. A method of reducing intersymbol interference and compensating for signal gain loss of a receiver connected to at least one data transmission channel is also provided.

Abstract: A reproduced signal waveform processing apparatus is provided. The apparatus includes an A/D converter for sampling a reproduced signal at a reproducing clock having a predetermined oscillation frequency; a first equalizer for equalizing a digital reproduced signal from the A/D converter; a second equalizer connected in series with the first equalizer for further equalizing the digital reproduced signal from the first equalizer; a phase frequency controller for detecting a phase frequency error between the digital reproduced signal from the first equalizer and the reproducing clock signal, and outputting a control signal on the basis of a result of the detection; and a variable frequency oscillator for varying the oscillation frequency in accordance with the control signal.

Abstract: A detector for locating a sonde includes a plurality of antennas, an analogue to digital converter 11 and a digital signal processor to isolate the magnetic signal produced by the sonde. The digital signal processor includes a phase feedback loop 21 to allow the digital processing unit to follow variations in the frequency of oscillation of the magnetic signal produced by the sonde.

Abstract: A clock management control circuit of the present invention is a clock control circuit for supplying a valid clock signal to a target circuit in accordance with a system clock signal. When a valid input instruction signal indicating timings of data input to the target circuit changes from a disabled state to enabled state, the supply of the clock signal to the target circuit starts in accordance with the system clock signal, and if a valid output instruction signal indicating timings of data output from the target circuit changes from the enabled state to disabled state, the supply of the clock signal is stopped after a lapse of a predetermined time period set externally. The clock control circuit for supplying the valid clock to the target circuit can therefore be used in common for a variety of waveforms of a valid input flag and a valid output flag.

Abstract: A precise downhole clock that compensates for drift includes a prescaler configured to receive electrical pulses from an oscillator. The prescaler is configured to output a series of clock pulses. The prescaler outputs each clock pulse after counting a preloaded number of electrical pulses from the oscillator. The prescaler is operably connected to a compensator module for adjusting the number loaded into the prescaler. By adjusting the number that is loaded into the prescaler, the timing may be advanced or retarded to more accurately synchronize the clock pulses with a reference time source. The compensator module is controlled by a counter-based trigger module configured to trigger the compensator module to load a value into the prescaler. Finally, a time-base logic module is configured to calculate the drift of the downhole clock by comparing the time of the downhole clock with a reference time source.

Abstract: The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.

Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of ?90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.

Abstract: The invention relates to a clock signal correction method, and to a clock signal input/output device into which a clock signal or a signal obtained therefrom is input and transmitted to a frequency divider, wherein a signal output by the frequency divider is transmitted to a signal integrator, and wherein a signal output by the signal integrator is transmitted to a first signal comparison circuit, wherein the signal output by the frequency divider is additionally transmitted to a second signal comparison circuit, and wherein the clock signal input/output device additionally comprises a signal input circuit for outputting a clock output signal as a function of a signal output by the first signal comparison circuit, and of a signal output by the second signal comparison circuit.

Abstract: A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that several sampling values of a bit cell transmitted with the received signal are distributed time-wise one after the other onto several output connections of the commutator device and emitted there in the form of corresponding intermediate signals. A first circuit combines a first group of intermediate signals of the commutator device into a first uniting signal, which serves as the basis for data recovery or comprises the recovered data signal, while a second circuit combines a second group of intermediate signals of the commutator device into a second uniting signal, which serves as the basis for clock recovery. The second uniting signal is fed to a phase regulator arrangement, which, dependent on this, sets the sampling phases assigned to the individual output connections of the commutator device.

Abstract: A current driving apparatus includes a first square wave generator (100), a second square wave generator (200), an FET (Field Effect Transistor) (3), and a power supply (9). The first square wave generator has an output connected to the second square wave generator's input. The second square wave generator has an output connected to the FET gate. A current clamping resistor (11) is provided between the FET source and the power supply. The FET drain provides current to a possible load (not shown). The first square wave generator generates a low frequency square wave signal for timing control, and the second square wave generator generates a high frequency square wave signal for amplitude control.

Abstract: A bit-rate independent optical receiver and a method thereof. In the bit-rate independent optical receiver, an optoelectric converter converts an input optical signal to an original electrical signal, a bit rate identifying unit forms a resultant signal by performing an exclusive-OR (XOR) logic operation on the original electrical signal received from the optoelectric converter and a second signal corresponding to the original electrical signal delayed by a predetermined quantity of time, and detects a bit rate from the resultant signal, a reference clock generator generates a reference clock signal according to the detected bit rate, and a clock and data recovery circuit recovers a clock signal and data from the input signal according to the reference clock signal.

Abstract: A method of transmitting digital signals which are passed via a communication system by means of a retimer between an input and an output, whereby according to the invention the data packet applied to the input is scanned with respect to the individual bits and within the individual bits and preferably at the center and the scanned data level is transmitted immediately to the output.

Abstract: A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the output of the integrator reaches a pre-specified threshold and gating circuits which gate the output of the crystal oscillator to the output terminal only when the threshold circuit has reached the specified threshold.

Abstract: The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.

Abstract: An adaptive lock position circuit includes a jitter distribution extremity detector and a phase shifting circuit. The jitter distribution extremity detector receives an input data signal and is operable to compare the input data signal with one or more clock signals derived from a recovered clock signal from a clock and data recovery (CDR) circuit to generate one or more control signals that define the boundaries of a jitter extremity detection window. The phase shifting circuit is coupled in a feedback loop with the jitter distribution extremity detector and receives the one or more control signals from the jitter distribution extremity detector and also receives the recovered clock signal. The phase shifting circuit is operable to shift the phase of the recovered clock signal as a function of the one or more control signals to generate a retiming clock signal such that an edge of the retiming clock signal is interpolated within the jitter extremity detection window.

Abstract: A data sampling apparatus includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a strobe signal by a second delay amount which is larger than the first delay amount, and a plurality of timing comparators for sampling a plurality of data signals delayed by the plural stages of first variable delay elements by the strobe signal delayed by the second variable delay element of the same stage, wherein the timing comparator includes a dynamic D-FF circuit for latching and outputting the data signal by its parasitic capacitance based on the strobe signal, a buffer for delaying the strobe signal, and a positive feed-back D-FF circuit for latching and outputting the output signal outputted by the dynamic D-FF circuit by its positive feed-back circuit based on the strobe signal delayed.

Abstract: Calibration targets are generated for lenticular printing. A method involves generating a square wave at a frequency determined by a target pitch for the lenticules. Then filtering the square wave to eliminate aliased harmonics having regard to a Nyquist frequency determined by the resolution of the printer and the required calibration precision. The resulting spatial domain square wave is printed onto a lenticular sheet to produce a calibration target. The targets are used to determine the true pitch of lenticules on a lenticular sheet.

Abstract: A clock recovery circuit includes plural stages of first variable delay elements for sequentially delaying a data signal by a first delay amount, plural stages of second variable delay elements for sequentially delaying a clock signal by a second delay amount which is larger than the first delay amount, a plurality of timing comparators for sampling a plurality of the data signals delayed by the plural stages of first variable delay elements with the clock signal delayed by the second variable delay elements of the same stages, a plurality of EOR circuits for performing exclusive OR operation on a pair of sampling results by a pair of the sequential timing comparators, and a recovery variable delay circuit for delaying the clock signal based on the operation result of the plurality of EOR circuits.

Abstract: A method and system is provided for clock/data recovery for self-clocked high speed interconnects. A data signal is received and then equalized. The equalized data signal then provides the trigger to separate “ones” and “zeros” one-shots. The equalized Manchester data signal is also integrated, compared with a threshold value to determine the negative and positive peaks of the data signal. Then after the appropriate peak is determined, a mid-bit signal is sent as input to a set-reset flip-flop which thereby outputs an asynchronous recovered non-return to zero signal. This asynchronous recovered non-return to zero signal then provides an enable input to the “ones” one-shot and the complementary asynchronous recovered non-return to zero signal provides an enable input to the “zeros” one-shot. The “ones” one-shot outputs a “ones” clock signal and the “zeros” one-shot outputs a “zeros” clock signal. These two signals are verified and a recovered clock out signal is provided.

Abstract: A bit rate control apparatus having a delay unit for delaying an input signal received in an optical receiver in an optoelectrically-converted state; a DC level outputting unit for exclusively OR'ing the input signal with the delayed signal outputted from the delay unit; an A/D converting unit for A/D converting a DC level outputted from the DC level outputting unit; a clock/data reproducing unit for reproducing clocks and data based on a bit rate control signal; and a control unit for calculating a variation in the DC level at every interruption timing, which is previously set, based on the A/D converted signal, and for determining whether the DC level variation occurs under the influence of temperature or due to a variation in bit rate based on a difference between the calculated DC level variation from a predetermined variation limit.

Abstract: The present invention discloses a frequency signal enabling apparatus and the method thereof for filtering noises and glitch when entering an operating mode from a power-saving mode. When the pulse width of the input frequency signal is smaller than the threshold pulse width, it will be considered as a noise and be filtered out. When the high-level pulse width of the input frequency signal is greater than the threshold, a first short pulse will be generated. When the low-level pulse width of the input frequency signal is greater than the threshold, a second short pulse will be generated. The relative position of the first short pulse and the second short pulse will be used to reconstruct the frequency signal, and the reconstructed frequency signal may serve as the operating frequency of the microprocessor or other digital IC.

Abstract: A circuit configuration regenerates clock signals. The circuit configuration includes an input differential amplifier, first and second inverters, and an offset compensation circuit. The input differential amplifier generates first and second amplified signals in response to first and second differential input clock signals. The first and second inverters generate a first and a second differential output clock signal. The offset compensation circuit controls the difference between the two output clock signals to zero or to a constant value. As an alternative to or in supplementation of the offset compensation circuit, it is possible to provide a control circuit for driving the two inverters, which shifts the input pulse shapes of the inverters to the optimum switching point of the inverters. The circuit configuration enables a regeneration of clock signals with simultaneous equalization of pulse distortions.

Abstract: Disclosed is a device for recovering a burst-mode clock. The burst-mode clock recovery device includes a delay unit and a logic element. A reference clock is produced by implementing a logic operation with respect to a signal output from signal forming device and a signal output from the signal forming device and delayed by a delay unit. A duty of a final output signal is corrected by implementing and AND operation with respect to the generated reference clock and an output from feedback device.

Abstract: A clock skew tolerant clocking scheme addresses both the max-time and min-time problems by using dual transparent pulsed latches operated by complementary phases of the clock signal. According to the present invention, the first pulsed latch is triggered by a first pulse derived by the leading edge of a clock signal pulse and the second pulsed latch is triggered by a second pulse derived from the trailing edge of the clock signal. By employing transparent pulse latches, the clock skew tolerant clocking scheme of the invention provides max-time clock skew tolerance. In addition, unlike prior art solutions, according to the invention, the transparency periods of the dual complementary pulsed latches do not overlap so there is never a transparency period between two successive stages and, therefore, there is no opportunity to introduce the min-time, or racing condition, problem.

Abstract: A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

Abstract: Circuits and methods align an internal signal with an external signal. A phase lock loop network receives the external signal to generate phase lock loop signals. A programmable ratio decoder provides a code. An alignment unit generates the internal signal based on at least one of the phase lock loop signals. The alignment unit aligns internal signal with the external signal based on the code.

Abstract: A method and an apparatus are provided for filtering a substantially square wave signal. At least a portion of the substantially square wave signal is applied to a first filter adapted to pass a range of frequencies adjacent the fundamental frequency and produce a first filtered signal. At least a portion of the substantially square wave signal is also applied to a plurality of second filters, where each of the second plurality of filters is adapted to pass a range of frequencies adjacent an odd harmonic component of the fundamental frequency and produce a second filtered signal. The first signal and the plurality of second filtered signals are combined to produce a representation of a square wave signal having a frequency substantially corresponding to the fundamental frequency.

Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

Abstract: A device generating a pulse signal includes at least one first register which stores waveform data therein, a pulse signal generation unit which generates a pulse signal in accordance with the waveform data of the first register, a control unit which is connected to a bus, and is controlled by control signals supplied from the bus, and a signal line which is separate from and independent of the bus, and is connected to the control unit, wherein the control unit updates the waveform data of the first register in response to a signal that is externally supplied through the signal line.

Abstract: A method and apparatus are disclosed for generating a second clock signal, having a second effective clock frequency, from a first clock signal, having a first effective clock frequency. Clock pulses of the first clock signal are counted to generate a count value. When the count value reaches a predetermined blanking value, a blanking signal is generated. The blanking signal blanks at least one clock pulse of the first clock signal. The process is repeated multiple times at a predetermined rate corresponding to the predetermined blanking value to generate the second clock signal.

Abstract: A method of providing real time digital pulse shaping includes: receiving a digital pulse input signal (31); applying the digital pulse input signal to first (33, 34, 35) and second (32, 36, 37) processing channels, the first processing channel including a CONCAVE shaper (34) and the second processing channel including a CONVEX shaper (36); applying selected digital control parameters to the CONCAVE shaper (34) and the CONVEX shaper (36) to produce desired first and second weigthing functions, and superposing the first and second weighting functions to produce a desired overall weighting function.

Abstract: A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.

Abstract: A reproduced signal waveform processing apparatus is provided. The apparatus includes an A/D converter for sampling a reproduced signal at a reproducing clock having a predetermined oscillation frequency; a first equalizer for equalizing a digital reproduced signal from the A/D converter; a second equalizer connected in series with the first equalizer for further equalizing the digital reproduced signal from the first equalizer; a phase frequency controller for detecting a phase frequency error between the digital reproduced signal from the first equalizer and the reproducing clock signal, and outputting a control signal on the basis of a result of the detection; and a variable frequency oscillator for varying the oscillation frequency in accordance with the control signal.