Abstract: A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.

Abstract: A voltage-controlled oscillator circuit includes a ring oscillator circuit for generating a signal having a series of pulses. The signal with the series of pulses is ac coupled to a filter circuit which converts the series of pulses into a substantially sinusoidal signal which is substantially symmetrical about the reference potential of the system. The sinusoidal signal is applied to an amplifier which converts the sinusoidal signal into a square wave. Because the square wave is generated as an amplified sine wave, it exhibits a high degree of symmetry, i.e., it has a highly accurate 50-50 duty cycle, which makes it applicable in demanding settings such as serving as a clock signal in a high-speed microprocessor system in which both rising and falling edges of the clock signal are used to synchronize events.

Abstract: In the process for converting a frequency signal to a DC voltage according to the invention a first and a second output voltage signal (UA1, UA2) are generated from the frequency signal. Each of the output voltage signals is a sequence of rectangular pulses the pulse sequence frequency of which is equal to a frequency f of the frequency signal. These are converted with a first and a second lowpass filter to a first DC voltage signal and a second DC voltage signal, respectively, with the second DC voltage signal being used to influence the pulse width T0 of the rectangular pulses of at least the first output voltage signal. This makes it possible to build a simple frequency-to-voltage converter using cost-effective standard monoflops in which a largely linear correlation between frequency f of the frequency signal and the magnitude of the first DC voltage signal is realized in a simple manner.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: Chewing gum products and methods for manufacturing same are provided. The gum includes a center having a water-soluble portion and a water-insoluble portion and including hydrogenated starch hydrolysate and no glycerin. A coating encloses the center.

Abstract: A waveform shaping circuit is provided so that the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency. An inverter which receives the clock pulses through an alternating current coupling capacitor is provided with a non-linear limiter element for limiting an amplitude of an output symmetrically on positive and negative sides thereof. A first current-limiting impedance and a second current-limiting impedance are connected between a power supply side terminal of the inverter and a power supply bus and between a grounding side terminal of the inverter and a grounding bus, respectively.

Abstract: The data and clock regeneration circuit can be completely integrated in a chip. The circuit has, in series, two independent PLL regulating stages which are optimally adjustable separately. The first PLL regulating stage has a large bandwidth and is optimized for maximum jitter tolerance and the second PLL regulating stage has a small bandwidth and is optimized for minimum jitter transfer. The circuit is suitable for use, for example, in transceivers for ATM, SONET, and SDH applications with signal transmission links in the Gbit range.

Abstract: A noise reduction circuit useful as a clock restoration circuit includes a DC removal circuit for removing a DC level from an input pulse train, an integrator for integrating the input pulse train after a DC level has been removed, a comparator for comparing the integrator output with a threshold value (Vmp) to detect for a missing pulse, a pulse generator inserting into the input pulse train an additional pulse delayed with respect to any missing pulse, and an output circuit for generating an output pulse train from the integrator output.

Abstract: To provide a clock and data recovery circuit which facilitates alteration of the frequency range and adjustment of characteristics.

Abstract: A phase stable clock circuit includes a phase gate having track-and-hold (T/H) circuits with each T/H circuit receiving a phase shifted continuous sinusoidal signal of predetermined phase and a control input signal to capture and hold phase samples of the sinusoidal signals. In alternative embodiments, a phase correction circuit provides phase correction values that are added to the held phase values to generate corrected phase values and time-error phase lookup table is used to generate time position correction values. The corrected phase values are applied to the phase gate remove deterministic phase errors to generate an output signal with a predetermined startup phase relative to the control input signal transition. The phase error-to-time lookup table adjusts the time placement of waveform record samples after the acquisition of the samples.

Abstract: A duty cycle correcting circuit is described having a first capacitor connected between a first node and a reference node and a second capacitor connected between a second node and the reference node. When the duty cycle of the output clock signal is greater than 50% the voltage across the second capacitor decreases thereby increasing the charging rate of the first capacitor, decreasing the discharging rate of the first capacitor, and restoring the output duty cycle to 50%. When the duty cycle of the output clock signal is less than 50% the voltage across the second capacitor increases thereby decreasing the charging rate of the first capacitor, increasing the discharging rate of the first capacitor, any restoring output duty cycle to 50%.

Abstract: Even if duty is shifted to either a state in which an “H” period is long or a state in which an “L” period is long, the duty is recovered to about 50%. A duty correction circuit corrects a duty shift or deviation developed when analog complementary cycle signals having a phase difference of about half cycle therebetween and a duty ratio of about 50% are converted to logic levels, through the use of, for example, serial two-stage NAND gate static latches.

Abstract: An oscillator circuit produces first and second oscillating logic signals that are of a same frequency and are non-overlapping in a first logic state. This oscillator includes a flip-flop circuit to produce third and fourth oscillating logic signals of opposite polarities, this flip-flop circuit being driven by first and second driving logic signals. First and second logic gates receive the third and fourth logic signals and produce the first and second logic signals, the logic state transitions in the first and second logic signals being produced as a function of the logic state transitions of the third and fourth logic signals. The first and second logic gates are organized so as to introduce a delay into the transitions from a second logic state to the first logic state, in the first and second logic signals, with respect to transitions in the third and fourth logic signals.

Abstract: A bit rate control apparatus and method for an optical receiver capable of avoiding an erroneous determination of the bit rate occurring under the influence of temperature.

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract: Differential clocks CLKa, CLKb are supplied, and controlled in phase by a phase control circuit. Based on differential clocks CLKa, CLKb that have been controlled in phase by the phase control circuit, a delay-locked loop (DLL) generates 16-phase clocks CLK1 through CLK16, and supplies generated 16-phase clocks CLK1 through CLK16 to phase comparators PD2. A control voltage V2 generated by a phase control signal based on phase difference information (UP/DOWN signal) outputted from phase comparators PD2 is supplied via a feedback loop to the phase control circuit, which uses control voltage V2 for the control of the phase of differential clocks CLKa, CLKb.

Abstract: A semiconductor integrated circuit is disclosed, in which a plurality of circuit blocks each having a clock distribution line pattern, a first signal path for transmitting the data signal from a first circuit block to a second circuit block, a second signal path for transmitting a clock signal, at least a first buffer circuit connected to the first signal path to constitute the first signal path, and a second buffer circuit connected to the second signal path to configure the second signal path are formed on a single semiconductor chip. The first and second signal paths have the same length, and data and clock are transmitted in parallel to each other on the first and second signal paths, respectively. The second circuit block latches the received data by the clock transmitted in parallel.

Abstract: A pulse delay circuit that provides a delay for a pulsed input signal that does not vary significantly under changing temperature, power supply voltage or process conditions. The delay provided by the pulse delay circuit is not significantly limited in duration. The pulse delay circuit includes a pulse detector, an RC delay circuit and a pulsed signal generator. The delay is primarily determined by the RC time constant of the RC delay circuit.

Abstract: A system for processing a signal s(t) from a sensor to recover sensed signal information within the bandwidth of the summation signal, wherein the signal s(t) includes a sensed signal m(t) and an offset signal having a first frequency f1. The system comprises: a sampling device for sampling the signal s(t) at a second frequency f2 that is a multiple of the first frequency f1, to create a sequence of sampled values; and an averaging device for averaging the sequence of sampled values to provide a sequence of averaged sampled values indicative of the sensed signal m(t).

Abstract: A clock generator has a duty cycle correction circuit that adjusts the duty cycle to 50%. A modulator is an inverter with extra source-limiting transistors in series to the power and ground supplies. A control voltage of about Vcc/2 is applied to the source-limiting transistors, causing them to operate in the linear region with limited current. A slow-slew output from the modulator is buffered by a driver. The driver output is filtered by a linear detector with a series resistor and input capacitor. The detector output is compared to a reference voltage of Vcc/2 by an error amp. The error amp generates the control voltage fed back to the modulator. An output capacitor creates a dominant pole with the error amp to ensure stability. A variable-threshold gate can be added between the driver output and the detector to separately adjust the measurement threshold voltage from the reference voltage to the error amp.

Abstract: One clock is selected from a plurality of clocks by a selector through programming. Clock lines are connected to the outputs of clock buffers connected to the selector. Programmable connector elements are connected onto these lines, and flip-flops and regulation loads are connected thereto. The programmable connector elements are selected through programming. This construction can realize a clock distributing circuit in a programmable logic device, which can suppress an increase in skew and can reduce a clock line wiring area.

Abstract: A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

Abstract: Methods and apparatuses consistent with the present invention recover a clock signal from a variable bit rate data signal by estimating, in the time domain, the bit rate of the data signal, and based on the estimated variable bit rate, determining a center frequency of a narrow-band filter for extracting the clock signal from the data signal. A clock recovery circuit consistent with the present invention extracts a clock signal from a variable bit rate data signal by estimating a minimum time interval between transitions in the data signal, generating a plurality of pulses that correspond respectively to transitions in the data signal, adjusting the duration of each of the pulses based on the estimated minimum time interval and inputting into a narrow-band filter the adjusted pulses, determining a center frequency of the narrow-band filter based on the estimated minimum time interval, and extracting in the narrow-band filter the clock signal from the adjusted pulses.

Abstract: A clock recovery circuit is provided for use in a memory with a clock synchronized interface, wherein an external clock is temporarily intercepted to shorten lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, receiving the external clock, for generating reference clocks, a control circuit comparing phases of the external clock and of the reference clocks and detecting the number of delay stages required for locking in, and a latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected, the generation of internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

Abstract: A device for the regeneration of a clock signal uses a reference clock signal given by an internal oscillator to measure the number of reference clock pulses between the first two synchronization pulses sent by an external serial bus or USB at the beginning of each transaction. Thus a rough measurement N is obtained of the USB clock signal to be regenerated. The delay of each of these two synchronization pulses with respect to the previous pulse of the reference clock signal is measured. This delay is computed with respect to an internally defined time unit. On the basis of the measurement of these two delays, and the measurement of the number of reference clock periods, and knowing the measurement n of the period of the reference clock signal in the time unit, the period of the USB clock signal to be regenerated is computed with precision.

Abstract: A clock generator which provides a stable, programmable pulse width output clock signal based on an input clock signal. The clock generator provides a leading edge of an output clock signal in response to a leading edge of an input clock signal. The trailing edge of the output clock signal is conditioned on feedback of the leading edge output clock signal with the trailing edge of the input signal.

Abstract: A method and circuit which allow for pre-emphasis of a high frequency on-chip signal have been developed. The circuit is configured to receive a digital signal from an on-chip source as input for a predriver stage. The method and circuit may use a dual or single predriver stage to equalize the signal when a transition in the value of the digital signal is detected. The single predriver stage circuit equalizes the signal with decreased power and area requirements for greater efficiency.

Abstract: A tuning signal is injected into an LC tank circuit oscillator, e.g., through an impedance (either reactive, inductive, capacitive and/or resistive) to tune the phase and/or frequency of the LC tank circuit oscillator. A negative resistance is included in parallel with the LC tank circuit oscillator to compensate for losses in the LC tank circuit, and a bias signal is provided to power the operation of the LC tank circuit. The tuning signal may be, e.g., an AC signal or a data signal. The tuning signal is injected into the LC tank circuit using capacitors, resistors, FET or bipolar transistors, and/or inductors. Multiple LC tank circuit oscillators may be used to provide stable multiplied or divided frequencies. In this case, the output of one LC tank circuit oscillator may be used to tune another LC tank circuit oscillator.

Abstract: In a clock reproduction and identification device, a clock extraction circuit extracts a transmission line clock from input data and a phase synchronization section reproduces an identification clock synchronized with the transmission line clock in frequency and phase. An identification section identifies the input data based on the identification clock.

Abstract: There is provided a method of controlling a clock, including the steps of (a) receiving an external clock signal, (b) calculating a first period of time defined as (T1−T2) wherein T1 is a cycle of the external clock signal, and T2 is a period of time during which the external clock signal is transmitted through devices generating skew to the external clock signal, (c) stopping the external clock signal to be transmitted by the first period of time, and (d) driving the external clock signal to thereby turn the external clock signal into an internal clock signal. The method makes it possible to detect delay in a clock signal, and generate no delay error inherent to a digital circuit.

Abstract: Circuits for the restoration of a drooped signal are disclosed. In the asynchronous mode circuit, the drooped signal can be restored by detecting the peak of the positive amplitude and the peak of the negative amplitude and take the difference between the two peaks. This difference signal is fed back the equalizer. In the synchronous mode circuit, the drooped signal is sliced and passed to a regeneration circuit. The regeneration circuit uses reference voltage signals and phase information from the slicer to generate a regenerated signal. The regenerated signal is compared with the equalized signal to generate a difference signal, again fed back to the equalizer. The sliced signal is also fed to a clock recovery circuit which recovers the clock signal embedded in the received signal. The two circuits can be combined to provide an optimal circuit for the restoration of a drooped signal.

Abstract: The signal regeneration circuit recovers a digital signal from an input signal that is supplied via metallic isolation (galvanic separation). The circuit has two input terminals for the input signal and one output terminal for the recovered digital signal. A current direction sensor detects the current direction prevailing between the input terminals and outputs the signal in accordance with the last prevailing current direction. The circuit is advantageously used in connection with digital circuits that require potential isolation at their input terminals.

Abstract: A circuit arrangement, in particular in DECT systems, for the regeneration of an input signal containing characteristic digital data sequences with N>1 allowed discrete values per digital position, having conversion means that produce a regenerated digital output signal from the comparison of the input signal with at least N−1 reference level, at least one integration element for obtaining the at least one N−1 reference level by integration of the segments of the input signal consisting of the characteristic data sequences, a drivable switching means for the activation or, respectively, deactivation of the integration of the input signal, a checking means that respectively activates the integration process by driving the switching apparatus at the beginning of a characteristic data sequence in the signal curve and, when the end of the data sequence is recognized, deactivates it again in order to avoid a shifting of the at least N−1 reference levels, as well as at least one delay elem

Abstract: An improved clock recovery circuit is disclosed. A first inverter pulse generator and a second inverter pulse generator for receiving nonreturn-to-zero (NRZ) data and in response thereto generating a signal having a frequency (f) is provided. A differential pair that is coupled to the first and second inverter pulse generators for mixing the signal provided by the pulse generators and a clock signal is provided.

Abstract: A comparator compares phases of an input data supplied from an input terminal and a synchronizing clock signal output by a variable counter, and outputting a comparison result signal indicative of any of a "lead", a "lag" and a "non-detection" of the edge of the input data with respect to the up edge of the synchronizing clock signal. A state detector circuit detects the numbers of "leads" and "lags" in comparison result signals output by the comparator, and outputting a state detected signal indicative of any of "the number of leads is larger", "the number of lags is larger" and "the number of leads is equal to the number of lags". A dividing ratio selection circuit outputs a dividing ratio signal indicative of any of a "dividing ratio smaller than a reference dividing ratio", a "dividing ratio greater than the reference dividing ratio" and the "reference dividing ratio", based on the comparison result signals output by the comparator and state detected signals output by the state detector circuit.

Abstract: In an optical recording/reproducing apparatus having a 3T-component compensating circuit, among the level-shifted radio frequency signals shifted during a reproduction of recorded data from an optical disc, the level of a 3T component is compensated for, so that error correction may be carried out by a digital signal processor. The optical recording/reproducing apparatus having a 3T-component compensating circuit for reproducing recorded data includes a peaking circuit for amplifying a 3T component from among RF signals outputted from a pickup. A compensating circuit compensates a level-shifted 3T component shifted during the amplification by the peaking circuit. A digital signal processor carries out error correction for the 3T component after the compensation by the compensating circuit.

Abstract: A timing circuit can be selectively configured to generate output pulses in response to either the falling edges or the rising edges of an input signal. The timing circuit includes a multiplexer, an output pulse width controller (OPWC), a gating circuit (GC) and a latch circuit. The OPWC includes a delay circuit that can be configured to provide a predetermined delay .delta. that can be larger than the pulse width of the input signal pulses. The multiplexer is connected to receive a first input signal and an inverted version of a second input signal. The first input signal is used in a rising edge triggered mode, whereas the second input signal is used in a falling edge triggered mode. The multiplexer receives a mode signal to selectively output one of the input signals to the GC. The GC is also connected to receive the output signal from the OPWC.

Abstract: A scanner circuit for digital signals with high data rate includes an arrangement for timing pulse recovery formed by a scanner stage for scanning a digital signal and an edge discriminator that evaluates at least one edge of the scanned digital signal and that controls a digital oscillator that generates a data timing signal.

Abstract: A high-speed current switch has complementary switching stages for collectively producing a square-wave output current. Spurious currents and charging delays caused by intrinsic capacitances in one stage substantially cancel those in the other stage.

Abstract: A low-skew single-ended to differential signal converter includes a conventional single-ended to differential converter that drives a pair of output driver circuits. Each driver circuit is formed from a pair of transfer gates that receive a supply voltage or a reference voltage, respectively. The transfer gates transfer only a portion of the supply or reference voltage in response to the inverted signal from the conventional converter. The portion of the transferred voltage is insufficient to trigger output members in the output drivers and the output voltages from the drivers do not transition in response to the noninverted signal. The inverted signal causes the outputs of the transfer gates to transition fully, triggering the respective output inverters. Because the inverted signal causes transitions of both of the output signals, skew of the output signals is reduced relative to skew of the inverted and noninverted signals.

Abstract: A delay lock loop circuit for a semiconductor memory element generates a synchronized internal clock signal by receiving an external clock signal as an input. The delay lock loop circuit generates a clock signal having a very fast period in order to enhance speed of data being synchronized by a clock signal. The delay lock loop (DLL) circuit includes: a N frequency dividing means which respectively receives the external signal having the frequency f, and generates a signal having a frequency f/N; a N delay lock loop means which respectively receives the signal having the frequency f/N generated from the N frequency dividing means, and maintains it for a predetermined period; and a merging means which performs a logic operation on each output pulse signal generated from the N delay lock loop means, and generates the synchronised internal signal.

Abstract: In order to reproduce a clock having little jitter in the clock reproduction in data transmission, a reproduced clock is outputted by sampling an inputted base band signal by using sampling pulses by means of a sampler and shaped by means of a flip-flop. Errors of the sampling timing are detected by sampling the base band signal two times with a predetermined interval for each bit and by comparing magnitude of fluctuations of preceding sampled values with magnitude of fluctuations of succeeding sampled values. A clock reproduced circuit acts as a phase synchronizing loop circuit during bit synchronizing signal periods, while during data signal periods errors of the sampling timing are corrected by using an output of the error detection.

Abstract: An integrated circuit, configured for connection to an SCSI bus includes a strobe assertion edge triggered glitch filter. Input data latches are controlled by the strobe assertion edge gated with a strobe enable signal and the inverted and delayed Q output of a flip-flop. Once a valid strobe assertion edge is detected, it is used latch data bus signals into the data latches. Following a defined delay period through a delay stage, the data latch strobe is masked from any further transition until the strobe enable signal is again affirmatively asserted by an SR latch. The masking period is defined upon receipt of a valid strobe assertion edge and maintained for a first period by the combination of the SR latch, a flip-flop and a delay stage. The latch strobe mask is maintained for a second period by a strobe masking extension circuit made up of series-connected flip-flops.

Abstract: A closed loop clock delay adjustment system measures the drift between the delay introduced by clock buffers and by delays inserted at the device data input pins. The system uses a reference delay at the input of a measurement flip-flop. The reference delay is defined to be an approximate average of the delays at the data input pins. An external clock signal is coupled to the input of the reference delay. The output of the reference delay is coupled to the data input of the measurement flip-flop. The external clock signal is also coupled to the input of a variable clock delay buffer sub-circuit. The output of the variable clock delay buffer is coupled to the clock signal input of the measurement flip-flop. In operation, the measurement flip-flop compares the variable clock delay buffer output signal with the clock signal delayed by the reference delay. If the variable clock delay buffer output signal is delayed more than the reference delay output signal, the variable clock delay is decreased.

Abstract: Starting from an input signal (data) and a clock signal (clk), this device supplies an output signal (CKREF0) identical to the input signal but resynchronized with the clock signal. It comprises two cascaded D-type flip-flops (63, 65), the clock signal of the second flip-flop being inverted (62) with respect to that of the first flip-flop. The first flip-flop has its output coupled to the data input of the second flip-flop via a multiplexer (64), which is controlled by a signal (d-Ph) containing information about the phase relationship between the input signal and the clock signal, in such a manner that either input signal or the signal from the first flip-flop is applied to the input of the second flip-flop. This device can be used in a known phase control loop comprising an oscillator whose frequency is controllable, a frequency divider, and a phase comparator.

Abstract: Described is a circuit for receiving a differential input signal at two substantially symmetrically built up current paths and for providing an output signal therefrom. At least one current path comprises means for adjusting the timing information of the input signal to the timing information of the output signal. The adjustment can be accomplished by modifying a voltage level in the respective current path until the timing information of the output signals at least substantially represents the timing information of the input signal, e.g. by modifying an impedance or a current in the respective current path. The adjusting of the timing information is executed by applying a defined input signal with a known timing information, comparing the timing information of the resulting output signal with the timing information of the input signal, and modifying at least one voltage level in at least one of the current paths until the timing information of the output and input signals at least substantially match.

Abstract: A receiver is described for recovering digital data from a transmitted balanced signal where the balanced signal includes a first plurality of pulses, each pulse having a first pulse width. The receiver includes an input circuit, a buffer circuit, and a calibration circuit. The input circuit receives the transmitted signal and includes a first differential amplifier for amplifying a first signal, a second differential amplifier for amplifying a second signal, and a converter for receiving the amplified first signal and amplified second signal and then generating a third signal. The first and second signals are included within the transmitted signal. The buffer circuit receives and buffers the third signal, and outputs a fourth signal including a second plurality of pulses which have a second plurality of pulse widths. The calibration circuit receives the fourth signal.

Abstract: A method for generating an output signal of desired polarity from an input periodical signal of frequency f1 via a clock signal of frequency f2, wherein f2 is substantially greater than f1, is provided. The input periodical signal includes a cyclic duration T1 of a first logic state and duration T2 of a second logic state. The method includes the steps of (1) counting pulses N of the clock signal during T1; (2) counting pulses M of the clock signal during T2; (3) generating the output signal by inverting the input periodical signal as M being larger than N and an activated state of select signal are determined.

Abstract: A circuit and method for synchronizing a data signal to one of a plurality of clocks. The clock may include (i) a pulse generator configured to generate two pulses separated by a delay, (ii) a clock generator configured to generate the plurality of clocks, and (iii) a logic circuit configured to select the clock for synchronizing the data signal.