Abstract: Of synchronous circuit cells such as flip-flops, some are of blocked type and others remain unblocked. In a semiconductor integrated circuit according to the present invention, a clock generating circuit is independently provided for each of a plurality of the unblocked synchronous circuit cells for a clock input thereto, in order to control clock skews and achieve a lower power consumption. The clock generating circuit is independently connected to each of a plurality of functional blocks comprising a plurality of the blocked synchronous circuit cells for the clock input thereto.

Abstract: Receiving units with inputs that may be ground-terminated and with inputs that are selectively ground-terminated or non-ground terminated are enabled with signal level shifting and a termination mode selection input. In a first exemplary implementation, a receiving unit is capable of having ground-terminated inputs. However, common mode voltage of the signal that is input to decoding data recovery circuitry is above ground because the input signal may be level shifted in between the ground-terminated inputs and the decoding data recovery circuitry. In a second exemplary implementation, a mode selection is accomplished by switching a voltage divider into operation and bypassing a level shifter for a non-ground terminated mode. For a ground terminated mode, the voltage divider is switched out of operation and the level shifter is switched into operation for its signal output to be decoded. Pre-amplification may also be employed to improve signal strength.

Abstract: In one embodiment, a clock multiplier circuit is coupled to receive an input signal and is configured to generate an output clock signal. The clock multiplier circuit is configured to generate a number of pulses on the output clock signal responsive to an edge of the input signal, wherein the pulses have a width that is independent of the number of pulses generated and independent of the frequency of the input signal. The number of pulses is selectable. In another embodiment, the clock multiplier circuit includes a circuit and an oscillator. The circuit is configured to cause a number of pulses on the output clock signal of the clock multiplier circuit responsive to a control signal. The oscillator is configured to generate a stream pulses having the width, wherein the circuit is coupled to receive the stream of pulses.

Abstract: A hierarchal block for an integrated circuit includes a plurality of sequential registers, a plurality of clock cluster buffers, and a plurality of clock pins. The sequential registers are grouped into a plurality of clusters. Each of the clock cluster buffers is associated with a respective one of the clusters such that a clock net connection can be made to a clock gate input of each of the registers in the respective one of the clusters. Each of the clock pins is associated with a respective one of said clock cluster buffers such that a clock net connection can be made between each clock pin and the respective one of the clock cluster buffers.

Abstract: An anti-jitter circuit has an integrator storage capacitor. A charge pump derives from an input pulse train at least one charge packet during each cycle of the input pulse train and supplies the charge packets to the storage capacitor. A controlled current sink operating in conjunction with a high impedance low pass filter continuously discharges the storage capacitor to create a sawtooth voltage waveform having a mean d.c. voltage level. A differential comparator compares the sawtooth voltage waveform with the mean d.c.

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 &mgr;m CMOS technology.

Abstract: A physical random number generator has a bi-stable latch that operates to latch a random number bit in response to a reception of a voltage oscillating signal. When a switching device is in a first operating state, the bi-stable latch is deactivated and an oscillator is activated to generate one or more unpredictable voltage oscillation signals, which may provoke the bi-stable latch into a metastable state upon an activation of the bi-stable latch. When the switching device is in a second operating state, the oscillator is deactivated and the bi-stable latch is activated to latch a random number bit as a function of the unpredictable voltage oscillation signals, the randomness of the random number bit being enhanced by any provoking of the bi-stable latch into the metastable state by the voltage oscillating signal(s).

Abstract: A device for the regeneration of a clock signal uses a reference clock signal given by an internal oscillator to measure the number of reference clock pulses between the first two synchronization pulses sent by an external serial bus or USB at the beginning of each transaction. Thus a rough measurement N is obtained of the USB clock signal to be regenerated. The delay of each of these two synchronization pulses with respect to the previous pulse of the reference clock signal is measured. This delay is computed with respect to an internally defined time unit. On the basis of the measurement of these two delays, and the measurement of the number of reference clock periods, and knowing the measurement n of the period of the reference clock signal in the time unit, the period of the USB clock signal to be regenerated is computed with precision.

Abstract: The present invention comprises: a plurality of output terminals through which a signal from an internal circuit is output; buffer circuits, each provided between one of the plurality of output terminals and the internal circuit; and a delay circuit connected to the specific buffer, the delay circuit delaying the signal from the internal circuit. With this arrangement, it is possible to measure a delay time from an input test signal even when a super-high-speed device is tested.

Abstract: An integrated circuit has a synchronous circuit and an asynchronous circuit. A clock-controlled input register circuit and an output register circuit for storing data are each connected to the synchronous circuit and the asynchronous circuit. Data are transferred from the synchronous circuit into the input register circuit, from where they are transferred into the asynchronous circuit and processed in the asynchronous circuit. Processed data are transferred into the output register circuit. A sequence controller generates a respective control clock signal for the register circuits in a manner dependent on the data processing duration of the asynchronous circuit. This enables a high data throughput between the synchronous circuit and the asynchronous circuit independently of a clock frequency of the synchronous circuit.

Abstract: A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a,14b,14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a,20b,20c, 22a,22b,22c) is inserted in each functional block and bus node.

Abstract: A clock and data recovery circuit includes a phase-shift circuit having a switch, which receives multiphase clocks, for selecting and outputting a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, which receive the plurality of clock pairs output from the switch, for outputting clock signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clocks of the pair; a plurality of latch circuits which receive input data in common; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling clock phase by outputting control signals for controlling the interpolators and/or switch of the phase-shift circuit based upon the filter output.

Abstract: A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.

Abstract: An IC including skew-programmable clock buffers, fixed skew logic, an external interface and a skew controller. Each skew-programmable clock buffer receives a distributed clock signal and provides a corresponding local clock signal having a programmed skew. The fixed skew logic enables permanent programming of static skew values and the external interface enables programming of dynamic skew values. The skew controller selects between the static and dynamic skew values and programs the skew-programmable clock buffers based on selected skew values. In one embodiment, the skew controller is operative to detect a skew over-ride command upon reset of the IC and to select between the static and dynamic skew values based on the skew over-ride command. The programmable memory may be integrated on the IC or externally coupled via the external interface. The fixed skew logic is implemented as any type of permanent programmable block, such as laser-blown fuses, an EPROM, etc.

Abstract: A first delay line for forward pulses and a second delay line for backward pulses are composed of unit delay elements. A state holding section determines the input position of a backward pulse on the second delay line according to the transfer position of a forward pulse transferred along the first delay line. In the unit delay elements constituting the first and second delay lines, the accuracy of synchronization can be improved by increasing the current driving capability of the transistors related to the rising of the pulse signal.

Abstract: There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of −90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.

Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.

Abstract: A circuit configuration regenerates clock signals. The circuit configuration includes an input differential amplifier, first and second inverters, and an offset compensation circuit. The input differential amplifier generates first and second amplified signals in response to first and second differential input clock signals. The first and second inverters generate a first and a second differential output clock signal. The offset compensation circuit controls the difference between the two output clock signals to zero or to a constant value. As an alternative to or in supplementation of the offset compensation circuit, it is possible to provide a control circuit for driving the two inverters, which shifts the input pulse shapes of the inverters to the optimum switching point of the inverters. The circuit configuration enables a regeneration of clock signals with simultaneous equalization of pulse distortions.

Abstract: A clock recovery circuit includes a phase discriminating circuit for discriminating, at every edge of a received data signal, phase lead or phase lag of an identically directed edge of the clock signal, and outputting the phase discrimination signal; an edge detecting circuit for detecting edges of the received data signal, outputting an edge detection signal of a fixed pulse width, delaying the received data signal up to half of the fixed pulse width and outputting the delayed signal; an exclusive-OR gate for outputting, as an edge injection signal, an exclusive-OR signal between the phase discrimination signal and delayed signal; and a voltage-controlled oscillator for variably controlling frequency of ring oscillation by a frequency control voltage, injecting the edge injection signal into the loop of ring oscillation in a period of the fixed pulse width, and outputting a clock signal locked to the received data signal.

Abstract: In a clock and data recovery circuit and method, the clock and data recovery circuit comprises a clock signal generator for generating N clock signals, each clock signal having phase difference of 360/N×K from each other, wherein the N denotes an integer and the K denotes an integer from 0 to N−1, a phase selector for generating an I+2th clock signal out of the N clock signals as a recovered clock signal if an Ith clock signal is on a first state and an I+1th clock signal is on a second state when logic level transition of a received data is detected, wherein the I denotes an integer from 1 to N, and a recovered data generator for generating a recovered data synchronized with the recovered clock signal by using the received data in response to the recovered clock signal output from the phase selector.

Abstract: An apparatus including a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein the output signals each have a frequency and a phase that are dynamically variable. The programmable logic circuit may be configured to generate one or more of the control signals and receive the one or more output signals.

Abstract: Described is a method of converting one representation of a circuit into another. For example, a first network representation adapted for use with an FPGA can be converted into a second network representation adapted for use in a mask-programmable gate array. The method begins with accessing the first network representation, such as a netlist, and identifying signal paths that might be sensitive to race conditions. Representations of delay elements are then inserted into each sensitive signal path. The timing of the modified network representation is then modeled by calculating the delays associated with each signal path. Any differences in the modeled delay values are minimized by modifying one or more of the inserted delay-element representations. In one embodiment, the inserted delay-element representations include stopper cells that maintain the nets to and/or from the delay-element representations.

Abstract: A clock extracting part has a first phase comparator circuit, a first up/down counter, a weighting circuit, a charge pump and a low-pass filter forming a voltage value determining part, and a voltage controlled oscillator circuit. A retiming clock generating part has a second up/down counter and a phase switching circuit. Furthermore, a phase adjusting part has a first counter, a second counter, a second phase comparator circuit and a third up/down counter forming a phase adjusting part. A clock data recovery circuit is formed by said clock extracting part, the retiming clock generating part, the phase adjusting part, and a first-in first-out memory part. Thereby, a clock data recovery circuit is obtained, in which jitter transfer characteristics and jitter tolerance satisfy the standards of both the SONET and SDH.

Abstract: The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.

Abstract: A clock and data recovery circuit includes a phase-shift circuit having a switch, which receives multiphase clocks, for selecting and outputting a plurality of clock pairs from among the multiphase clocks, and a plurality of interpolators, which receive the plurality of clock pairs output from the switch, for outputting clock signals in which delay time is stipulated by time obtained by performing interior division of the phase difference between the clocks of the pair; a plurality of latch circuits which receive input data in common; a phase detecting circuit for detecting and outputting phase, with respect to the clock, of a transition point of the input data from the outputs of the plurality of latch circuits; a filter for smoothing the output of the phase detecting circuit; and a control circuit for controlling clock phase by outputting control signals for controlling the interpolators and/or switch of the phase-shift circuit based upon the filter output.

Abstract: An N-transistor switches a current of a first constant current source by a positive input pulse to generate an output pulse current where an overshoot and an undershoot appear. A P-transistor switches a current of a second constant current source by a negative correction pulse applied at timing of occurrence of the overshoot to generate a correction pulse current. Another N-transistor switches a current of a third constant current source by a positive correction pulse applied at timing of occurrence of the undershoot to generate a correction pulse current. These correction pulse currents are added to the output pulse current to obtain a current as a wavelength where the overshoot and undershoot are largely reduced.

Abstract: A clock distribution network for clock distribution in an integrated circuit (IC) using digital feedback for skew compensation and jitter filtering.

Abstract: A system and method for distributing clock signal information as rising and falling edge signals is disclosed. In one embodiment a first pulse signal includes a pulse generated for the rising edge of each clock pulse signal includes a pulse generated for the falling edge of each clock pulse. The temporal information associated with the time delay of the leading edges of corresponding pulses of the first and second pulse signals may be used to recover the clock signal. In one embodiment, skewed amplifiers are used to amplify the first and second pulse signal edge pulse. In one embodiment, the first and second pulse signals are regenerated and amplified before they are and into a tri-state buffer to recover the clock signal.

Abstract: An asymmetry detection circuit having a simple circuit configuration capable of realizing reliable detection without dependence on the signal level and capable of realizing high precision asymmetry detection almost completely free of any influence from a voltage offset or the like, and a detection method of same, wherein a capacitor cuts off the direct current component of an input signal and passes the alternating current component, a bias voltage is added to the alternating current component in accordance with a constant voltage of a constant voltage source to generate an APL clamp signal, a comparator compares the signal with a constant voltage and outputs a pulse voltage signal representing a duty ratio of the signal in the APL value, a voltage/current conversion circuit outputs a current signal to charge or discharge a capacitor to generate an integrated signal, and a filter eliminates the alternating current component of the integrated signal and outputs the direct current component as an asymmetry dete

Abstract: A distributed clock generator for a semiconductor device. In one embodiment, the clock generator is not localized in one particular location on the semiconductor die and then distributed, but instead the clock generation itself is distributed throughout the integrated circuit. The clock generator itself is a CMOS phase shift oscillator which uses a series resistance and a capacitance to ground. Phase shift elements utilize the phase shift of distributed transmission lines around the integrated circuit die and are thus conveniently implemented using the series resistance and parallel capacitance of the transmission lines.

Abstract: Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.

Abstract: A clock signal generator circuit comprises an off-chip driver, a first clock control circuit for outputting a first internal clock signal Tu synchronizing with an external clock signal CK, a second clock control circuit for outputting a second internal clock signal Td 180° out-of-phase with the external clock signal CK, a third clock control circuit for outputting a third internal clock signal aTx1 synchronizing with the first clock signal Tu and advanced in phase by at least the signal delay time in the off-chip driver, a fourth clock control circuit for outputting a fourth internal clock signal aTx2 synchronizing with the second clock signal Td and advanced in phase by at least the signal delay time in the off-chip driver, an OR circuit to which the third and fourth internal clock signals aTx1, aTx2 are inputted and which outputs a fifth internal clock signal aTx, and a fifth clock control circuit for outputting a sixth internal clock signal Tx which is in synchronization with the fifth internal clock s

Abstract: A clock control circuit comprises a control circuit 102 for outputting a control signal for adding or subtracting a phase to a reference clock, which is an input clock or a clock generated from the input clock, on each clock period of the reference clock, and a phase adjustment circuit 101 fed with the input clock and outputting an output clock having the phase adjusted to the reference clock.

Abstract: Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon mounting various circuit boards on multiple slots, even if the location of the system slot is varied, the skew of clocks transmitted to the other slots may be minimized. Accordingly, the system may be configured in a flexible manner because of such variability of the system slot's location. Further, the system may be efficiently repaired and maintained because it is possible to easily and quickly take measures in response to any failure occurring on the board mounted on the system slot.

Abstract: A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator [(1)]for sampling the received signal[(S)] in such a way that several sampling values of a bit cell transmitted with the received signal [(S)]are distributed time-wise one after the other onto several output connections [(2)]of the commutator device[(1)] and emitted there in the form of corresponding intermediate signals. A first circuit [(5)]combines a first group of intermediate signals of the commutator device [(1)]into a first uniting signal[(VS1)], which serves as the basis for data recovery or comprises the recovered data signal, while a second circuit [(6)]combines a second group of intermediate signals of the commutator device [(1)]into a second uniting signal[(VS2)], which serves as the basis for clock recovery.

Abstract: In an ultrahigh-speed clock extraction circuit wherein a local pulse generating light source 22 for generating a local optical pulse stream synchronized in bit phase with an input optical signal pulse stream is placed in a phase-locked loop, when repetition frequencies of the input optical signal pulse stream and the local optical pulse stream bear a particular relationship, a frequency demultiplier 32 and multipliers 43 and 52 are set so that the frequency of a modulation signal for an optical modulator 41 and a frequency which is a natural-number multiple of the modulation signal frequency, and the frequency of a down-converted version of an optical pulse stream output from a photodetector 42 differ from each other.

Abstract: A signal transmission apparatus is disclosed for setting delay amounts based on an operational speed. At least some of a plurality of rectangular wave signals transmitted in parallel are individually delayed by a plurality of signal delaying means for different time periods from one another in order to prevent the occurrence of noise. At this point, the delay time in the plurality of signal delaying means are set by time varying means based on the operational speed of a digital circuit which outputs digital data as the rectangular wave signals.

Abstract: A waveform generation apparatus comprises a delay circuit comprising i pieces of unit delay circuits connected in series, and providing i kinds of delay states by deriving signals from the respective unit delay circuits; k pieces of selection circuits each selecting one delay state from among the i kinds of delay states; a waveform generation circuit for generating n pieces of binary state signals in the same state, or generating n pieces of binary-state signals having a shape according to recording data supplied from the outside, on the basis of the signals having the i kinds of delay states; a transmission path for transmitting the n pieces of binary-state signals generated by the waveform generation circuit; a waveform synthesis circuit for generating a signal having multi-valued information from the n pieces of binary-state signals transmitted through the transmission path; a phase difference detection circuit for detecting phase differences among the n pieces of binary-state signals in the same state, wh

Abstract: A clock recovery circuit is provided for use in a memory with a clock synchronized interface, wherein an external clock is temporarily intercepted to shorten lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, receiving the external clock, for generating reference clocks, a control circuit comparing phases of the external clock and of the reference clocks and detecting the number of delay stages required for locking in, and a latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected, the generation of internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

Abstract: When an up signal UP is inputted, a switch is turned on and thereby a capacitor is charged to raise a control voltage VC. Further, when a down signal DWN is inputted, a switch is turned on and a capacitor discharges to hold the down signal DWN in the capacitor. Then, when a switch is turned on by a transmission signal EXE, an electric charge is injected into the capacitor to lower the control voltage VC. Further, when a switch is turned on by a reset signal RST, the capacitor is charged by an amplifier to cancel the down signal DWN. As a result, a low jitter reproduction clock can be generated regardless of an operating frequency.

Abstract: A method and related circuit for clock generation and recovery utilizes digital components exclusively. The method is used to generate a wobble clock and an absolute time in pre-groove (ATIP) clock for controlling the operation of an optical disk drive. The circuit includes a counter and a digital logic circuit and utilizes clock triggering processes.

Abstract: In a circuit for producing output pulses which correspond to pre-selected voltage pulses occurring in an input signal train; means connected to derive from said input signal train a succession of unidirectional pulses, at least some of which pulses occur in time coincidence with the leading and trailing edges of said pre-selected voltage pulses; means including a one-shot multi-vibrator connected to receive said unidirectional pulses and produce a first series of pulses having a uniform duration less than the duration of said pre-selected voltage pulses, means including a bi-stable multi-vibrator connected to receive and produce from said first series of pulses a second series of pulses equal to one half the number of pulses in said first series occurring in a given time interval, and means including a discriminator circuit connected to receive said first and second series of pulses and derive a third series of pulses which corresponds to said pre-selected voltage pulses occurring in said input signal train.

Abstract: A method for increasing a transition time period for an edge transition of a clock signal has been developed. The method includes detecting an edge transition of a clock signal of a computer system. Next, additional system power consumption is initiated upon detection of the edge transition. This additional power consumption will lengthen the edge transition time period of the clock signal.

Abstract: A system and method for distributing clock signal information as rising and falling edge signals is disclosed. In one embodiment a first pulse signal includes a pulse generated for the rising edge of each clock pulse signal includes a pulse generated for the falling edge of each clock pulse. The temporal information associated with the time delay of the leading edges of corresponding pulses of the first and second pulse signals may be used to recover the clock signal. In one embodiment, skewed amplifiers are used to amplify the first and second pulse signal edge pulse. In one embodiment, the first and second pulse signals are regenerated and amplified before they are and into a tri-state buffer to recover the clock signal.

Abstract: Methods and apparatus for generating clock signals accurately locked to multi-gigabits-per-second data signals received over fiber optic channels are disclosed. The invention includes a phase detector for comparing a data signal and a clock signal, a one shot unit for detecting a data transition, an XOR, a filter, a main charge pump, a compensating charge pump for producing additive or compensating current, and a VCO for generating the clock signal. The phase detector includes multiple D-flip flops. The one shot unit includes a delay unit and an AND gate. The filter includes a resistor, a capacitor and a negative resistance amplifier. The main charge pump includes differential inputs, double outputs, cross-quading resistors, differential NPN input transistors, and a current source. The compensating charge pump includes differential NPN input transistors and a current source.

Abstract: An apparatus and method for providing an input signal having a desired pulse width and amplitude to atomic force miscoscopes (AFMs) for use in nano-lithography are provided. An input signal providing apparatus for a contact type AFM includes: a pulse width adjusting unit which adjusts the width of a positive pulse of an input square wave to a predetermined pulse width; and an amplitude adjusting unit which adjusts the amplitude of the positive pulse of the square wave to a predetermined voltage. An input signal providing method for the contact type AFM uses the apparatus having this structure. An input signal providing apparatus for a non-contact type AFM further includes a square pulse generating unit which generates a square pulse having a predetermined phase in synchronization with an input resonance signal, and an input signal providing method for the non-contact type AFM further involves generating the square pulse having a predetermined phase in synchronization with the input resonance signal.

Abstract: A clock smoothing circuit generates a smoothed clock signal from a gapped clock signal having unevenly spaced pulses separated by gaps that result from the removal of data bits and from a reference clock signal having evenly spaced pulses that create a predetermined reference frequency. A smoothing element is coupled to the input elements to receive the gapped clock signal and the reference clock signal. In one embodiment, the smoothing element generates a smoothed clock signal having one pulse for each of the pulses in the gapped clock signal and having a frequency that is greater than one-half of the predetermined reference frequency. Each pulse in the smoothed clock signal is synchronized with a pulse in the reference clock signal.

Abstract: A user circuit unit is configured by a gate array, a PLT circuit is configured in a microprocessor macro unit, a clock frequency output from the PLL circuit in the microprocessor macro unit is directly distributed to auser circuit unit (CLK 3), and the clock frequency distributed to the user circuit unit is distributed to the microprocessor macro unit through a frequency divider configured by the user circuit unit.

Abstract: The oscillator 40 with cycle time correction includes a low accuracy oscillator 30A generating a clock CLK3, a counter 41 counting the clock CLK3 and cleared by activation of a clear signal CLR1, a register 42 storing a count CN of the counter 41 as a reference value RV in response to activation of a capture signal CAP; a comparator 43 activating a coincidence signal EQ when CN=RV, a control register 44 including a bit outputting a clear signal CLR2, a bit outputting an enable signal EN and a bit outputting a capture signal CAP, and logic circuits 45 and 46 activating the clear signal CLR1 when the clear signal CLR2 is active or when the enable signal EN and the coincidence signal EQ are both active.