Abstract: A receiver is described for recovering digital data from a transmitted balanced signal where the balanced signal includes a first plurality of pulses, each pulse having a first pulse width. The receiver includes an input circuit, a buffer circuit, and a calibration circuit. The input circuit receives the transmitted signal and includes a first differential amplifier for amplifying a first signal, a second differential amplifier for amplifying a second signal, and a converter for receiving the amplified first signal and amplified second signal and then generating a third signal. The first and second signals are included within the transmitted signal. The buffer circuit receives and buffers the third signal, and outputs a fourth signal including a second plurality of pulses which have a second plurality of pulse widths. The calibration circuit receives the fourth signal.

Abstract: The present invention relates to a circuit for processing vertical synchronization logic signals of positive or negative polarity. Based on signals locating, on the one hand, the presence of the beginning of a pulse and, on the other hand, the rising and falling edges in the synchronization signals, a brief pulse is provided in a signal generated by a one-shot. This pulse induces the generation of edges in signals controlling a latch which generates a logic detection signal. According to the polarity of the received signals, the latch is set or reset and the state of the detection signal indicates the polarity of the synchronization signals.

Abstract: A drive arrangement for a switched output stage, such as an output stage of a gradient intensifier of a tomography apparatus has a pulse-width modulator and drive logic for producing at least two drive signals. The drive logic produces, for each drive signal, an edge of each on-phase pulse at a time made fixed corresponding to a time reference clock signal thereby allowing a fine adjustment of the on-phase of the power transistors of the switched output stage with low components costs, and a prescribed dead time between the individual on-phases is reliably adhered to.

Abstract: An improved circuit for producing a pulse having a predetermined pulse width. The pulse width forming circuit includes a first delay element for receiving an input pulse and delaying the input pulse by a first delay time, an OR gate for receiving the input pulse at an input terminal and a first delayed pulse signal from the first delay element at another input terminal and adding the first delay time to a pulse width of the input pulse, a second delay element for receiving an output pulse of the OR gate and delaying the output pulse by a second delay time, and an AND gate for receiving the input pulse and a second delayed pulse signal from the second delay element for producing a pulse waveform having a predetermined pulse width whose starting edge corresponds to an end timing of the input pulse and whose stop edge corresponds to an end timing of the second delayed pulse signal.

Abstract: In a double-sided pulse width modulator, an amplifier has a first input connected to a first reference potential, a second input, and an output. A first bank of storage elements have a first terminal connected to the second input of the amplifier, and a second terminal. A first bank of switches have an output terminal connected to a second terminal of the storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of the modulator and a polarity control bit for a first value to be input into the input terminals. A feedback storage element is connected in parallel with a first timing switch between the second input of the amplifier and the output of the amplifier. A comparator has a first input connected to a second reference potential, a second input, a timing enable input, and an output. A second bank of storage elements have a first terminal connected to the second input of the comparator, and a second terminal.

Abstract: A clock generating circuit includes a clock generator and a cycle controller. The clock generator is coupled to receive a reference oscillating signal. The clock generator provides a clock signal responsive to the reference oscillating signal. The cycle controller is coupled to provide a cycle control signal to the clock generator. The clock generator stretches a cycle of the clock signal responsive to a first value of the cycle control signal.

Abstract: A pulse-width modulation signal generator having a pre-phase converter which includes N pre-delay circuits connected in cascade, and N main phase converters each of which includes M main delay circuits, where N and M are natural numbers greater than one, and N>M. The output of each of the N pre-phase circuits is supplied to one of the N main phase converters to generate phase converted clock signals used for generating a pulse-width modulation signal.

Abstract: A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit.

Abstract: A power converter forming part of a telephone subscriber line interface circuit selectively generates a ringing signal waveform, for supply to the line, or a supply voltage for a driver circuit for providing loop current on the line. First and second fixed frequency PWM signals are used to control the power converter, and hence the voltage which it generates, for the ringing signal waveform and the supply voltage respectively. The first PWM signal enables the power converter to provide a high power level needed for ringing signals. The second PWM signal has a lower frequency, and hence results in lower switching losses and power dissipation, and a lower duty cycle, suitable for the lower power level needed for the supply voltage, and is conveniently produced by masking pulses of the first PWM signal. The frequency of the second PWM signal is greater than 270 kHz, to avoid transmitting spectral energy to the line below this frequency.

Abstract: Various embodiments for controlling a ramp rate of a high voltage generator circuit such as a charge pump circuit are disclosed. In one embodiment the ramp rate of the output signal is controlled by modulating an amplitude of the oscillating signal at the input of the charge pump circuit. In another embodiment, the ramp rate is controlled by modulating the current loading at the output of the charge pump circuit. In yet another embodiment, the ramp rate of the output signal is controlled by modulating the frequency of the oscillating signal at the input of the charge pump circuit.

Abstract: Correction of a duty-cycle is performed for use with a divide-by-two phase-splitter to increase precision of the duty-cycle of an incoming local oscillator signal in order to provide more precise phase relationships during generation of a phase and amplitude modulated carrier. Phase-splitter input signals are generated by limiting the slew-rate of an incoming signal to produce an intermediate signal. The intermediate signal is clipped in relation to a reference level. The reference level is adjusted by a feedback signal to produce an adjusted duty-cycle signal as an output signal. The feedback signal is proportional to the adjusted duty-cycle signal.

Abstract: Pulse width modulation driver circuitry both limits and regulates the voltage that is applied to a load from a power source which provides a voltage that may far exceed the maximum safe load voltage. The driver circuitry includes a reactive filter coupled to the load, a voltage sensor for sensing the instantaneous voltage across the load, a timer, and a comparator. The reactive filter alternately takes in energy from the power source and discharges it into the load. The voltage sensor, timer, and comparator cooperate with a switch to modulate the application of power to the load and to the reactive filter in response to the instantaneous magnitudes of the load voltage and the power source voltage.

Abstract: A skew logic circuit device comprises:two or more inverters which are connected in series with one another between an input line and an output line; first control switching means for switching voltage from a first power voltage source toward an output terminal of every odd inverter; second control switching means for switching voltage from a second power voltage source toward an output terminal of every even inverter; and edge signal generating means for sequentially controlling the operation of the first and second control switching means by the edge signal of a fixed pulse width caused by logically combining the signal from the input line.

Abstract: There is disclosed a pulse-width controller which includes a first pulse-width adjusting section which adjusts the pulse width of a main pulse signal, a second pulse-width adjusting section which adjusts the pulse width of a reference pulse signal, a pulse-width measurement section which measures the pulse width of the reference pulse signal adjusted by the second pulse-width adjusting section, a target pulse-width setting section for setting a target pulse width to be achieved by the first pulse-width adjusting section, and a control section which outputs to the first pulse-width adjusting section a control signal for use in adjusting the pulse width of the main pulse signal in the first pulse-width adjusting section, on the basis of pulse-width information regarding the reference pulse signal measured in the pulse-width measurement section and the target pulse-width information set by the target pulse-width setting section.

Abstract: A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal.

Abstract: The apparatus and the method representing an improved power management system are disclosed. The apparatus incudes a feedback control system with a delay element. The delay element introduces the oscillation frequency outside the input frequency band into the feedback control system. Therefore, the apparatus emulates a very efficient pulse width modulator (PWM) with a feedback. The apparatus additionally includes a pulse shaper amplifier that squares the pulse of the output signal.

Abstract: A circuit for detecting delay of more than a set period of time from a last signal transition for any of a plurality of data signals, comprising a differential comparator, and integrator pairs for each signal, one integrator of the pair being triggered by transition of the signal from low to high and the other triggered by transition of the inverse of the signal from low to high, each integrator having a voltage measured by the differential comparator against a reference voltage, each integrator being reset by the trigger for the other integrator.

Abstract: The invention provides a method and system for reshaping periodic waveforms to a selected duty cycle. An incoming periodic waveform has its edge transitions stretched out, and the stretched edge transitions compared with an adaptively selected threshold, to generate a reshaped waveform with a 50% duty cycle. The incoming periodic waveform is a square wave clock signal. The edge transitions are stretched using an inverter which is biased and filtered, and the stretched edge transitions are squared off using a comparator. The reference voltage for the comparator is selected using a second filter coupled in a feedback configuration with the biasing transistors for the inverter.

Abstract: An auto-refresh control circuit for a semiconductor device includes a burn-in signal generator detecting a burn-in test state and generating a burn-in signal and a synchronous buffer receiving a clock signal and an external signal and generating an asynchronous signal and a synchronous signal corresponding to the external signal, the synchronous buffer synchronizing the asynchronous signal to the clock signal. A decoder, coupled to the synchronous buffer, receives control signals and the synchronous signal synchronized to the clock signal from the synchronous buffer and outputs a refresh signal. A refresh control signal generator, coupled to the burn-in signal generator, synchronous buffer, and the decoder, receives the refresh signal, the burn-in signal, and the asynchronous signal and generates an auto-refresh control signal.

Abstract: A timer circuit for providing output pulses of an adjustable duration based upon stored decode parameters. The circuit has a timer element which generates a periodic timing signal. Preferably the frequency of the periodic timing signal is also adjustable. A frequency divider is clocked by the timing signal and provides a plurality of frequency divided outputs. A decode circuit combines selected ones of the frequency divided outputs based upon decode parameters and generates a timer circuit output pulse having a duration determined by the frequency divided outputs selected by the decode parameters. The decode parameters are stored in a non-volatile data storage unit so that the timer output pulse will remain the same after power interruption.

Abstract: A circuit that forms a square wave pulse train signal wherein each pulse is centered about a zero crossing of a reference sinusoid. A first capacitor is coupled to be charged and discharged at equal rates by a first transconductance amplifier. Upon a first positive zero crossing of the reference sinusoid, the first transconductance amplifier begins charging the first capacitor. Upon the first negative zero crossing, the first transconductance amplifier begins discharging the first capacitor until a first predetermined voltage level is reached. Upon reaching the first predetermined voltage level, the first transconductance amplifier begins charging the first capacitor again. The voltage on the first capacitor is compared by a first comparator to a second predetermined voltage level higher than the first voltage level. The output of the first comparator is a pulse which is centered about a second positive zero voltage crossing of the reference sinusoid.

Abstract: A phase-frequency detector (12) is configured for operating at a high frequency. A transition of a clock signal (REF CLK) is detected by a first latch (52) and a signal UP is generated. A transition of a feedback signal (FBK) is detected by a second latch (56) and a signal DOWN is generated. An logic circuit (64) detects the signals UP and the DOWN and generates a reset signal (RESET). A pulse-width of the reset signal (RESET) is controlled and limited by the logic circuit (64) to provide a faster response time for setting the first and second latches (52 and 56) to a state that allows detection of the phase and frequency differences between the clock signal (REF CLK) and the feedback signal (FBK).

Abstract: A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

Abstract: An electrical network creates a differential voltage signal and comprises a plurality of first impedance elements of substantially equal values which are connected to form an impedance bridge. The impedance of at least one of the first impedance elements changes in response to at least one selected external condition to which the first impedance elements are exposed. The network also comprises a second impedance element which has two nodes. The second impedance element is connected at these nodes between a first pair of the first impedance elements. The differential voltages are measured between these nodes and between another node or nodes with magnitudes and signs being dependent upon the change in the impedance of the first impedance elements.

Abstract: A semiconductor composite element in which abnormal conditions of overcurrent, control supply voltage reduction and overheat are detected, and different abnormality signals are outputted according to the respective abnormal conditions thus detected. The semiconductor composite element includes: abnormal condition detecting circuitry for detecting the overcurrent and control supply voltage reduction of any one or all of the plurality of semiconductor switching elements and the overheat of the semiconductor composite element. An abnormality signal generating circuit is provided for producing different abnormality signals according to the respective abnormal conditions detected by the abnormal condition detecting circuitry.

Abstract: A pulse-width controller for a switching regulator is provided. The pulse-width controller is coupled to a bulk regulator in the switching regulator to control the bulk regulator to produce an output voltage in a fixed level and an output current in a desired level in response to various demands from the load. The pulse-width controller takes a voltage of feedback-voltage indicative of a change in the output voltage of the bulk regulator and a first voltage of feedback-current and a second voltage of feedback-current indicative of a change in the output current of the bulk regulator as feedback signals. These feedback signals can cause the pulse-width controller to produce a square-wave signal with an adaptive pulse width that controls the bulk regulator to produce the output voltage and current in the desired levels.

Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.

Abstract: The present invention provides an analog biased pre-driver and pad as well as a duty cycle adjustment cell prior to the pre-driver and pad. The pre-driver and pad may operate in either a 3 volt mode, a 5 volt mode or any voltage in between depending only on the power supply voltage present. No production configuration or post-production configuration is required. The present invention utilizes a special bias circuit to reduce the Vcc, temperature and other processing variations. A duty cycle cell produces a range of duty cycles when the circuit is operating between a 3 volt and 5 volt range.

Abstract: The clock synthesizer includes an oscillator section for providing a train of pulses corresponding to the transitions of a master clock signal, a first register coupled to the oscillator for dividing the train of pulses by a fixed integer to produce a plurality of first phase shifted signals corresponding in number to said integer, and a plurality of second shift registers corresponding in number to the integer and each having a clocking input coupled to a respective one of the first phase shifted signals. The second registers produce a plurality of second phase shifted signals having leading edge transitions separated from each other by displacements corresponding to the transitions of the master clock signal. The second phase shifted signals are then combined to generate the lower frequency clock pulses, which may be used, e.g., in the clocking of a charge coupled device image sensor.

Abstract: A pulse-width modulator is disclosed which can be used, for example, in a power factor corrected electronic ballast circuit. The pulse-width modulator circuit combines a reference waveform signal with a second signal to form a composite waveform signal. The composite waveform signal is then compared with a reference voltage. The level of the pulse-width modulator's output depends upon the results of the comparison, such that a change in the level of the second signal causes an adjustment in the duty cycle of the output. In an electronic ballast application, the reference waveform can be a scaled version of the oscillator waveform found in the ballast's inverter circuit.

Abstract: A non-inverting, inverting, delayed non-inverting, and delayed inverting non-overlapping clock signal is provided by a non-overlapping clock generator circuit (41, 61). The non-overlapping clock generator circuit (41, 61) increases time for circuit operation by minimizing delays between non-overlapping clock signals and simultaneously transitioning rising edges of clock signals. A non-overlapping clock generation circuit (41) comprises six NOR gates (43-48) and an inverter (42). Three NOR gates form a first delay line (43-45) and the remaining three NOR gates form a second delay line (46-48). The inverter (42) provides an inverted clock signal to the second delay line. A clock signal propagates through one delay line while the other delay line is non-responsive due to a feedback signal from the active delay line.

Abstract: An illuminator system is provided that is responsive to a trigger signal from a remote source to supply controlled pulses to a load, such as an array of light emitting diodes in a LED strobe. The LED strobe is positioned in close proximity to a lens mounting system. The system of the present invention includes a remote trigger source, a load such as an array of light emitting diodes, and a pulse gate section. The pulse gate section includes a trigger interface having an input connected to the trigger source and is configured to generate a pulse trigger signal in response to a trigger signal from the trigger source. A clock generator responds to the pulse trigger signal by generating at least one clock signal, and a flash pulse generator responds to the clock signal and to at least one user definable input signal by generating a flash pulse signal. The flash pulse signal is used to activate or deactivate the load, and a load drive section is used to drive the load.

Abstract: A pulse signal shaper supplying a pulse signal having a stable pulse width, including an input circuit that produces a first pulse signal in response to an input signal, a delay circuit that produces a second pulse signal obtained by delaying the first pulse signal by a predetermined time, and a signal mixing circuit that is connected to the input circuit and the delay circuit. The mixing circuit combines the first pulse signal and the second pulse signal to produce a third pulse signal having a pulse width equal to or greater than a delay time provided by the delay circuit, and supplies the third pulse signal as an output signal from the pulse signal shaper. In a preferred embodiment, the input circuit includes an oscillator responsive to the input signal. When the input signal has a higher frequency than a predetermined frequency, the input signal is supplied as the first pulse signal at a frequency equal to te frequency of the input signal.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: Disclosed is a programmable sound generator for generating digital outputs of tone and noise signals used for producing computer sound effects. The programmable sound generator includes at least two channels generating digital output serving as either tone signal or noise signal. A mixer is used to process the outputs of the channels in a digital, time-sharing manner. A volume controller coupled to the mixer is used to control the volume of the sound in a digital pulse width modulation (PWM) manner. Also, the volume controller allows its output to become floating when the programmable sound generator is not in use so as to allow another sound generating means to share the same sound transducing means. In the programmable sound generator, the tone generation and the noise generation share the same hardware, which allows low-cost production of the programmable sound generator.

Abstract: A one-shot current circuit generates a current for a desired period during an input signal transition, the desired period during an input signal transition being proportional to the edge rate of the input signal. The circuit includes a MOS transistor device which selectively conducts current between an input terminal and a current generating circuit. The current generating circuit can be a bipolar transistor having its base coupled to the input terminal and a main current path between a circuit output and a supply voltage.

Abstract: A timing signal generator adjustably times successive pulses of an output timing signal. The generator receives input data before each output pulse and controls the timing of that output pulse in accordance with the input data. The generator includes a circuit providing a set of 2N phase signals frequency locked to a reference clock signal but evenly distributed in phase. First and second selectors each sample the data once during each cycle of the clock signal. The sampled data tells the first selector whether it is to produce a first output signal during the next clock signal cycle and, if so, which of the first N phase signals the first selector is to select for controlling timing of edges of the first output signal. The sampled data also tells the second selector whether it is to produce a second output signal during a next clock signal cycle and, if so, which of the second N phase signals the second selector is to select for controlling the second output signal.

Abstract: An apparatus and method for instantaneously stretching multi-phase clock signals includes a delay line to generate a plurality of multi-phase clock signals. An instantaneous signal stretch logic circuit is connected to the delay line. The instantaneous signal stretch logic circuit transforms the plurality of multi-phase clock signals into stretched multi-phase clock signals in response to a filter capacitor analog signal and a digital stretch signal. Multiple embodiments of the instantaneous signal stretch logic circuit are disclosed. However, each embodiment includes dual current control paths with a single current control path responsive to the digital stretch signal, which is preferably a single bit value.

Abstract: Disclosed are method and apparatus for producing electric waveform driver signals for exciting acoustic emitters such as foghorns, wherein the frequency and amplitude of the signals are readily variable to match the input requirements of the respective drivers of the acoustic devices. In disclosed embodiments of a signal generator according to the present invention a coupling circuit outputs the driver signal through an array of field-effect transistors.

Abstract: A duty cycle correction circuit that facilitates correction of clock signal duty cycles, including correcting for errors introduced by intervening devices in the clock signal distribution network. The duty cycle correction circuit of the preferred embodiment comprises a clock chopper circuit, a duty cycle comparator circuit, and a control circuit. The duty cycle comparator circuit compares the duty cycle of the clock signal with the duty cycle of a reference signal. The control circuit adjusts the clock chopper circuit based upon the duty cycle comparison, resulting in an output with a corrected duty cycle.

Abstract: A pulse generating circuit includes a first portion and a second portion. The first portion is coupled to a control signal and a first signal, and generates the rising edge of a pulse signal in response to the control signal transitioning to a first state. The second portion receives the rising edge of the pulse signal and causes the first signal to transition to a second state in response to the rising edge of the pulse. The transitioning of the first signal to the second state causes the first portion to generate a falling edge of the pulse signal.

Abstract: A circuit suitable for use in a regulated bi-directional output power supply requiring controlled transitions between states, such as in a Battery Polarity Switch is provided to utilize many of the same circuit components in regulating both opposing polarities of the output signal. An exemplary circuit achieves use of a single error amplifier and pulse width modulator circuit to obtain both positive and negative regulation of the battery polarity switch output, along with controlled transition between the two states. In a specific embodiment a logic inverter allows the single pulse width modulator to control in both directions. A ramped reference fed to the error amplifier allows the same amplifier to control the transitions.

Abstract: A pulse generating circuit for use in a semiconductor memory device is triggered by a transition of an input logic signal, to provide an output pulse having a predetermined pulse width or period. Feedback from the output pulse is used to isolate the input signal once the output pulse has begun, so as to prevent premature truncation of the output pulse if the input signal changes state during the output pulse period. This pulse generator is particularly advantageous in high-speed semiconductor memory integrated circuits where the input pulse may be relatively brief.

Abstract: A pulse width modulation driver is capable of regulating the average voltage applied to a load that is powered from a source having a wide range, e.g. 20 to 80 volts DC, of possible voltages. The driver cyclically interrupts the load current at a frequency which is substantially constant. This is particularly advantageous for driving frequency-sensitive loads such as motors.

Abstract: A timing generator which receives a rate signal and generates an output signal based on the rate signal, and comprises at least two delay lines for causing delays in the rate signal, a formatter for receiving signals from the delay lines and for determining the rise and fall of an output signal according to such signals from the delay lines, and for generating an output signal, memories for storing delay time data from the delay lines, and a data selector for taking the delay time data from the memories and to switch the delay time data, whereby accurate timing signals are generated utilizing short skew adjustment time.

Abstract: An address transition detecting circuit comprising a first address transition detecting stage for generating a first address transition detection signal, the first address transition detection signal having a pulse width which is constant and stable when a supply voltage is relatively low, a second address transition detecting stage for generating a second address transition detection signal, the second address transition detection signal having the same pulse width as that of the first address transition detection signal from the first address transition detecting stage when the supply voltage is relatively high, a switching stage for switching selectively the first and second address transition detection signals from the first and second address transition detecting stages to an output line, and a supply voltage detecting stage for detecting a level of the supply voltage and controlling the switching stage in accordance with the detected level.

Abstract: A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.

Abstract: An edge-trigger pulse generator that is suitable for use in a signal generator is disclosed, including positive and negative logic embodiments. The positive logic embodiment includes: a first time-delay circuit for delaying and inverting an input pulse; a second time-delay circuit for broadening the width of the input pulse; a NAND gate for receiving outputs of the first time-delay circuit and the second time-delay circuit, and performing a NAND logical operation for the outputs; and an inverter for receiving and inverting output of the NAND gate, so that the width of an pulse output from the edge-trigger pulse generator can be determined merely by the edge-trigger pulse generator while the width of the input pulse is not wider than a predetermined width. The negative logic embodiment replaces the NAND gate with NOR gate and has a second time-delay circuit that is different from the second time-delay circuit of the first embodiment.

Abstract: A pulse-width-extension circuit for producing an output pulse signal whose pulse width is extended as compared with a pulse width of an input pulse signal when the pulse width of the input pulse signal is equal to or longer than a given width. The pulse-width-extension circuit produces no output pulse signal when the pulse width of the input pulse signal is shorter than the given width.

Abstract: A variable pulse width generator comprised of apparatus for receiving a clock signal, apparatus for terminating an output pulse from a leading edge of the clock signal, and apparatus for initiating another output pulse following the terminated output pulse from the leading edge of the clock signal and after a first delay, whereby successive output pulses are initiated and terminated that are related to the leading edge of the clock signal, and thus are related to the frequency but not the pulse Width of the clock signal.