Abstract: A PWM signal generator comprises a pulse width indication signal generator outputting a pulse width indication signal, and a pulse width adjustment portion receiving the pulse width indication signal. The pulse width adjustment portion outputs an adjusted pulse width data which corresponds to the pulse width indication signal when the pulse width indicated by the pulse width indication signal is equal to or wider than a predetermined width. The pulse width adjustment portion accumulates the pulse width indicated by the pulse width indication signal when the pulse width indicated by the pulse width indication signal is narrower than the predetermined width. The pulse width adjustment portion outputs the adjusted pulse width data which corresponds to a sum data of the pulse width accumulated in the pulse width adjustment portion when the sum of the pulse width becomes equal to or wider than the predetermined width.

Abstract: A pulse-width modulation circuit converts an input signal into a pulse signal to be supplied to a switch amplifying circuit. The modulation circuit includes a comparison signal generator, an amplitude controller for modulating a comparison signal from the signal generator, and a comparator for comparing the modulated comparison signal and the input signal. The comparator outputs a signal whose level is inverted in accordance with the level of the input signal. The signal outputted from the comparator is supplied to the switch amplifying circuit.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: A method and apparatus for an improved timer circuit and improved pulse width detection includes initiating a ramp timer and setting a timer latch output level substantially simultaneously in response to the occurrence of an input signal. The occurrence of the input signal also causes a counter to be enabled to count clock cycles. The ramp timer signal of the ramp timer is frozen (i.e., paused) by a timer control circuit, upon the occurrence of a first clock cycle following the enabling of the counter. The counter then counts a predetermined number of clock cycles after the ramp timer signal is frozen and, upon the occurrence of a last one of a predetermined number of clock cycles, generates a terminal count signal. Upon receiving the terminal count signal, the timer control circuit unfreezes ramp timer signal. The ramp timer runs until completion at which time the ramp timer generates an end of ramp control signal. The control signal is communicated to timer latch to reset timer latch output level.

Abstract: A control circuit is described in which a single input terminal receives digital control signals and analog control signals. In accordance with the principles of the invention, the control circuit includes an automatic power down circuit to place the control circuit into a low power draw or “sleep” mode whenever predetermined conditions are present. The automatic power down circuit monitors the single input terminal and when no demand for motor operation occurs for a predetermined period of time, the automatic power down circuit operates to place the control circuit into the low power draw mode.

Abstract: By using a first delay circuit that delays by a predetermined time a reference pulse signal having a constant pulse width and a second delay circuit that delays by an arbitrary time the output signal of the first delay circuit, a voltage conversion circuit generates an output pulse signal having a variable pulse period, and varies its output voltage according to the pulse period of this output pulse signal.

Abstract: A digital controller for a DC converter has a timing and control unit which produces a control pulse signal with varying duty cycle and frequency in accordance with pulse on- and off-times determined by digital values read from a look-up table addressed via an A-D converter in dependence upon an input voltage for the DC converter. The stored digital values are such that a period of the control pulse signal varies over a range of about two-thirds to about four-thirds of a nominal value. Closed loop feedback control can be added by modifying addressing of the look-up in dependence upon an error signal from the DC converter output voltage, with scaling depending on the input voltage.

Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

Abstract: A timing circuit independently controls placement of the positive and negative edges of a periodic signal. This signal may then be used to control a wide variety of integrated circuit applications. The timing circuit includes separate programmable delay lines and a signal processor. Each delay line delays an input clock signal by a different increment of time. The signal processor then generates a timing signal from the clock signal, where the timing signal has a first edge controlled by the first delayed clock signal and a second edge controlled by the second delayed clock signal. The edges may be controlled so that the timing signal assumes different logical values for different amounts of time, thereby customizing the signal to any application. An example of one application includes using the timing signal control switching in a DC-DC converter.

Abstract: The present invention discloses a circuit for controlling a pulse width including a frequency detection circuit for extracting an operation frequency band by receiving an external clock, delaying the external clock for a different time and comparing a frequency of the external clock with frequencies of the external clocks delayed for the different time, respectively, and outputting a plurality of mode signals according to the operation frequency band; and a pulse generation circuit for generating a pulse having its width varied by the operation frequency, by using a delay time based on the plurality of mode signals from the frequency detection circuit. As a result, the circuit for controlling the pulse width can be applied to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supporting various operation frequencies.

Abstract: A control circuit is described in which a single input terminal receives digital control signals and analog control signals. A circuit coupled to the single input provides a first output to indicate that a signal at said single input terminal is a digital signal and a second output indicates that a signal at said single input terminal is an analog signal.

Abstract: A monocycle forming network may include a monocycle generator, up and down pulse generators, data modulators and clock generation circuits. The network may generate monocycle pulses having very narrow pulse widths, approximately 80 picoseconds peak to peak. The monocycles may be modulated to carry data in ultra-wideband communication systems.

Abstract: A PWM controller having frequency jitter includes a modulator for generating a first jitter current and a second jitter current. An oscillator generates a pulse signal for producing a switching frequency in response to the modulation of the first jitter current. An attenuator is connected in a voltage feedback loop for attenuating a feedback signal to an attenuated feedback signal, in which the attenuated feedback signal is utilized to control an on-time of a switching signal. A variable-resistance circuit is connected with the attenuator for programming an attenuation rate of the attenuator in response to the modulation of the second jitter current. The switching frequency increases whenever the first jitter current increases. Meanwhile, the impedance of the attenuator will decreases and the attenuation rate will increase whenever the second jitter current increase.

Abstract: In a noise sensitivity improved switching system and method thereof, comprised sensing the output voltage of the switching system to generate a feedback signal, respectively amplifying the feedback signal by two gains to generate two signals in phase or out of phase, filtering one of the two amplified signals, and summing or comparing the filtered signal and the other one, thereby reducing the noise interference to the switching system.

Abstract: The present invention provides one pulsewidth control loop (PWCL) device with complementary signals. The PWCL device includes one control stage circuit, one buffer chain, one complementary circuit, two charge pumps, and one comparator. The control stage circuit is used to receive a clock signal and the control signal of the comparator, and output a signal to the buffer chain. The buffer chain is used to receive the output signal from the control stage circuit and output a signal to the complementary circuit. The complementary circuit is used to receive the output signal from the buffer chain and output two complementary signals. Each of the two charge pumps is used to receive one of the output signals from the complementary circuit and output a signal to be one of the inputs of the comparator. The comparator is used to receive the output signals from each of the two charge pumps. Then, the comparator outputs a signal and feedbacks to be one of the input signals of the control stage circuit.

Abstract: A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.

Abstract: A circuit arrangement for producing a PWM signal (x) having a prescribed PWM frequency from two signals (a, b) which are input into the circuit arrangement, where the PWM signal (x) has a duty ratio which varies with the difference between the signals (a, b) comprises a signal generator (16) for producing a cyclic comparison signal, particularly an essentially trapezoidal signal (d), whose frequency is the same as the PWM frequency and whose shape is dependent on one (a) of the two signals (a, b), and a comparator (18) for comparing the other (b) of the two signals (a, b) with the comparison signal (d) and for providing the PWM signal (x) at the output of the comparator.

Abstract: A pulse width modulation (PWM) circuit comprising an input circuit, first and second controllers, and first and second Schmidt triggers. The first controller sets a first voltage level by a first current generated responding to an input signal and an output of the input circuit. The first Schmidt trigger sets a first logic level when an output of the first controller reaches the first voltage level. The second controller sets a second voltage level by a second current generated responding to the input signal and an output of the first Schmidt trigger. The second Schmidt trigger generates a PWM output signal with a variable frequency in accordance with the first and second currents.

Abstract: A method and system for generating variable frequency cyclic waveforms using pulse width modulation (PWM) to provide adjustable precision frequency and enhanced resolution is disclosed. The technique includes a plurality of sets of duty cycle values, each set corresponding to the desired waveform profile at a given frequency, coupled with a mechanism for applying a selected duty cycle for a variable number of PWM cycles, to achieve an adjustable fine resolution of the waveform frequency.

Abstract: A multi-turn pulse width modulation (PWM) generator for generating a PWM output corresponding to multiple 360 degree turns. A counter receives a reference signal, and counts a number of cycles of the reference signal to generate a binary output corresponding to the number of cycles counted. A frequency divider receives a sensor output signal, and divides the frequency of the sensor output signal by the number of turns in the multiple turns to generate a frequency divided signal. The sensor output signal has substantially the same frequency as the reference signal, but can be offset in phase from the reference signal. A demultiplexer receives the binary output, and generates a plurality of turn indicator signals, each corresponding to one of the multiple turns. A multiplexer receives the turn indicator signals and a mechanical turn indication signal, and selects one of the turn indicator signals that corresponds to the mechanical turn indication signal.

Abstract: In one embodiment, a power supply system has a transistor driver that receives a PWM signal and generates signals to drive output transistors of the power supply system in response to the PWM signal. If the PWM signal is low for a certain length of time, the transistor driver disables t least one of the output transistors.

Abstract: Apparatus and methods to control laser duty cycle are disclosed. According to one example, a driver circuit may include a duty cycle adjustment circuit, an output stage configured to receive an input signal having a duty cycle and a replica output stage configured to receive the input signal and to produce an output signal that is coupled to a duty cycle adjustment circuit. In such an arrangement, the duty cycle adjustment circuit is configured to affect the duty cycle of the input signal.

Abstract: A circuit for detecting a logic transition is proposed.

Abstract: Provided is a digital duty cycle correction circuit and method for a multi-phase clock, in which duty cycle correction information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle correction method for a multi-phase clock and phase information of the input clock signal is held constant during duty cycle correction of the input clock signal by correcting duty cycles of the input clock signal by changing the falling edge of the clock without changing the rising edge of the input clock signal during duty cycle correction of the input clock signal, thereby correcting the multi-phase clock. To this end, the digital duty cycle correction circuit includes a clock delay means that takes the form of a shunt capacitor-inverter, a clock generation means including a clock rising edge generation circuit and a clock falling edge generation circuit, and a digital duty cycle detection means including integrators, a comparator, and a counter/register.

Abstract: A clock shrink circuit has an inverting first matching stage which is responsive to an input clock signal to generate a first inverted signal having a first matching delay. The first matching delay is a difference between a first rise and a first fall propagation time of the first matching stage. An inverting first pull-up stage is coupled to the first matching stage and is responsive to the first inverted signal to generate a second inverted signal having a first pull-up delay which is substantially reduced by the first matching delay. The first pull-up delay is a difference between a second rise and a second fall propagation time of the first pull-up stage.

Abstract: A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when “delay time td+allowance time ta” has elapsed from a start signal Sp. The delay time td is shorter than “the minimum time width of H level of PWM signal SPWM1?allowance time ta”. The delay time td is also time from the variation of level of the PWM signal SPWM1 to actual variation in the passage of current through a power section.

Abstract: A pulse generating circuit generates a pulse with a desired pulse width even when a process parameter for manufacturing fluctuates or a source voltage varies. The pulse generating circuit includes a first voltage outputting section having a first delay circuit and operating to output a first voltage changing from a high level towards a low level based on a first time constant according to a one-shot pulse, a second voltage outputting section having a second delay circuit and operating to output a second voltage changing from a low level towards a high level based on a second time constant according to the one-shot pulse, and a differential circuit to generate a pulse with a pulse width corresponding to a period from a time point of inputting the one-shot pulse to a cross time point when the first voltage coincides with the second voltage.

Abstract: A circuit for controlling pulse width of a signal for driving a light emitting element, includes a pulse width control circuit capable of responding to multi-bit rates in the same circuit structure. For this purpose, the pulse width control circuit has a Tr/Tf control section controlling at least one of a rise time Tr and a fall time Tf of an input signal according to the bit rate of the input signal; a waveform shaping section shaping a signal output from the Tr/Tf control section to generate an output signal; and a control signal generating section generating a control signal for controlling an operation of the Tr/Tf control section based on pulse width control information.

Abstract: An electronic system according to various aspects of the present invention comprises a signal generator configured to generate a first signal and a duty cycle correction circuit configured to be responsive to the first signal and provide a corrected signal having a corrected duty cycle. The duty cycle correction circuit may include a duty cycle detection circuit and a signal adjustment circuit. The duty cycle detection circuit is suitably configured to identify a disparity between a corrected duty cycle of the corrected signal and a target duty cycle. In one embodiment, the duty cycle detection circuit includes a self-bias circuit configured to generate a control signal according to the disparity between the corrected duty cycle and the target duty cycle. The signal adjustment circuit may be responsive to the control signal and configured to provide the corrected signal having the corrected duty cycle according to the control signal.

Abstract: A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PWM output signals have dual deadtime delay in which the delay between the inactivation of the first signal and the activation of the second signal may be different than the delay between the inactivation of the second signal and the activation of the first signal. This provides an improved capability to deal with non-symmetric switching characteristics of the external switching devices, and the circuitry to which they are connected.

Abstract: The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.

Abstract: A high bandwidth, feed-forward oscillator generates a ramp or sawtooth voltage for controlling the operation of a pulse width modulator-based, switched DC power supply circuit. The oscillator is operative to effectively immediately adjust the slope of each rising and falling portion of the ramp/sawtooth signal, as necessary, in proportion to the magnitude of the input voltage, while maintaining the frequency of the ramp waveform effectively constant. A comparator network establishes a difference between peak and valley portions of the sawtooth in accordance with input voltage. In response to a change in input voltage a control circuit modifies the value of the difference between the peak and valley portions to define a new set of respective peak and valley portions VpeakNEW and VvalleyNEW, and immediately causes the sawtooth waveform to transition to the new set of respective peak and valley portions VpeakNEW and VvalleyNEW at said prescribed frequency.

Abstract: A mono-cycle generating circuit includes a multiplexer, a pulse generating circuit, and a buffer circuit. The multiplexer receives data of a logical 1 or a logical 0, determines whether to generate a positive mono-cycle or a negative mono-cycle, based upon the data, and outputs clock signals varying in time based upon the data. The pulse generating circuit is coupled to the multiplexer, receives the clock signals and generates a first series of pulses including an up-pulse preceding a down-pulse, or a second series of pulses including a down-pulse preceding an up-pulse, in response to the clock signals received by the multiplexer. The buffer circuit is coupled to the pulse generating circuit and includes a switch circuit and a common mode buffer. The switch circuit generates the positive mono-cycle or the negative mono-cycle, based upon whether the first series of pulses is received from the pulse generating circuit or the second series of pulses is received from the pulse generating circuit.

Abstract: Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

Abstract: A radio frequency amplifier and a method of driving the radio frequency amplifier which are excellent in the controllability at the time of a low power output while keeping the advantage of a high efficiency and give the heating generated by a power loss of such a degree that dewing generated due to over-cooling by the cooling system is not generated at the time of a low power output. The radio frequency amplifier is structured by a variable wave height and a variable wave width pulse wave generating circuit that generates a pulse wave (rectangular wave) having an arbitrary pulse height and pulse width, and a power amplifier that is driven by the rectangular wave.

Abstract: In a pulse width modulation circuit, which generates an output whose pulse width is modulated by controlling a duty ratio of an oscillation circuit adapted to generate an oscillation at a frequency determined by a resistor and a capacitor to be electrically charged via the resistor, there is provided a resistance value varying means to vary a value of the resistor. The value of the resistor is varied by shorting the both ends of the resistor with a transistor, whereby the capacitor is charged in a reduced amount of time realizing a high-speed pulse width modulation circuit.

Abstract: An oscillator has timing characteristics that are determined by resistor and capacitor values. The circuit comprises an astable multivibrator and a current reference. The multivibrator comprises a first and a second timing capacitor. The multivibrator is configured to produce an oscillating output signal in response to charging and discharging the first and the second timing capacitors. The current reference is configured to control the rate of change of charge of the first and second timing capacitors. The current reference is determined in part by the resistor values.

Abstract: A circuit and method of generating an internal chip clock signal for distribution throughout an integrated circuit in response to an external clock signal includes the steps of generating a minimum width internal clock signal if the width of the external clock signal is less than a predetermined minimum width, generating an internal clock signal having a width substantially equal to the width of the external clock signal if the width of the external clock signal is greater than a predetermined minimum width but less than a predetermined maximum width, and generating a maximum width internal clock signal if the width of the external clock signal is greater than a predetermined maximum width.

Abstract: A pulse width modulated common mode feedback technique for a differential charge pump includes averaging the output of a differential charge pump to determine the common mode voltage; generating from the pump up and pump down pulses a set of up source pulses and down source pulses and a set of up sink pulses and down sink pulses and adjusting, in response to a difference between a reference voltage and the common mode voltage, the width of at least one of the sets of source and sink pulses to match the reference common mode voltages.

Abstract: A pulse generating circuit that has a reset pulse generation circuit configured to output a reset pulse when an input signal changes from a first state to a second state and a set pulse generation circuit configured to output a set pulse when the input signal changes from the second state to the first state is provided. This reset/set pulse generation circuits each comprise a CMOS inverter and a delay unit. The delay unit includes a capacitor chargeable/dischargeable in response to an output signal of the CMOS inverter to output a delayed output signal. In the reset pulse generator circuit, its capacitor is connected between the CMOS inverter's output end and the power supply line. The set pulse generator circuit's capacitor is coupled between the CMOS inverter's output end and the ground line. The inverter circuit sets the output end at the power supply line before the state change of the input signal and sets this output end at the ground potential after the state change of the input signal.

Abstract: A voltage conversion circuit has a pulse generator that generates a pulse signal having a fixed pulse width and a variable pulse period. The output voltage of this voltage conversion circuit is determined according to the ratio of the pulse width to the pulse period of the pulse signal generated by the pulse generator. This circuit configuration makes it possible to produce as the output voltage lower voltages than ever.

Abstract: A controller that is linearly responsive to an input voltage provides continuously adjustable control of the width of a periodically repeating digital pulse, thereby achieving a linear voltage to duty-cycle ratio transfer function. The circuit of the present invention includes a master clock input, a ratio control voltage input, a controlled duty cycle clock output, a high gain amplifier configured as an integrator having differential inputs, each equipped with a low pass filter, a controlled current source, a resettable timing capacitor, a threshold detector and a reference pulse generator.

Abstract: A signal generator generates an output signal with a programmable duty cycle and includes a first buffer which generates in response to an input signal an intermediate signal having a selected edge with a voltage slope selected to vary a length of a selected phase of the output signal. A second buffer having a selected input voltage threshold generates the output signal in response to the intermediate signal.

Abstract: A pulse-width controller (1800) is described. Pulse generators (1700L, 1700H) are coupled to receive clock signals (1320, 1321) and configured to extend respective high-time and low-time pulse widths to provide signals with lengthened pulse widths (1320P, 1321P). Control signals (1803, 1804) are generated from pulse-width lengthened signals (1320P, 1321P). Clock signals (1320, 1321) and the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are provided to differential logic (1823 through 1828), such as Differential Cascode Voltage Switch Logic, to provide a differential output (1611, 1612) which is duty-cycle adjusted. The control signals (1803, 1804) in combination with the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are used to selectively activate a respective portion of the differential logic (1823 through 1828) to pass signals to the differential output (1611, 1612).

Abstract: The invention provides a semiconductor integrated circuit incorporating a clock signal multiplying circuit which can generate a double multiplied clock signal in following up changes in power voltage and a frequency of a reference clock signal without using a phase comparator. The semiconductor integrated circuit can include first circuits which delay clock signals in stages, a second circuit which selects one of a plurality of delay clock signals which have been provided with different delays in the first circuits, and a third circuit which generates a double multiplied clock signal with a frequency double the clock signal based on a delay clock signal selected by the clock signals inputted to the first circuits and the second circuit.

Abstract: The present invention relates to a circuit and method for generating an internal clock signal. According to the present invention, it is determined whether an external clock signal is a high frequency or a low frequency. Depending on the determination, the external clock signal is waveform-shaped to generate an internal clock signal or the external clock signal as the internal clock signal as it is. Therefore, rising edge timings of the external clock signal and the internal clock signal become coincident regardless of the frequency of the external clock signal. Reduction in an operating margin within the circuit due to reduction in the pulse width of the internal clock signal is prevented. Thus, the circuit of the present invention can be used in the high frequency and the low frequency at the same time and reliability of the circuit can be improved.

Abstract: A PWM buffer circuit includes a duty cycle converting circuit and a frequency-fixed PWM signal generating circuit. The duty cycle converting circuit is used for receiving a first PWM signal and then generating a duty cycle reference voltage on the basis of the first PWM signal. The duty cycle reference voltage is a one-to-one mapping function of the first duty cycle. The frequency-fixed PWM signal generating circuit is used for receiving the duty cycle reference voltage and then outputting a second PWM signal with a fixed frequency. The second PWM signal has a second duty cycle, which is determined in accordance with the duty cycle reference voltage. In addition, the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.

Abstract: A circuit for controlling pulse width of a signal for driving a light emitting element, includes a pulse width control circuit capable of responding to multi-bit rates in the same circuit structure. For this purpose, the pulse width control circuit has a Tr/Tf control section controlling at least one of a rise time Tr and a fall time Tf of an input signal according to the bit rate of the input signal; a waveform shaping section shaping a signal output from the Tr/Tf control section to generate an output signal; and a control signal generating section generating a control signal for controlling an operation of the Tr/Tf control section based on pulse width control information.

Abstract: A current-mode pulse-width-modulation (PWM) circuit converts analog current signals into pulse signals. The PWM circuit includes a first I-V converter and one or more second I-V converters, each of the one or more second I-V converters being coupled to one of the current signals. Each of the first and second I-V converters is also coupled to a current generator which generates a current that linearly changes with time. For each of the first and second I-V converters, when a polarity of the input current thereof changes, an output changes between a high voltage level and a low voltage level. A logic circuit is coupled to the first and each second I-V converter to obtain a pulse signal that has a pulse width linearly proportional to the current level of the respective current signal.

Abstract: Two comparators are arranged to generate a pulse-width modulator (PWM) control pulse. The first comparator is arranged to start the PWM control pulse, while the second comparator is arranged to stop the PWM control pulse. The first comparator can be a high speed CMOS comparator that includes a built-in offset. The first and second comparators can be arranged such that the built-in offset of the first comparator dominates the overall operation at the start of the control pulse. The start of the PWM control pulse is initiated by a ramp voltage and a predetermined reference level instead of a clock edge. The PWM control pulse can be linearly varied down to a zero pulse width. The PWM control pulse may be used to control the on-time of the switching element in a switching-type converter.