Abstract: The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.

Abstract: An output circuit including an input terminal; an output terminal; a PMOS transistor connected with a positive side of a power voltage and the output terminal; a NMOS transistor connected with a negative side of the power supply voltage and the output terminal; a first inverter, to which a gate voltage of the PMOS transistor is input and which exhibits hysteresis in threshold voltage; and a second inverter, to which a gate voltage of the NMOS transistor is input and which exhibits hysteresis in threshold voltage, wherein an OR logic signal of the input signal and a signal obtained by inverting an output signal from the second inverter is input to a gate of the PMOS transistor, and an AND logic signal of the input signal and a signal obtained by inverting an output signal from the first inverter is input to a gate of the NMOS transistor.

Abstract: A sub-circuit for facilitating the synchronization of event-based samples of signals in a cross-correlation circuit utilizing event-based sampling is provided. The sub-circuit alternatively integrates one of the signals to be cross-correlated and alternates between the signals in response to the output of a hysteretic comparator. The invention extends to a method of manipulating the input signals to a cross-correlation circuit utilizing event-based sampling so-as to facilitate the synchronization of the event-based samples of the signals.

Abstract: A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node and the output node. Each of the capacitance stages includes a capacitor, and a control transistor having a gate capacitance in series with the capacitor, wherein the gate capacitance is configured to be added to the capacitance of the capacitor between the input node and the output node.

Abstract: A comparator (12A,12B) includes a first differential input stage (10) including first (MN2) and second (MN3) input transistors and a load (MP9,MP10), the first input transistor (MN2) having a gate, source, and drain coupled to a first input voltage (Vin?), a first tail current source, and the load, respectively. The second input transistor has a gate and source coupled to a second input voltage (Vin+) and a first tail current source. A second differential input stage (11) includes a third (MN4) and fourth (MN5) input transistors, the third input transistor having a gate and source coupled to a first reference voltage (Vref+) and the second tail current source, respectively. The fourth input transistor (MN5) has a gate and a source coupled to a second reference voltage (Vref?) and the second tail current source, respectively. Drains of the third and fourth input transistors are coupled to the load.

Abstract: A Schmitt trigger has a first inverter, a second inverter, a bias means, and a transistor. The inverter has an input and an output. The second inverter has an input coupled to the output of the first inverter and has an output. The bias means provides a first bias voltage on a first output terminal. A magnitude of the bias voltage is selectable by a first input signal. The transistor has a first current electrode coupled to a first power supply terminal, a control electrode coupled to the output of the second inverter, a second current electrode coupled to the output of the first inverter, and a body coupled to the first output terminal. Selectability of the magnitude of the bias voltage provides selectability of the hysteresis of the Schmitt trigger.

Abstract: Embodiments of the invention relate to a signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal. Advantageously, the signal receiver according to embodiments of the invention comprises a conversion stage inserted between the first and second voltage references and connected between the first and second input terminals of the signal receiver and an input terminal of an hysteresis comparator, connected in turn to the output terminal of the signal receiver. In particular, the conversion stage performs a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by the hysteresis comparator.

Abstract: An IBOC broadcasting receiver that uses two different bit error rates as threshold values in receiving hybrid broadcasting in a simultaneous broadcasting format, and switches between digital broadcasting reception and analog broadcasting reception based on the two threshold values. The IBOC broadcasting receiver counts the number of occurrences of switching between digital broadcasting reception and analog broadcasting reception in a specified period of time, and increases a hysteresis width between the two threshold values when the number of occurrences of switching counted exceeds a specified number.

Abstract: Embodiments of the present invention provide an oscillator circuit having a steady output frequency that is independent of the supplied voltage. This oscillator includes a Schmitt trigger circuit which may be implemented within an integrated circuit of a wireless terminal or other like portable electronic device. The Schmitt trigger circuit receives a threshold voltage input and a second voltage input. The Schmitt trigger circuit generates an output voltage equal to either a first output voltage or a second output voltage based on the results of comparing the threshold voltage input to the second voltage input. An RC network may be coupled to the output of the Schmitt trigger circuit and is operable to supply the second voltage input to the Schmitt trigger circuit.

Abstract: A semiconductor integrated circuit includes a first external terminal for receiving a voltage converted by a resistance portion from a current varying in response to an extrinsic factor, a second external terminal for externally outputting the voltage received at the first external terminal as a detection signal, a control circuit outputting a control signal for changing a resistance value of the resistance portion based on the voltage received at the first external terminal, and a third external terminal for outputting the control signal to the resistance portion.

Abstract: A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D?). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q?). One of the outputs (Q?) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.

Abstract: A dynamic flip-flop circuit which outputs an output signal on which a digital data signal is reflected based on a clock, includes: a first control stage configured to output a signal having a level inverted from that of the digital data signal within a period within which the clock has a second level; a second control stage configured to output a signal of a first level within the period within which the clock has the second level and a signal of a level within another period within which the clock has the first level; a third control stage configured to output an output signal of the first level within a period within which the signal outputted from the second control stage has the second level; and a phase adjustment circuit configured to adjust the phase to produce a second clock and supply the second clock to the third control stage.

Abstract: Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Abstract: An adaptive hysteresis receiver processes a high speed digital signal. A differential receiver circuit compares the high speed digital signal to a reference voltage to generate an output signal. A register circuit latches the output signal, according to a clock signal, to produce a control signal. A reference voltage generator generates the reference voltage, from a plurality of voltages defining a deep hysteresis level and a shallow hysteresis level, in response to the output signal and the control signal.

Abstract: A hysteresis circuit including a comparator and capacitive voltage divider circuit. The capacitive voltage divider circuit includes a first capacitor coupled between an input terminal and a positive comparator input, a second capacitor coupled between ground and the positive comparator input, and a third capacitor coupled between the comparator output and positive comparator input. A reference voltage is applied to the negative comparator input. The comparator is powered by the input signal provided on the input terminal. When the voltage on the positive comparator input is less than the reference voltage, the third capacitor is effectively coupled in parallel with the first capacitor. When the voltage on the positive comparator input is greater than the reference voltage, the third capacitor is effectively coupled in parallel with the second capacitor.

Abstract: A hysteresis circuit applied to a comparator and an amplifier circuit thereof are provided. A hysteresis circuit is disposed on a positive feedback path of the comparator, such that the comparator resists noise interferences, and the hysteresis circuit has a feature of not affecting the feedback voltage signal, thereby making the hysteresis range of the comparator be more precise.

Abstract: Hysteresis circuit 10 is composed of three inverters 40, 42, 44. Node NB in hysteresis circuit 10 is connected to the input terminal of transition-detecting part 14 of transmission control part 12. Transition-detecting part 14 detects the timing of the start of the output inversion operation and the timing of the completion of the transition in hysteresis circuit 10 corresponding to potential VB of node NB, and it controls activation/deactivation of inverter 50 on the signal transmission path.

Abstract: Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Abstract: The present invention provides a data latch circuit. The data latch circuit includes a first data latch unit, a second data latch unit, a third data latch unit, and a phase selector. The first data latch unit is used for latching a first input data according to a first clock signal and outputting a first output data. The second data latch unit is used for latching the first output data according to a second clock signal and outputting a second output data. The third data latch unit is used for latching the second output data according to a third clock signal and outputting an output data. The phase selector is coupled to the second data latch unit for generating the second clock signal to the second data latch unit according to phase relation between the first clock signal and the third clock signal.

Abstract: A digitally programmable hysteresis comparator a includes digitally programmable variable resistor. One or more control bits are operable to modify the resistance of the variable resistor, and such modification is operable to modify the hysteresis width of the comparator.

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

Abstract: To maintain the noise removal characteristic of a Schmidt trigger circuit stably. There are provided a Schmidt trigger circuit 10 constituted from a Vp/Vn setting unit 11 for determining the threshold level of an input signal and an RS latch unit 12, a driver unit 13 having a low-pass filter function of passing a pulse signal with a predetermined width or more, output from the Schmidt trigger circuit 10, and an operating current setting and sensor unit 14 for changing a supply voltage and supplying the changed supply voltage to an inverter INV4 having the low-pass filter function so that the inverter INV4 changes the width of a pulse to be passed through. The operating current setting and sensor unit 14 includes a sensor circuit 16 having a P-ch transistor MP2 and an N-ch transistor MN2 that are connected in series for setting the supply voltage.

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.

Abstract: A comparator includes a differential amplification circuit having differential input transistors and load transistors, an output transistor for outputting an output value of the comparator, a diode having a cathode connected to a ground, a current output circuit, a resistor connected between an anode of the diode and the bases of the load transistors. When the output transistor is in the OFF state, the diode clamps the voltage of the resistor to a forward voltage so that no current flows through the resistor. When the output transistor is in the ON state, the resistor has a slight voltage so that a slight current flows through the resistor. Thus, a threshold voltage of the comparator has a slight hysteresis without increase in resistance of the resistor.

Abstract: A simplified comparator circuit (10) having hysteresis and lower power requirements for its implementation. The circuit (10) includes 2 minimum-sized MOSFETs (MN4, MN5) providing feedback from the circuit output to an input device (MN1) body to produce hystereis, requiring very little power. This invention is suitable for applications not requiring a precisely set hysteresis magnitude.

Abstract: Disclosed is a Boundary-Scan test receiver for capturing signals during board interconnect testing. The test receiver has a comparator with a first input to receive signals during board interconnect testing, and a second input to receive a reference voltage. A programmable hysteresis circuit is coupled to at least one of the comparator's inputs. The programmable hysteresis circuit may be configured to program a hysteresis voltage and/or a hysteresis delay, both of which help prevent the comparator from integrating signal noise.

Abstract: A signal detector circuit and digital signal receiver implementing the same. In one embodiment the digital signal receiver includes a switch point detector having a detector output and including a transistor array comprising one or more pull-up branches and one or more pull-down branches. A switch point control circuit is coupled to the switch point detector. The switch point control circuit generates branch enable signals for selectively enabling or disabling said one or more pull-up branches and said one or more pull-down branches in a detector output polarity dependent manner.

Abstract: A comparator is provided, which compares an input voltage and a reference voltage by using a plurality of inverting circuits connected in series. The comparator includes a first inverting circuit, a second inverting circuit, a feedback path, and a capacitor arranged on the feedback path. The first inverting circuit inverts a difference between the input voltage and the reference voltage for output. The second inverting circuit further inverts the output of the first inverting circuit for output. The feedback path feeds back the output of the second inverting circuit to the input side of the first inverting circuit. The capacitor causes hysteresis such that an increasing threshold and a decreasing threshold of the second inverting circuit corresponding to an increase and a decrease of the input voltage have a difference therebetween.

Abstract: In one embodiment, a comparator is provided with a first differential input stage that receives an input voltage and a reference voltage and produces a first differential output, and a second differential input stage that has differential inputs and produces a second differential output. A comparator stage produces a comparator output in response to the first and second differential outputs. The comparator also has a hysteresis control circuit, the components of which include 1) a resistor and a hysteresis regulating voltage input, coupled between the differential inputs of the second differential input stage, 2) first and second current generators, and 3) at least one switch, under control of the comparator output, to alternately enable different combinations of the first and second current generators, thereby inducing a first or a second current through the resistor.

Abstract: The present invention is constructed of a first input circuit having a higher logic level VIH made up of a first inverter circuit 22 controlled by an input signal and an N-type MOSFET 16 controlled by a latch circuit 24 which stores a preceding state, a second input circuit having a lower logic level VIL made up of a second inverter circuit 23 controlled by an input signal and a P-type MOSFET 15 controlled by a latch circuit which stores a preceding state and the latch circuit 24 which stores a preceding state.

Abstract: A hysteresis current comparator includes a first current comparison unit, a second current comparison unit, and a control circuit connected to the two current comparison units. The first current comparison unit compares a first reference current with an input current and outputs a first voltage accordingly. The second current comparison unit compares a second reference current with the input current and outputs a second voltage accordingly. The control circuit generates an output voltage according to the voltages output by the two current comparison units, or generates an output voltage according to the voltages output by the two current comparison units and the output voltage of the control circuit at a former state.

Abstract: An input voltage is applied to an inverting input terminal of a comparator having no hysteresis. A first constant voltage is divided by resistors to create a reference voltage. The reference voltage is applied to a non-inverting input terminal of the comparator through a resistor. Only while an output voltage of the comparator is a low level, a predetermined constant current is supplied to a supply point of the reference voltage and a constant current of the same magnitude is absorbed from the non-inverting input terminal of the comparator.

Abstract: A Schmitt trigger includes a PMOS transistor and an NMOS transistor, each having a gate coupled to an output voltage terminal. The Schmitt trigger is configured such that an input voltage that switches on the PMOS transistor determines a low voltage threshold and an input voltage that switches on the NMOS transistor determines a high voltage threshold. By coupling devices such as diodes to either or both of the PMOS and NMOS transistors, a margin between the low voltage threshold and ground and between the high voltage threshold and a supply voltage are maintained as the supply voltage is reduced. In addition, hysteresis is maintained or increased as supply voltage is increased.

Abstract: A power-on reset circuit includes a Schmitt trigger circuit, a voltage divider, and a compensate circuit. The Schmitt trigger circuit includes a plurality of MOS devices of a uniform threshold voltage (Vt) for determining a power reset trigger level. The voltage divider is coupled to an input of the Schmitt trigger circuit for tracking the supply signal. The compensate circuit is operative to generate a small reset pulse to compensate for temperature and the supply signal variation effect.

Abstract: A method and apparatus for an output buffer with dynamic impedance control have been disclosed.

Abstract: Programmable dynamic amplifiers with hysteresis are provided. The hysteretic amplifiers have a first input voltage threshold when the output voltage is at a high voltage and a second input voltage threshold when the output voltage is at a low voltage. A multiplexer controls the hysteretic threshold voltages in response to the output signal of the amplifier. The hysteretic amplifiers can be programmed to have positive or negative hysteresis. When the amplifier is programmed with positive hysteresis, the output voltage transitions after the input voltages have both reached a common voltage value. When the amplifier is programmed with negative hysteresis, the output voltage transitions before the input voltages have both reached a common voltage value.

Abstract: A hysteresis detection method has two reference voltages Vref1, Vref2 relative to an input voltage Vin. It is determined whether the input voltage Vin becomes higher than or lower than the reference voltages Vref1, Vref2, and a judged result is outputted. In the initial stage in which the detection is started, regardless of the magnitude of the input voltage Vin, the reference voltage is fixed to any one of the reference voltages Vref1, Vref2. There are provided a hysteresis detecting method and a hysteresis detecting circuit in which, in the hysteresis detection having two reference voltages and which determines whether the input voltage is higher than or lower than the two reference voltages, one of the reference voltages can be judged and the judged result can be outputted regardless of the magnitude of the input voltage in the initial state in which the reference voltage is stabilized from the time in which the circuit is actuated.

Abstract: The present invention provides one hysteresis circuit device. The hysteresis circuit device includes an input voltage level generator, a switch, and a comparator. The input voltage level generator is used to receive an input signal and output a high input voltage and a low threshold voltage. The switch is used to receive the high input voltage and the low threshold voltage, and output a switch output signal according to a digital signal. The comparator has one terminal used to receive the switch output signal, and another terminal used to receive a reference signal. Then, the comparator outputs the digital signal. The hysteresis circuit device can change their voltage levels by an external circuit; therefore, the noise resulting from the input signal can be avoided and the problem of false detection of the comparator can be solved.

Abstract: An On-Off control circuit between the IEEE1394a and IEEE1394b compliant physical layer (PHY) output driver circuitry and the glass fiber optical physical medium dependent (PMD) sub-layer within the architecture of the IEEE 1394b standard addresses the stability issue incurred by electronic circuit's inherent noise that interferes with the connection detecting procedure defined by the connection management protocol (CMP) of the IEEE 1394b standard. The circuit includes of a voltage divider to provide a reference voltage of about 50% of the output common mode voltage, a voltage comparator, and a feedback coupled to the positive input of the comparator to eliminate possible oscillation. The negative input of the comparator may be connected to the mid point of TPB termination network and the positive input of the comparator may be connected to the output of the voltage dividing circuit. The output of the comparator may be connected to the transmission enable bar input of the optical transceiver.

Abstract: The differential input receiver provides constant symmetrical hysteresis over a wide input signal range. The differential input receiver includes a pair of complementary differential comparators having common input terminals, a pair of series connected complementary current mirrors each having source terminals driven by the output terminals of the corresponding differential comparator, a pair of transistors connected in series across each differential pair transistor in each differential comparator to form a potential divider across it, and a pair of series connected inverting buffers connected to a common output of the differential comparators to provide the final output. The individual buffer outputs are fed back to the control terminals of the series connected transistors in a manner that provides positive feedback thereby providing equal rise-time, fall-delay and transition times in the output signal.

Abstract: A variable drive strength hysteresis input circuit is disclosed that comprises pull-up circuitry and pull-down circuitry. A variable drive strength circuit changes the pull-up drive strength and the pull-down drive strength in response to receiving an input voltage signal that transitions either from a low level to a high level or from a high level to a low level. In one advantageous embodiment the variable drive strength hysteresis input circuit comprises four p-channel MOSFET transistors and four n-channel MOSFET transistors. The invention efficiently reduces transition noise in the inputs to an integrated circuit chip.

Abstract: An on-chip test mechanism for transceiver power amplifier and oscillator frequency for use with the transmitter portion of an integrated RF transceiver. The RF output from the power amplifier in the transmitter is input to a built-in dedicated analog comparator having a configurable threshold. The threshold is adjusted to a predetermined level at which crossings start to occur at the comparator output. The comparator outputs pulses only if the power amplifier output is above a minimum configurable level. The comparator output is input to a frequency divider whose frequency output is tested by a low cost external tester to determine the actual RF frequency thereby confirming generation of the correct oscillator frequency and that the amplitude of the signal at the output of the power amplifier is sufficiently high for the configurable threshold level to be exceeded, thereby determining the compliance of the output power with its defined specifications.

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: A static receiver having a first inversion threshold for received signals undergoing a HIGH-to-LOW transition, and a second inversion threshold for received signals undergoing a LOW-to-HIGH transition, where the first inversion threshold is greater than the second inversion threshold. One embodiment comprises a static receiver, a pFET, and a nFET, where when a HIGH-to-LOW transition is being received at the receiver's input port, the pFET is coupled to the input port so as to contribute to raising the inversion threshold, and when a LOW-to-HIGH transition is being received at the input port, the nFET is coupled to the input port so as to contribute to lowering the inversion threshold. Other embodiments are described and claimed.

Abstract: An apparatus and method of a programmable hysteresis comparator capable of producing a digital signal in response to differential input signals is disclosed. In one embodiment, the programmable hysteresis comparator includes a hysteresis offset programmable circuit that is operable to selectively provide a hysteresis offset in response to a programmable hysteresis offset control signal. The programmable hysteresis comparator further includes a comparator circuit, which is capable of receiving differential input signals. The hysteresis comparator is operable to output a digital signal in response to differential input signals and the hysteresis offset.

Abstract: Comparator circuits, including rail-to-rail comparator circuits, can implement inverter structures such as current-starved inverters to provide hysteresis to the comparator's output. For example, a current-starved inverter can have its input driven by the comparator output and add current to the currents produced by the comparator's input stage. The inverter current can be derived from bias sources used to bias the input stage of the comparator so that the inverter current can track the input stage bias currents.

Abstract: The invention provides a high-speed buffer that may used at the input of an integrated circuit, such as an input buffer. This buffer may be configured for use as a standard buffer with a single switching threshold, such as a TTL-to-CMOS buffer, or used as a Schmitt trigger with hysteresis, which as at least two switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a reference output voltage in response to a plurality of reference voltages. The second circuit may be configured to generate an output voltage in response to the reference output voltage and an unknown voltage. The output voltage may comprise accurately controlled hysteresis.

Abstract: A hysteresis circuit for use in a comparator having a first and a second transistors as an input stage and a constant current source. The hysteresis circuit comprises a first resistor disposed between a source of the first transistor and the constant current source and a second resistor disposed between a source of the second transistor and the constant current source, and comprises a first and a second current generating means. The first current generating means supplies a current to the source of the first transistor and derives a current out from the source of the second transistor if an output signal of the comparator is a first logic value, while the second current generating means supplies a current to the source of the second transistor and derives a current out from the source of the first transistor if the output signal of the comparator is a second logic value.