Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses a parallel transistor and an enabling transistor connected in parallel to one of the differential pair transistors to create hysteresis. The parallel transistor and enabling transistor are used to generated an effective offset voltage which must be overcome for the comparator to switch states.

Abstract: A hysteresis generator for providing a comparator with a precision hysteresis reference input. An output of the comparator controls a switch which determines whether or not a reference current is applied to a resistor. The resistor is connected between a reference voltage and an input to the comparator. A buffer amplifier provides the reference voltage to the resistor. The reference current is taken from a second resistor connected between the output of the buffer amplifier and the input of a current mirror. The current mirror applies its output current to the first resistor. A diode may be inserted between the output of the buffer amplifier and the first resistor to make the hysteresis voltage generated by the current applied to the first resistor substantially temperature independent.

Abstract: A thermal shut down circuit with built-in temperature hysteresis, comprising first and second transistors configured as a bistable trigger circuit. The two transistors switch either a first or second emitter current through a bias resistor, thereby establishing a voltage hysteresis. By applying a reference voltage to the base of the first transistor, temperature dependent state transitions occur. A buffer transistor coupled to the collector of the second transistor allows the thermal shut down circuit to turn ON or OFF an auxiliary circuit. Thermal communication between the auxiliary circuit and the base-emitter junction of the first transistor allows the thermal shut down circuit to shut down the auxiliary circuit when the temperature exceeds a shutdown temperature, and thermal hysteresis built into the thermal shut down circuit prevents undesirable ON-OFF oscillation of the auxiliary circuit.

Abstract: In a voltage-limiting circuit, the voltage to be limited is applied to the terminals of a resistive line, and the current flowing in this line is amplified by a current mirror that thus produces a reference current. A current-controlled voltage source receives this reference current and produces a reference voltage. This reference voltage is given to a hysteresis comparator that switches over for two distinct values of the voltage to be regulated. The disclosed device is particularly useful in the field of the load pumps used in electrically programmable memories.

Abstract: A hysteresis limiter including a hysteresis limiting circuit, a signal variance tracking device and a reference voltage selecting device can dynamically track variance of signals and adjust a reference voltage. The signal variance tracking device enters an offset tracking mode when there has not been any variance occurring in an output of the hysteresis limiting circuit for a predetermined period of time. In the offset tracking mode, the reference voltage selecting device continuously activates a change of the reference voltage until the output of the hysteresis limiting circuit becomes unstable. The unstable state implies that an offset is located, so treatment of the input signals can then be proceeded.

Abstract: A power-on reset (POR) circuit that initially asserts the POR signal when the supply voltage is turned on. As the supply voltage increases the POR signal is deasserted when it is determined that the supply voltage is sufficiently high to make storage elements in a circuit being controlled by the POR signal fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough to render the storage elements in the controlled circuit incapable of holding accurate data. The POR signal is then reasserted at this low power supply voltage level. The low power supply voltage level that triggers the reassertion of the POR signal is lower than the sufficiently high power supply voltage level that triggers the deassertion of the POR signal, thus allowing the power supply voltage level to drop significantly before the POR signal is reasserted. A control signal allows the POR signal to be generated in response to different power supply voltage levels.

Abstract: An edge detector for producing output signals in a manner dependent on positive and/or negative edges of an input signal comprises a control circuit (10), by which a reference signal level (V.sub.ref) available at a storage element (C) may be continuously assimilated at a predeterminable first level change rate (PG.sub.1) to the input voltage level (V.sub.E). It moreover includes at least one comparison circuit (12), which supplies an output signal (V.sub.A, V.sub.A ') indicative of the occurrence of an edge, when the input voltage level (V.sub.E) changes by at least a predeterminable relative threshold value (U.sub.off) in relation to the reference voltage level (V.sub.ref). The control circuit (10) comprises a delay means (14) whose delay time (.DELTA.t.sub.D) causing a delay in the assimilation of the reference voltage level is selected to be equal to the ratio of the predeterminable relative threshold value (U.sub.off) to the predeterminable first level change rate (PG.sub.1).

Abstract: A hysteresis comparator circuit using, for a virtually power-free detection of the voltage value to be subjected to a comparison, a differential stage utilizing on one end load transistors and on the other hand a negative feedback stage and preferably a current mirror stage. The control electrode of one load transistor is fed with the voltage to be used for the comparison. The control electrode of the other load transistor is fed with a reference voltage on the basis of which this load transistor forms a constant load impedance. The second load transistor has a third load transistor connected in parallel thereto, which in response to the output signal of the comparator is either conducting or blocking, so that in accordance with the output signal of the comparator, an additional load impedance is connected in parallel to the impedance of the second load transistor or no such connection is made.

Abstract: A control circuit, in particular for a direct current control in positioning systems, comprising a differential circuit (1), a control logic (2) and a full bridge (3) connected between a supply voltage V.sub.S and a reference potential GND. The differential circuit (1) has a first hysteresis comparator (HC1) and a second hysteresis comparator (HC2). The two comparator inputs (HC1-, HC1+, HC2-, HC2+) of the two hysteresis comparators (HC1, HC2) are connected each to one of two input terminals (IN1, IN2) of the control circuit and crosswise to a comparator input of the respective other comparator (HC1, HC2). The inverting input of each comparator (HC1, HC2) is connected to the non-inverting input of the respective other comparator. (FIG.

Abstract: A method of repeating a pulse signal comprised of outputting a signal at a first voltage level upon a first rising edge of the pulse signal exceeding a low threshold, then raising the threshold and outputting the signal at another voltage level upon a second trailing edge of the pulse signal dropping below the raised threshold. An improved VLSI circuit has at least one conductive track containing distributed parasitic elements, the track being divided into two or more separate segments, a repeater connecting each of the segments, and apparatus for modulating the threshold of the repeater prior to and/or during the interval of a pulse carried by the track.

Abstract: A comparator with hysteresis in bipolar technology having a voltage/current converter with a voltage input forming the comparator input connection, and a current output, a bistable current source with a current feeding connection coupled with the current output of the voltage/current converter and a current output connection forming the comparator output, the bistable current source being currentless in a first stable state and consuming current only in the second stable state, the firing current which must be fed to the current feeding connection to switch the bistable current source from the currentless state to the power-consuming state being different from the quenching current which must be fed to the current feeding connection to switch the bistable current source from the power-consuming state to the currentless state, to obtain a hysteresis of the comparator, and all transistors being formed as bipolar transistors.

Abstract: A hysteresis circuit including first and second voltage reference circuits responsive to an input control signal for providing first and second voltage levels connected in series to produce a higher voltage level; a first switching circuit, responsive to the voltage reference circuits to turn on and provide an output drive signal when the higher voltage is reached; a second switching circuit, responsive to the first switching circuit turning on, for removing one of the first and second voltage levels to produce a lower voltage level; the first switching circuit turning off in response to the input level control signal decreasing below the lower voltage level.

Abstract: This invention relates to the operation of common electronic comparators and particularly to an electronic circuit with a comparator for the operational test of integrated circuits (ICs). According to the invention, the electronic circuit comprises a common comparator with an input, an output and a reference input. To the reference input a constant reference voltage is applied. The input voltage to be compared with the reference voltage is superimposed to a time-dependent signal and the resulting voltage is applied to the input of the comparator.

Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses a parallel transistor and an enabling transistor connected in parallel to one of the differential pair transistors to create hysteresis. The parallel transistor and enabling transistor are used to generated an effective offset voltage which must be overcome for the comparator to switch states.

Abstract: In a voltage-limiting circuit, the voltage to be limited is applied to the terminals of a resistive line, and the current flowing in this line is amplified by a current mirror that thus produces a reference current. A current-controlled voltage source receives this reference current and produces a reference voltage. This reference voltage is given to a hysteresis comparator that switches over for two distinct values of the voltage to be regulated. The disclosed device is particularly useful in the field of the load pumps used in electrically programmable memories.

Abstract: A wave-shaping circuit comprises a dynamic hysteresis generating circuit for generating a dynamic hysteresis voltage having a certain crest value and whose signal level attenuates at a speed proportional to a number of engine revolutions to mask an ignition noise superimposed on an input signal, and a threshold generating circuit for generating a threshold voltage whose signal level increases/decreases in proportion to the number of engine revolutions to mask an interference noise superimposed on the input signal and to reliably detect a minimum level of the input signal. Either the dynamic hysteresis voltage or the threshold voltage, whichever is higher, is selectively output as a comparison reference signal through a high-level selecting circuit.

Abstract: A power-up circuit with hysteretic characteristics for regulating the activation of one or more output buffers of an extended logic circuit. The hysteresis of the power-up circuit of the invention permits turn on of a switching transistor of the circuit at one threshold voltage level and maintains the active state of that switching transistor until a second lower threshold voltage level. The hysteresis is achieved by providing two separate and electrically isolated control paths that are connected to the control node of the switching transistor. The first control path includes a plurality of diode devices designed to regulate the power supply level required to turn on the switching transistor. The second control path also includes diode devices but in lesser numbers so that, once the switching transistor is turned on by the first control path, it remains on in spite of fluctuations at the power supply rail.

Abstract: A circuit for providing programmable hysteresis levels is disclosed. The circuit includes comparators for producing output signals when an input signal crosses respective set points and a hysteresis circuit for establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. The hysteresis circuit includes a programmable hysteresis input for adjusting the hysteresis differential to different preset and intermediate hysteresis levels.

Abstract: A hysteresis system with constant threshold voltage, regardless of an increase or decrease of an output signal by detecting the increase/decrease state of the input signal, and includes a second voltage signal generator for generating a second voltage signal which is gradually increased when a first voltage signal inputted is high and is gradually reduced when the first voltage signal inputted is low, a voltage comparator for comparing the reference threshold voltage signal with the second voltage signal generated from the second voltage signal generator and producing a corresponding value; a threshold voltage initialization circuit for comparing reference voltage with the first voltage signal inputted and producing a threshold voltage initialization signal in accordance with a corresponding value; and a threshold voltage generator to which an output signal produced from the voltage comparator and the threshold voltage initialization signal produced from the threshold voltage initialization circuit are fed ba

Abstract: A power-on reset (POR) circuit that initially asserts the POR signal when the supply voltage is turned on. As the supply voltage increases the POR signal is deasserted when it is determined that the supply voltage is sufficiently high to make storage elements in a circuit being controlled by the POR signal fully operational. The POR signal is kept deasserted until the power supply voltage level drops to a level low enough to render the storage elements in the controlled circuit incapable of holding accurate data. The POR signal is then reasserted at this low power supply voltage level. The low power supply voltage level that triggers the reassertion of the POR signal is lower than the sufficiently high power supply voltage level that triggers the deassertion of the POR signal, thus allowing the power supply voltage level to drop significantly before the POR signal is reasserted. A control signal allows the POR signal to be generated in response to different power supply voltage levels.

Abstract: A method for providing programmable hysteresis levels includes producing output signals when an input signal crosses respective set points and establishing a hysteresis in the output signals. When a comparator's output signal is "on", the input signal is shifted by a hysteresis differential. The output signal is terminated when the shifted input signal returns to the set point. A programmable hysteresis input is adjusted to set the hysteresis differential to different preset and intermediate hysteresis levels.

Abstract: A motor current detection circuit is formed of a current detector for detecting an overloaded state of a motor by comparing a motor current value, which represents current flowing through the motor, with a predetermined reference value, and a hysteresis generating circuit for generating, in the current detector, a hysteresis characteristic corresponding to an integrated value with respect to time of an increment amount by which the motor current value exceeds the reference value. Chattering in output of the current detector is reduced so that an overloaded state of the motor can be detected quickly.

Abstract: A current source gate drive circuit for simultaneous firing of a set of series or parallel thyristors is described. The circuit includes two current loops, each of which serves as a current transformer primary. Electrically insulating tubes enclose the current loops. Current transformer cores, around which are wound a certain number of secondary turns, surround the current loops, thus magnetically coupling the primary current of the current transformer to the secondary turns. Thyristor gate driver circuits are electrically coupled to the current transformer cores. Each of the thyristor gate driver circuits receives and rectifies ac current signals from the current loops and forms a current pulse train firing signal. Each thyristor gate driver circuit has a corresponding thyristor that is fired by the current pulse train firing signal. The thyristors operate at a high voltage, but are electrically isolated from the current loops by the insulating tubes.

Abstract: A method of repeating a pulse signal comprised of outputting a signal at a first voltage level upon a first rising edge of the pulse signal exceeding a low threshold, then raising the threshold and outputting the signal at another voltage level upon a second trailing edge of the pulse signal dropping below the raised threshold. An improved VLSI circuit has at least one conductive track containing distributed parasitic elements, the track being divided into two or more separate segments, a repeater connecting each of the segments, and apparatus for modulating the threshold of the repeater prior to and/or during the interval of a pulse carried by the track.

Abstract: A differential comparator with a hysteresis proportional to the peak value of the input signal. The comparator operates independently of the magnitude of the supply voltage and of the ambient temperature while handling both differential and single-ended inputs and without introducing a delay between the input and the output.

Abstract: A BiCMOS power-up circuit for delaying the operation of an extended circuit until the voltage available to the high-potential power rail of the extended circuit is sufficiently high that all elements of the extended circuit will be powered at a high enough voltage to function correctly. The power-up circuit of the present invention has its most direct application to three-state output buffers connected to a common bus, and in this context this circuit can maintain the output buffers in their high-Z, inactive state until the voltage available from the circuit-energizing power-supply has risen high enough that all of the stages of the buffers will operate correctly, and in particular will not be current-sourcing and current-sinking simultaneously.

Abstract: A semiconductor device includes a differential amplifier and a first and a second pull-up transistor for generating a reference voltage. The second pull-up transistor has a gate connected to an output terminal of the differential amplifier. The differential amplifier is such that, when an output voltage thereof previously outputted is at a high level, both the first and second pull-up transistors become conductive so that the reference voltage becomes equilibrium at a high level voltage, and when an output voltage previously outputted is at a low level, the first pull-up transistor becomes conductive and the second pull-up transistor becomes non conductive so that the reference voltage becomes equilibrium at a low level voltage. With this arrangement, a high speed operation of the differential amplifier is realized.

Abstract: A digital input circuit including a first digital buffer for receiving a digital data signal and for providing a first buffered digital data output, the first digital buffer having a first switching threshold voltage; a second digital buffer for receiving the digital data signal and for providing a second buffered digital data output, the second digital buffer having a second switching threshold voltage that is greater than the first predetermined switching threshold voltage; a selection circuit responsive to the first buffered digital data output and the second buffered digital data output for providing a selection circuit output that is a replica of the first buffered digital data output or the second buffered digital data output; and a flip-flop for receiving the selection means output and providing a flip-flop output that is indicative of the logical state of the digital data signal.

Abstract: A comparator (10) provides a high speed comparison between at least two input signals and includes at least two stages (12) and (14). Each stage (12 and 14) includes a pair of transistors (24), a complementary pair of transistors (28) and an enabling transistor (26). The stages are coupled to provide positive feedback back to the first stage (12). A controller (15) operably couples to the enabling transistors. When the first input signal (16) is at a higher voltage level than the second input signal (18), the first comparison output (20) goes low. Conversely, when the second input signal (18) is at a higher voltage level than the first input signal (16), the second comparison output (22) goes low. When the first comparison output (20) goes low, the second enabling transistor (34) is disabled by the controller (15). When the second comparison output goes low, the first enabling transistor (26) is disabled by the controller (15).

Abstract: A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.

Abstract: A drive circuit includes first and second circuit sections. The first circuit section maintains, during an initial stage of a transient period of an input signal, its output level before the signal transition and supplies after the transient period an output signal responsive to the signal transition. The second circuit section has a first circuit portion receiving the input signal and a second circuit portion, responsive to the input signal, and the output of the first circuit section, to accelerate the signal transition of the first circuit portion. Signal delay in a signal transition due to a large parasitic capacitance and resistance can be recovered by the drive circuit. The drive circuit has a large noise margin and operates at a high-speed and in a wide frequency range.

Abstract: An integrated circuit memory (114) has a power supply independent address buffer (50) that comprises an inverter (60), a bipolar transistor (67), and a P-channel transistor (68). The inverter (60) has an output terminal coupled to a base of the bipolar transistor (67). The P-channel transistor (63) is for injecting a current at the output terminal of the inverter in response to a reference voltage. The reference voltage varies proportionally to variations of a power supply voltage in order to compensate for gate-to-source voltage changes of a P-channel transistor (61) of the inverter (60) that occurs as a result of a changing power supply voltage. For address buffer (50), a range of address transition times as a function of power supply voltage is decreased, thus improving an address set-up and hold time of the integrated circuit memory (114).

Abstract: A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply includes a voltage clamping stage (14) and a hysteresis switching stage (16). The voltage clamping stage (14) is formed of an N-channel resistor (M1), a first resistor (R1), and a second resistor (R2). The hysteresis switching stage (16) includes a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1).

Abstract: A preamplifier for use with currents developed by a photodetecting diode is disclosed wherein the currents are coupled to the base of an NPN transistor connected as a common emitter stage and a feedback resistor is connected by way of a buffer amplifier to the base to provide a standard transimpedance configuration. A control loop monitors the signal level by integrating the output of the buffer amplifier, and upon the detection of large signals the control loop causes a MOSFET in parallel with the feedback resistor to decrease the transimpedance and thereby increase the signal handling capability of the preamplifier. The control loop is also connected to a second MOSFET in parallel with the collector load resistor of said NPN transistor to decrease the effective collector load impedance for large signal levels.

Abstract: A circuit and method for generating a power-on reset signal with a designable hysteresis is disclosed. The circuit includes a low voltage stage, a high voltage stage, and a hysteresis stage. The low voltage stage includes a resistor in series with a current mirror. The high voltage stage includes a current mirror in series with a diode and two resistors. The hysteresis circuit includes a transistor connected across one of the two resistors. The method for generating the power-on reset signal includes the steps of sinking a power-on reset signal low when a voltage source reaches a first V.sub.be voltage threshold; driving the power-on reset signal high when the voltage source reaches a second threshold value; and providing hysteresis to the power-on reset signal.

Abstract: A VISS circuit for preventing image search malfunction occurrence due to variation in the speed of a video tape used in a video cassette recorder makes it possible to carry out a normal VISS operation by utilizing the pulse width of the Schmitt trigger pulse, which is varied in accordance with the change in speed of the video tape. The circuit includes a Schmitt trigger circuit capable of varying the width of the Schmitt trigger pulse in accordance with variation of upper and lower extreme voltage values of a control signal based on the speed signals after detecting the tape speed signals at the time of the recording and the control signals from the control head, the varied width of the Schmitt trigger pulse being supplied to a VISS operation circuit, and a control device for supplying a signal for varying the width of the Schmitt trigger pulse produced by the Schmitt trigger circuit in accordance with the tape speed.

Abstract: A Schmitt trigger circuit has a field effect transistor coupled between a first fixed potential and an output terminal, and a variable negative resistance circuit coupled between the output terminal and a second fixed potential; the gate of the field effect transistor and the control input of the negative resistance circuit are coupled to the input terminal of the Schmitt trigger circuit; wherein the negative resistance circuit includes a first field effect transistor coupled between the output terminal and the second fixed potential, and a gate coupled to an internal node; a second field effect transistor coupled between the internal node and the second fixed potential, and a gate coupled to the input terminal; and a third field effect transistor coupled between the first fixed potential and the internal node, and a gate coupled to the output terminal.

Abstract: There is added to a conventional magnetic-field detector, which includes a magnetic-field-to-voltage transducer such as a Hall element connected to a Schmitt trigger circuit, a DC voltage monitor circuit to produce a high binary monitor signal only when the DC supply voltage is within a predetermined normal band, and a logic circuit having one input connected to the output of the monitor circuit and a second input connected to the output of the Schmitt trigger circuit. During periods when the binary-Schmitt-output voltage remains high, corresponding for example to a high ambient magnetic field, noise spikes on the DC line can cause an anomalous change in the binary-Schmitt-output voltage of a magnetic-field detector from a high level to a low level.

Abstract: An automatic trigger circuit including: a two-arm current mirror including a first arm connected between a DC electrical supply and a ground, the first arm including a first transistor including a first source connected to the DC electrical supply, a first gate, and a first drain connected to the first gate; a second transistor including a second gate connected to the DC electrical supply, a second drain connected to the first drain and a second source; a third transistor including a third drain connected to the second source, a third gate for receiving a first level reference voltage, and a third source; and a fourth transistor including a fourth drain connected to the third source and a fourth source connected to the ground; and a second arm connected between the DC electrical supply and the ground, the second arm including a fifth transistor including a fifth source connected to the DC electrical supply, a fifth gate connected to the first gate and a fifth drain; and a sixth transistor including a sixth dr

Abstract: A differential type MOS transmission circuit includes a signal driving circuit and a signal receiving circuit to realize high speed transmission for a short distance transmission between different LSIs, etc. A pair of transmission lines between the signal driving circuit and the signal receiving circuit are driven by a pair of drivers in the signal driving circuit so as to take either one of three states, i.e. one state where both of the lines are in a precharged states and two states where either one of the lines is in a discharged state. A signal driving circuit includes signal generating circuits generating variations in control signals varying pulse-like in response to rise and fall of an input signal to thereby obtain the discharge state.

Abstract: An improved Schmitt trigger, especially useful for large scale integrated circuit applications, includes a buffer (inverter) having a pull up device and two pull down devices all connected between a voltage supply and ground, and each receiving the input signal at its gate terminal. A node between the output terminals of the pull down devices is connected to the output terminal of the Schmitt trigger. A feedback line connects the output terminal of the Schmitt trigger to the gate of an N-channel depletion device connected between the pull-up and pull-down devices. Also provided are two devices to control the timing of the Schmitt trigger; these two control devices are connected between the output terminal of the Schmitt trigger and the output terminal of the inverter.Also provided in one embodiment is electrostatic discharge protection connected to the Schmitt trigger input and output terminals, and in another embodiment a control device for turning on and off the supply voltage to the inverter.

Abstract: The present invention provides an integrator 5 with switched hysteresis for inductive proximity switches comprising a reference current source IREF connected between a reference voltage supply rail and a first side of a current mirror, a second side of the current mirror being connected to a proximity switch rectifier, the first side of the current mirror being connected to a capacitor CINT and to one input of a two input comparator, the other input of the comparator being held at a threshold level, wherein a fixed hysteresis current source IHYST is provided in parallel with the current reference source IREF, the fixed hysteresis current source IHYST producing a switchable current which is a fixed proportion of the current of the current reference source IREF, the fixed hysteresis current source IHYST being switched on (off) when a target is detected and off (on) when no target is detected. This invention provides for reduction of effects detrimental to the speed of operation of the switch.

Abstract: A high speed compare circuit includes a plurality of bit compare block circuits (0 through N) which are coupled in a wired OR configuration to a match line. Each bit compare block (0 through N) includes a compare circuit for receiving a bit and its complement from word A and a corresponding bit and its complement from word B. The compare circuit includes an output line which is normally maintained high to indicate that a match exists. The output line is coupled to a common mode dip filter which is comprised of N and P channel transistors. The output line of the compare circuit is coupled to the gates of a first and a second P channel transistor. The first P channel transistor is coupled to V.sub.cc, and the second P channel transistor is coupled in series to the first P channel transistor. The output line from the compare circuit is also coupled to the gate of an N channel transistor coupled in series with the first and second P channel transistors. The N channel transistor is also coupled to ground.

Abstract: Adverse visual effects on a video display caused by switching operations in a digital-to-analog converter of the video subsystem and by parasitic impedance loading the DAC are minimized. Current cells associated with the DAC generate discrete currents for the video display. Each current cell has a current source for providing a current continuously and first and second switching mechanisms. The first switching mechanism is actuated by a select signal for switching the current to a current sink having a dummy resistance R.sub.d, and the second switching mechanism is actuated by an nselect signal for switching the current to the video display. The select and nselect signals, are generated from input data. A first feedback loop combines the select signal with the data to derive the nselect signal so that the nselect signal is generated after the select signal decreases to a predefined threshold, preferably zero.

Abstract: The low power voltage comparator with hysteresis includes a comparator (10) that is operable to receive the output from a battery (14) on the positive input thereof and the output of a battery (16) on the negative input thereof. An offset circuit (22) is provided in series with the voltage of the battery (14) and the comparator (10), and an offset circuit (24) is provided between the battery (16) and the comparator (10). The offset circuits (22) and (24) are adjustable by a hysteresis control circuit (26) to offset the voltage thereof for the non-selected battery to be higher than that for the selected battery such that the voltage drop across the offset for the non-selected battery is greater than that for the selected battery. When the voltage on the selected battery falls below the offset voltage of the non-selected battery, the hysteresis control then decreases the offset upon selecting the other battery and increases the offset or the battery that is deselected.

Abstract: A comparator circuit having a signal input and at least one signal output having an ON-state and an OFF-state, wherein the ON-state represents an input signal lying above a pre-given switching level V.sub.s and the OFF-state represents an input signal lying below the switching level V.sub.s. The comparator circuit has two comparators, the signal inputs of which are each acted upon by the input signal, wherein both the comparators are wired together in such a way that a switching on of the first comparator produces a signal corresponding to the ON-state of the comparator circuit and the switching off of the second comparator produces a signal corresponding to the OFF-state of the comparator circuit.

Abstract: A first input signal has successive zero amplitude crossings. A first comparator generates a first bilevel output signal responsive to the first input signal. The first comparator has a hysteresis characteristic which is switched on at each said zero crossing of the first input signal and switched off prior to each occurrence of the next following zero crossing. A second input signal has successive zero amplitude crossings and is displaced in phase relative to the first input signal. A second comparator generates a second bilevel output signal responsive to the second input signal. The hysteresis characteristic is switched on by level transitions of the first bilevel output signal and switched off by level transitions of the second bilevel output signal. The first and second input signals may be sinusoidal. The hysteresis characteristic may controlled by first and second flip/flops, which are set by the first bilevel output signal and reset by the second bilevel output signal.

Abstract: A current source is selectively switched into the output circuit of a differential amplifier for producing hysteresis. In a circuit embodying the invention, a differential amplifier (diff-amp) stage operated at a first current level set by a first current source has first and second input terminals for the application therebetween of a differential input signal and first and second output nodes for the production of differential output signals. A second current source for inducing hysteresis is connected to one of the output nodes of the diff-amp and is selectively enabled. A differential input signal (VIN) is applied across the input terminals. When VIN varies in one direction and reaches a first threshold level, the second, hysteresis inducing, current source is enabled whereby a larger current can flow in the one node. VIN then has to vary in the opposite direction and reach a second threshold level to disable the second current source.