Abstract: Two inverting amplifier circuits, which each include an active load transistor and a switch transistor and are different from each other in threshold voltage, and a flip-flop circuit is provided to obtain an output signal having hysteresis characteristics. Further, a low-resistance load transistor for regulating the threshold voltage and a high-resistance load transistor for restricting a through current are provided to cope with low power supply voltage and small amplitude signal input. By virtue of this construction, the invention can provide a Schmitt trigger circuit which is less likely to undergo an influence of a variation in production conditions and a variation in properties of transistors and is free from the flow of a stationary current.

Abstract: A system and method for providing an anticipatory Schmitt trigger circuit that changes the output level of the trigger circuit in anticipation of crossing a predetermined voltage value such as a zero voltage level. In an exemplary embodiment, the anticipatory Schmitt trigger includes a comparator, a feedback resistor, an input resistor, a pull-up resistor, a plurality of voltage divider resistors, and a capacitor.

Abstract: A comparator circuit having a first state and a second state, a threshold potential for transition from the first state to the second state, another threshold potential for transition from the second state to the first state, and hysteresis characteristics that are independent of process, temperature, and supply voltage variations. Preferably, the threshold potentials and hysteresis characteristics depend only on a reference potential and on ratios of resistances of pairs of resistors.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN− voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A circuit for discriminating between complementary first and second input signals. By using a logic gate in parallel with a signal amplifying circuit, the signal amplifying circuit can be disabled when it is no longer required. Once the logic gate is capable of detecting distinct complementary states in the two input signals, the signal amplifying circuit is disabled and the circuit uses one of the input signals as its output signal. The circuit is improved by using a pair of Schmitt inverters so the logic circuit will not vacillate unpredictably when the input signals are in an indeterminate state.

Abstract: A switching circuit, comprising: a first node for receiving a first voltage; a second node 502 for providing an output; a third node for receiving a second voltage; a capacitance 506 coupled between the second node 502 and the third node; means for intermittently charging the capacitance 506 to provide a first output voltage from the second node 502; and a switch 501 connected between the first node and the second node 502 for isolating the second node 502 from the first node when open and for discharging the capacitance 506 to provide a second output voltage when closed.

Abstract: Structures and methods for high speed signaling over single sided/ended current sense amplifiers are provided. The present invention introduces hysteresis within a pseudo-differential current sense amplifier and provides it with adjustable thresholds for the detection of valid signals coupled with the rejection of small noise current transients or reflections and ringing when using low impedance interconnections and/or current signaling. The circuit provides a fast response time in a low power CMOS environment, and conserves circuit design space by allowing for single sided/ended sensing. A first embodiment includes a current sense amplifier having a first amplifier and a second amplifier which are electrically coupled. Each amplifier includes a first transistor of a first conductivity type and a second transistor of a second conductivity type, where the first and second transistors are coupled at a drain region.

Abstract: A differential receiver has a switching point accurately set according to a reference voltage, which switching point is dynamically modified, that is, dc hysteresis is provided, by a circuit internal to the differential receiver. Positioning of the resultant hysteresis characteristic about the reference signal is adjusted by establishing a backgate voltage differential between an input transistor and a reference transistor of the differential receiver. A switching circuit is also provided for controlling switching of a hysteresis circuit at the reference signal plus or minus a desired offset. The switching circuit is gated by an output signal of the input transistor.

Abstract: A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.

Abstract: A system (10) for propagating a digital signal through a slew-rate limited node (18) includes a signal generator (12) which generates slowly-slewing signal (14). A signal conditioner (16) couples to signal generator (12) at node (18) to receive slowly-slewing signal (14), and produces rapidly-slewing signal (20). Signal conditioner (16) converts signal (14) into signal (20) to reduce the propagation delay from signal generator (12) to load (24) by comparing signal (14) with a low voltage threshold, VL, and a high voltage threshold, VH. Signal conditioner (16) employs memory device (92) to determine whether signal (14) is rising or falling upon crossing either threshold VL or VH.

Abstract: A receiver circuit, in accordance with the present invention, includes a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier, and a second stage includes an input coupled to the output of the first stage. The second stage also includes a logic gate coupled to the output of the first stage, the logic gate having an output representing the output of the receiver circuit, and a feed back element coupled from the logic gate output and connecting to a switching element. The switching element, being responsive to the logic gate output, switches a current source on and off to adjust a switchpoint of the receiver circuit.

Abstract: A hysteresis circuit has a comparator which compares a threshold voltage and an input voltage. The threshold voltage is supplied from a voltage dividing circuit having resistors. A constant current circuit is connected to a voltage divided point of the voltage dividing circuit through a switch. The ON and OFF of the switch is controlled by an output of the comparator. When the switch is turned ON, a constant current flows to the voltage divided point, so that the value of the threshold voltage supplied from the voltage dividing circuit to the comparator is changed.

Abstract: A current-controlled differential input comparator having a double sided hysteresis is provided, including a differential input comparator having a first comparator input, a second comparator input, a comparator output, and a switching threshold, wherein the switching threshold causes the comparator output to have a first output state when the first comparator input is greater than the second comparator input and to have a second output state when the first comparator input is less than the second comparator input, a first hysteresis resistor communicating with the first comparator input, a second hysteresis resistor communicating with the second comparator input, an inverter connected to the comparator output, the inverter generating an inverted comparator output, and a current supply connected to the comparator output and to the inverted comparator output, the current supply being capable of switching a first hysteresis current to the first hysteresis resistor and a second hysteresis current to the second h

Abstract: When a short-circuit transistor is switched on, an impedance of an emitter-collector path through a switching transistor in a driver stage becomes higher as a load current becomes greater, and the load current and power loss in the switching transistor thus become lower. This effect is increased by connecting a voltage divider in parallel with the emitter-collector path through the switching transistor, by a parallel transistor. When the switching transistor is switched off, the parallel transistor blocks the current path via the voltage divider and the load for undesirable residual currents.

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a biasing circuit providing first and second biasing signal states. The biasing signal states are adjustably delayed relative to the detected signal.

Abstract: A comparator with hysteresis having a simplified architecture such that the amount of hysteresis can be readily adjusted. In one aspect, a comparator with hysteresis comprises a first switch for coupling an analog input voltage to a signal node in response to a first clock signal; an inverter having an input port and an output port; a capacitor operatively coupled between the signal node and an input port of the inverter; a second switch operatively connected between the input port and the output port of the inverter, the second switch being responsive to the first clock signal; a latch having a clock port, an output signal port, an inverse output signal port, and an input data port, the input data port being coupled to the output port of the inverter; and a reference voltage control circuit for selectively outputting a first internal reference voltage and a second internal reference voltage to the signal node in response to the output signal and inverse output signal, respectively, received from the latch.

Abstract: A high-gain comparator has a built-in hysteresis offset voltage generation feature. The comparator is characterized as having several elements, including a differential amplifier pair that is provided with first and second input voltages, an offset voltage element that creates an offset voltage between the first and second elements of the differential amplifier pair, an output generation element operably coupled to the differential amplifier pair that generates an output voltage of the comparator which is indicative of a voltage difference between the first and second input voltages, and a control element operably coupled to the output signal that controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.

Abstract: An oscillator in an integrated circuit in which the oscillator signal is taken from the output of a comparator, and the decision level of the comparator is determined by the voltage difference between the input of the comparator and the substrate of the integrated circuit. Interference voltages on the substrate, caused by other circuitry on the integrated circuit, are compensated with equal interference voltages at the input of the comparator. To effect this compensation, a capacitor is connected between the input of the comparator and the substrate, in lieu of the conventional capacitor that is connected between the input of the comparator and a ground potential.

Abstract: An hysteresis input buffer includes a first CMOS inverter generating a node signal, a second CMOS inverter coupled to the first CMOS inverter, inverting the node signal from the first CMOS inverter, and producing an intermediate signal, and a hysteresis control circuit coupled to the second CMOS inverter, receiving the intermediate signal, and producing an output signal having a low level during a predetermined delay time and a high level after the predetermined delay time has elapsed.

Abstract: A voltage detector circuit discriminates between a 13 volt Programming signal and a 6 volt signal without creating a field across the gate oxide of a sensing transistor in excess of 7.0 MegaV/cm. A PMOS transistor has a source terminal and a substrate terminal connected, both connected to the input terminal, A gate terminal is connected to a VCC voltage level. A shunt NMOS transistor has a drain terminal connected to the drain terminal of the PMOS transistor and a source terminal connected to a ground terminal. A gate terminal of the shunt NMOS transistor is connected to the VCC voltage level. The NMOS transistor is turned on to provide a shunt resistance between the drain terminal of the PMOS transistor and ground. A drain terminal of a series NMOS transistor is connected to the drain terminal of the PMOS transistor. A gate terminal of the series NMOS transistor is connected to VCC. The source terminal of the series NMOS transistor is connected to a sensing output terminal.

Abstract: A hysteresis comparator circuit which has: a first differential input circuit that operates according to the difference between input voltage and reference voltage; an adder circuit that is composed of first and second addition input ends and differential output voltage of the first differential input circuit is input to the first and second addition input ends as first addition input; a quantizer that quantizes output voltage of the adder circuit and outputs the quantized value as output signal; an attenuator that attenuates output voltage of the quantizer; and a second differential input circuit that applies differential output obtained by differential-amplifying output voltage of the attenuator to the first and second addition ends as second addition input as well as forming a positive-feedback system.

Abstract: A multifunction reset circuit including low power bandgap, a comparator, and an open drain buffer circuit--with the inclusion of four external components (three resistors and one capacitor) to provide undervoltage monitoring, power failure indicating, manual resetting and other reset control conditions to a single integrated circuit terminal, together with hysteresis tolerance.

Abstract: A hysteresis comparator circuit and a waveform generating circuit reduce a power consumption of a DC/DC converter so as to improve a power consumption efficiency when the DC/DC converter is operated with a relatively small load. The hysteresis comparator circuit is connected to a reference voltage source providing a reference voltage. A hysteresis comparator compares an input voltage with one of a first threshold voltage and a second threshold voltage. A hysteresis voltage generating circuit selectively generates one of the first and second threshold voltages by controlling a state of electric charge stored in each of the capacitors. An electric charge stored in the capacitors is provided from the reference voltage source.

Abstract: An apparatus and method for interfacing integrated circuits having incompatible input-output signal offset voltages that is relatively inexpensive and yet is also insensitive to noise.

Abstract: A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator.

Abstract: To prevent an erroneous operation of a buzzer upon fall of a source voltage, a buzzer driving device connectable with a direct current source (1) comprises a charging/discharging circuit (3) which is connected with the direct-current source (1) via a switch (2) and performs the charging and discharging at a predetermined time constant (CR) when the switch (2) is turned on and off, respectively, a hysteresis circuit (25) to which an output voltage of the charging/discharging circuit (3) is input and which operates until the output voltage rises to or above an operation threshold value (V.sub.T) after the start of the charging of the charging/discharging circuit (3) and thereafter remains inoperative unless the output voltage falls to or below a stop threshold value (V.sub.S) which is smaller than the operation threshold value (V.sub.

Abstract: An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN- voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: A ring oscillator using CMOS technology having three logic gates, including a threshold amplifier, where the transistors that set the voltage rise threshold and the voltage drop threshold in the amplifier are controlled by a bias control circuit so that the ratio of voltage rise threshold to the voltage supply diminishes and the ratio of the voltage drop threshold to the voltage supply increases, when the supply voltage falls.

Abstract: An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414).

Abstract: A level adjusting circuit for controlling a voltage supplied to a load such as a semiconductor device, which comprises a voltage level detecting circuit, a reference potential generating circuit for generating a pair of reference potential values to be output into the voltage level detecting circuit, and a monitor pad for drawing out the voltage supplied to the load, wherein the reference potential values are respectively used to compare with the voltage to thereby output a signal for starting supply of the voltage and a signal for ceasing the supply of the voltage under a usually used condition; and the voltage level detecting circuit is to compare either one of the reference potential values with the voltage or the other reference potential value with the voltage at a time under a testing condition, whereby the reference potential generating circuit can accurately be adjusted to change the reference potential values to render the voltage in a range permissible for operation of the load.

Abstract: Method and circuitry for implementing low voltage input buffers using low voltage CMOS transistors are disclosed. Various novel circuit techniques enable the input buffer to safely receive and reliably detect input logic signals in the presence of overshoot or undershoot conditions. In a preferred embodiment, the source terminals of input transistors are biased such that the impact of overshooting or undershooting signals at the input terminal are drastically reduced.

Abstract: A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator.

Abstract: The present invention discloses a Schmitt-trigger circuit with less power consumption by reducing the amount of the required DC current. The Schmitt-trigger circuit disclosed in the present invention basically encompasses a comparison circuit, a first current cutting circuit, and a second current cutting circuit. The comparison circuit receives the input signal and then generates the output signal. Both the first and second current cutting circuits feed in the output signal, and then generate feedback signals to feed the comparison circuit for cutting the DC current path when the input signal rises or falls to predetermined trigger points. When there is only one of the first and second current cutting circuits is required, the higher or lower trigger point can be adjusted without necessary to vary the size-ratio of the PMOS and NMOS transistors.

Abstract: A Schmitt trigger circuit has an input device and an amplifier. The input device has a current adder device having a P-type current mirror circuit and a N-type current mirror circuit connected in parallel. The P-type current mirror circuit has a positive constant current source for converting an external input signal to a positive constant current and a first output current control transistor for controlling an output current from the positive constant current source. The N-type current mirror circuit has a negative constant current source for converting the external input signal to a negative constant current and a second output current control transistor for controlling an output current from the negative constant current source. The amplifier amplifies the output signal from the input device and generates the feed-back control signal to be used for controlling and driving the first output current control transistor and the second output current control transistor.

Abstract: A subscriber line interface circuit which includes a transient signal detector with temporal hysteresis. During steady state operation, the drive current for the subscriber loop allows the loop to respond to changes in loop conditions according to a steady state time constant of the loop filter. Upon detection of a line voltage transient which exceeds a predetermined threshold in either a positive or negative direction, the filter time constant is significantly reduced (e.g., 100:1) and held at such reduced value following the initial transient and for a predetermined time period after the line voltage has fallen back below such predetermined threshold. This allows the transient conditions to be fully compensated prior to resetting the filter time constant back from the lower transient value to the higher steady state value.

Abstract: An improved pulse detection circuit provides for a reduced delay response and noise immunity. The pulse detection circuit includes a comparator with a hysteresis circuit providing a hysteresis response on the order of a minimum pulse width and a reference circuit having a time constant which is a function of unexpected signal input level.

Abstract: A logic circuit for providing hysteresis in the sensing of the temperature of an integrated circuit includes two voltage comparators and a D-type flip-flop. Each of the comparators compares a reference voltage and a respective one of two voltage signals which represent and vary in respective relations to the temperature of the integrated circuit. The resulting binary output signals of the comparators are asserted and de-asserted at different approximate temperatures, i.e., with one being higher and the other being lower with respect to one another. One comparator output signal serves as both the input data signal and output clear control signal for the flip-flop while the other serves as the clock signal. Accordingly, the output signal of the flip-flop is asserted during a time which follows an increase in the measured temperature above the higher approximate temperature value and precedes a decrease in the measured temperature below the lower approximate temperature value.

Abstract: A comparator circuit (100) produces a binary output voltage at an output (109) in response to a time varying input signal received at an input (108). The comparator circuit includes an output circuit (106) having a first current mirror (202), a second current mirror (204), a bias circuit (206) and a helping current source (208). Bias currents are applied in response to the state of the output voltage at the output to increase the gain and the hysteresis of the output circuit.

Abstract: An integrated circuit in which Schmitt input circuits can be tested in a short time and a highly accurate test result can be obtained. The integrated circuit includes switches each passing outputs of Schmitt inverters with inputs connected to input-output ports to the inputs of tristate circuits with outputs connected to adjacent input-output ports. The outputs of the Schmitt inverters may be blocked by the switches from being passed to internal logical circuits. A switch passes the output of the Schmitt inverter to the adjacent tristate circuit during the test of the Schmitt inverter. Alternately, each half of the Schmitt inverters can be tested as predetermined control signals selectively control each switch and each tristate circuit.

Abstract: A differential comparator having a low-offset comparator and two processing paths, each of which receives one of the two primary inputs to the differential comparator and generates one of the two inputs to the low-offset comparator. The output of the low-offset comparator is the output of the differential comparator. Each processing path is capable of (1) generating an offset voltage and (2) turning on and off the generation of that offset voltage. In a preferred embodiment, each processing path has a passive resistor that generates the offset voltage and a pair of shunt transistors that selectively shorts out the passive resistor. The output of the low-offset comparator is connected (either directly or indirectly through an inverter) to the gates of the shunt transistors. The shunt transistors are therefore controlled by the output of the low-offset comparator. In each of two modes of operation, a different one of the passive resistors is "on" while the other passive resistor is "off.

Abstract: A Schmitt trigger (30) operates at low power and low frequency and can be implemented in a small amount of surface area on an integrated circuit. Specifically, the Schmitt trigger (30) includes transistors (34, 40) that are implemented as long channel devices and operate in a linear region for providing resistive elements, and another pair of transistors (44, 46) that function as non-linear devices allowing a current through the Schmitt trigger (30) to provide both a reference and the switchpoints for the Schmitt trigger (30). These transistors also establish low current through the Schmitt trigger (30).

Abstract: A comparator with a built-in offset is disclosed. The claimed comparator includes a bias current circuit, a differential input stage with the built-in of-set, and a hysteresis circuit. The built-in offset is generated by using a resistor in the differential input stage of the comparator such that the resistor is driven by the bias current as well as the current generated by the hysteresis circuit. Additionally, a reset circuit which uses the comparator with the built-in offset is claimed. The reset circuit uses a voltage divider circuit to divide a first input voltage to the comparator. A band-gap voltage reference is used to provide a second input voltage to the comparator. Therefore, the reset circuit generates a reset signal when the divided voltage reaches the value of the band-gap voltage plus the offset. In another embodiment, a comparator having a differential input stage, an output stage, and a bias circuit with a hysteresis circuit is disclosed.

Abstract: To evaluate the output signal of an active sensor which is configured as a binary current signal, a circuit arrangement is disclosed by which a proportional current is produced from the sensor current by way of a current mirror circuit. The current produced by a current mirroring operation is drawn from a stabilized voltage source by way of an ohmic resistance, and a binary voltage signal corresponding to the sensor output signal is generated thereby. The voltage signal is sent to a flipflop which compares the voltage signal with a reference value that is composed of a reference voltage and a hysteresis voltage. The change-over threshold of the flipflop is varied or adapted as a function of the actual sensor current, leakage currents, etc.

Abstract: An internal voltage generating circuit for generating an internal voltage VINT from an input external voltage VEXT is provided to stabilize the internal voltage. When the external voltage VEXT is less than or equal to a first boundary voltage VT1 or a second boundary voltage VT2 (>VT1), a constant voltage VINTN independent on the external voltage VEXT, which is produced by a constant voltage generator is outputted therefrom. When the external voltage VEXT is greater than or equal to the first boundary voltage VT1 or the second boundary voltage VT2, a variable voltage (>VINTN) linearly increased with an increase in VEXT, which is produced by a variable voltage generator, is outputted therefrom. When a detecting means detects that the external voltage VEXT has been increased to VT2 or higher, the characteristic of the internal voltage is switched from a constant voltage characteristic to a variable voltage characteristic.

Abstract: Control circuit for producing output voltages from a plurality of sensor signals, wherein each of the sensor signals are identical and mutually phase shifted. The control circuit comprises a plurality of comparators for producing the output voltages, wherein each comparator is respectively supplied with one of the sensor signals and with an amount of hysteresis which depends on the amplitude of one or more of the respective other sensor signals. The control circuit further comprises electronic circuitry for deriving the respective amount of comparator hysteresis for each of the comparators from the amplitude of one or more of the respective other sensor signals.

Abstract: An apparatus and method for controlling a variable threshold signal conditioning circuit to condition a variable amplitude periodic input signal in response to the control signals received. A plurality of transistor circuits, each responsive to a control signal, are disposed in parallel with the positive feedback resistor of a trigger circuit. The transistor circuits are controlled to adjust the upper threshold levels of the trigger circuit in order to reduce the false triggering effects of noise in the input signal. The lower threshold level is held constant at the input signal mid-line voltage while the upper threshold level is varied over a plurality of preprogrammed values. A microprocessor determines the appropriate threshold level for the circuit by comparing the timing signal output of the signal conditioning circuit to preprogrammed values stored in the microprocessor memory.

Abstract: A balanced current amplifier mirrors either a fully differential or single ended input signal into common output circuits in a manner to generate a fully differential output signal without any d.c. bias. Input signal nodes are maintained at a desired voltage by circuit elements other than those of the current mirror circuits, thus freeing the current mirroring elements from having to be sized for this purpose. The sizes of the output transistors are adjustable in order to set the gain of the circuit. In addition to amplifier circuits, a full-wave rectifier, a comparator, and a filter, all operating with current signals, are described. A single circuit module may include all of these circuits with a user provided the capability to program the module to perform any one or more of these functions.

Abstract: In a latching circuit including a first inverter having first input and output sides, a second inverter having second input and output sides, the first input side is connected to an input terminal, the second input side is connected to the first output side, the second output side is connected to the input terminal, and the second inverter further has first and second transistors having a primary conduction-type and are serially connected between first power supply terminal and the input terminal and including first and second gates having first and second gate lengths, respectively, third and fourth transistors having a secondary conduction-type reverse to the primary conduction-type and are serially connected between a second power supply terminal and the input terminal and including third and fourth gates having third and fourth gate lengths, respectively. The first gate length is greater than the second gate length while the third gate length is greater than the fourth gate length.

Abstract: A pulse detecting system 1 has a high speed A/D converter 10 and a slew controlled pulse detector 110. The A/D converter 10 has large hysteresis for holding the converted digital value of an input signal V.sub.PULSE until the A/D converter 10 is reset. The slew controlled pulse detector 110 limits the slew rate of large amplitude pulse to correct arrival errors and provide an output signal V.sub.AT that more accurately represents the arrival time of the input pulse signal, V.sub.PULSE.