Abstract: In a first phase a first sensor signal, essentially comprising the current offset signal of the sensor, is applied to the input of an electronic circuit. The first sensor signal is fed to a first signal path and stored therein. In a second phase a second sensor signal, comprising the current offset signal and a time-dependent measured signal, is applied to the input and the stored first sensor signal is fed to the input by means of the first signal path, such that essentially the time dependent measured signal is fed by means of a second signal path coupled to the input.

Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hysteresis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.

Abstract: A hysteresis comparing device with constant hysteresis width and the method thereof, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: An interface circuit (100) and method for interfacing received digital signals, relative to a first ground potential, for transmission on the bus, relative to a second ground potential. A transformer (106) passes edges of the received digital signals. A Schmitt trigger (110) reconstructs signals from the edges of signals passed by the transformer, so as to produce digital signals, for transmission on the bus, relative to the second ground potential. The Schmitt trigger bias points may be set by an oscillators incorporating another Schmitt triggers (120) located on the same semiconductor die to reduce temperature variability.

Abstract: A comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second transistor (M2) whose gates form the inputs of the comparator. The main current paths of both transistors are connected to each other at one end, with a third transistor (M3) and a fourth transistor (M4) being provided. The gate of the third transistor is connected to the gate of the first transistor and its main current path is circuited between the one end of the main current paths of the first and second transistor and is connected via the main current path of the fourth transistor to the other end of the main current path of the second transistor. The gate of the fourth transistor is connected to the output signal or inverted output signal of the comparator. The comparator in accordance with the invention may be put to use e.g. in an ASK demodulator such as those used in RFID transponders.

Abstract: A Schmitt trigger circuit has an adjustable hysteresis characteristic by providing a plurality of feedback circuits that differently affect at least one, and preferably both, of the circuit's upper trip point level and lower trip point level. The upper trip point level can be adjusted by selecting a desired feedback circuit from a first set of feedback circuits, and/or the lower trip point level can be adjusted by selecting a desired feedback circuit from a second set of feedback circuits. Feedback circuit selection is achieved by one or more control signals that may be programmable. The hysteresis characteristic can be adjusted to meet desired noise margin, delay, and input recognition criteria at different VCC levels. The Schmitt trigger circuit may be a CMOS Schmitt trigger with two input stage NMOS, two input stage PMOS transistors, a first set of NMOS feedback circuits, and a second set of PMOS feedback circuits.

Abstract: The present invention discloses a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, comprising a first time hysteresis unit, a second time hysteresis unit and an inverter. The first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level. The second time hysteresis unit has the characteristic of time hysteresis connected to the first hysteresis in series when the input signal transits from the second level to the first level.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: A comparator with two thresholds includes a two-threshold latch in which one input and one output respectively form an input and an output of the comparator. The latch has a first node between a first power supply terminal and the output of the latch. The comparator also includes a first negative feedback loop acting on the first node for setting the first threshold of the comparator as a function of a first power supply potential. The first threshold is also a function of a first reference potential that is stable.

Abstract: An input receiver with hysteresis including a differential sense amplifier, a reference circuit having a reference node providing a reference signal at a nominal threshold voltage level, and a switching stack device. The amplifier has a first input which receives an input signal, a second input coupled to the reference node, and an output which provides an output signal having first and second states indicative of the input signal. The switching stack device operates to adjust the reference signal based on the output signal between upper and lower threshold levels in an opposite direction of the input signal. The reference circuit may be a voltage divider that divides a power voltage signal to develop the reference signal. The switching stack device may include a P-channel device and an N-channel device coupled to the voltage divider to adjust the threshold voltage level of the reference signal.

Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hysteresis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode.

Abstract: A method and apparatus for signal processing may include an electronic circuit comprising a receiver configured to receive a signal and a dynamic threshold circuit configured to process the signal. The dynamic threshold circuit is configured to compare the signal to a threshold and generate an output signal according to the comparison. The dynamic threshold circuit is also configured to change the threshold to a selected level at a selected time. In various embodiments, the selected level is selected to be a level between the level of the input signal and a midpoint of the input signal. In another embodiment, the selected time is selected to correspond to a stabilization time of the input signal.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: The invention relates to a signal receiver inserted between a first and a second voltage reference and having a first and a second input terminal effective to receive differential signals and an output terminal effective to provide a converted signal. Advantageously, the signal receiver according to the invention comprises a conversion stage inserted between the first and second voltage references and connected between the first and second input terminals of the signal receiver and an input terminal of an hysteresis comparator, connected in turn to the output terminal of the signal receiver. In particular, the conversion stage performs a conversion from any input signal received on respective input terminals to an intermediate signal provided on an output terminal and suitable for reception by the hysteresis comparator.

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract: A novel and useful apparatus for and method of automatic gain control (AGC) using Kalman filtering and hysteresis. A nonlinear, time-variant loop filter such as a Kalman filter is employed in the feedback loop of an AGC circuit. The circuit is able to transition quickly and make fast adaptations to new levels of the input signal by use of a restart mechanism used to dynamically modify the gain of the loop filter thus enabling the AGC circuit to quickly adapt to changes in the signal level of the input. An AGC circuit incorporating a hysteresis circuit in the feedback loop is also disclosed.

Abstract: A wake-up circuit for a ECU on a CAN bus utilizes two complementary switching transistors which will turn ON when there is a differential voltage between CANH and CANL which will turn ON the transistors to pass a current which will be mirrored over to create a voltage which will switch a comparator or a Schmitt trigger. The two signals are then ORed together to generate a digital wake-up signal that can be utilized by other on-chip circuitry.

Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hystersis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.

Abstract: A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: A magnetic field sensor includes: a Hall element; a voltage amplifier for amplifying an output voltage from the Hall element so as to output an amplified signal; a voltage comparison circuit for receiving the amplified signal; a switch circuit provided between the voltage amplifier and the voltage comparison circuit for inverting a polarity of the amplified signal; and a latch circuit for holding an output signal from the voltage comparison circuit. The voltage comparison circuit inverts a polarity of a hysteresis voltage that determines a reference value of a magnetic field intensity in response to a first synchronizing signal, which triggers a detection of a magnetic field, and a second synchronizing signal following the first synchronizing signal.

Abstract: A circuit is disclosed for monitoring a reference voltage generated in a semiconductor memory device to facilitate a memory access operation. The circuit utilizes a pair of Schmitt trigger circuits. A first of the Schmitt trigger circuits detects the voltage appearing on the output of a reference voltage generator falling below a minimum threshold voltage level. A second of the Schmitt trigger circuits detects the output voltage of the reference voltage generator exceeding a maximum threshold voltage level. The circuit may further include reset circuitry for initially placing predetermined voltage levels on the inputs of the Schmitt trigger circuits. An output circuit receives the output of each Schmitt trigger circuit and generates an output signal having a value indicative of whether the output of the reference voltage generator is not within an acceptable voltage range.

Abstract: A two-terminal switch circuit (1) for periodically energizing a load (20) from a voltage supply includes a controllable switch (4) connected between the switch terminals (2,3), a resistance (8) and a capacitor (9) connected in series between the terminals (2,3), and a voltage threshold responsive arrangement (26) having a hysterisis characteristic. The voltage threshold responsive arrangement has a signal input (27) and a power supply input (29) connected to the common point (12) of the resistance and the capacitor, and a signal output (28) connected to a control input (13) of the controllable switch. The voltage threshold responsive arrangement is powered by the capacitor voltage. The threshold responsive arrangement closes the switch when the capacitor charges to a first threshold voltage and opens the switch when the capacitor thereafter discharges to a second threshold voltage which is lower than the first threshold voltage.

Abstract: A current controlled oscillator is described comprising: a latch comprising two logic inverters to maintain a switch state for a determined duration, the latch having two complementary output voltages; a differential switch pair comprising a first and a second switch controlled by the two complementary output voltages respectively to steer a control current to a first and a second node alternatively; a third and fourth switch driven on by a high level voltage at one of the first and second node to set and reset the latch; and a fifth and sixth switch controlled by the two complementary output voltages respectively to pull down voltages at the first and second node alternatively, wherein the first and fifth switch are controlled by a same control signal and the second and sixth switch are controlled by a same control signal; whereby the frequency of switching is a function of the capacitance of the first and second node and the control current.

Abstract: A multiple voltage environment input pad with a circuit input comprises a level shifter circuit (A) and a buffer circuit (B). The buffer circuit B comprises an inverter comprising at least two transistors (6, 7) of opposite types, followed by twin controllable voltage dividers (8, 10; 4, 5, 9) of opposite types. Each controllable voltage divider (8, 10; 4, 5, 9) has at least two controllable voltage divider inputs and a controllable voltage divider output. For each of the controllable voltage dividers (8, 10; 4, 5, 9) one of the inputs is connected to an output (16) of the level shifter circuit (A) and another one of the inputs is connected to an output (14) of the inverter. For each of the controllable voltage dividers (8, 10; 4, 5, 9) the voltage divider output is connected to a current input connection of a transistor (6, 7) of corresponding type of the inverter. The level shifter circuit (A) comprises a series pass transistor (2) and in parallel thereto a transistorized capacitor (15).

Abstract: In an interface between a high-active driving circuit for driving a predetermined semiconductor power element and a microcomputer for controlling an output signal of the driving circuit, the microcomputer comprises a transistor, a collector terminal of which is an output side of the microcomputer; and the driving circuit comprises a first resistor, one end of which is directly connected with the output side of the microcomputer; a Schmidt circuit which is connected in series with the other end of the first resistor; a diode, an anode side of which is connected to a path between the first resistor and the Schmidt circuit; a power supply voltage connected with a cathode side of the diode; and a second resistor, one end of which is grounded and the other end of which is connected with a side of the first resistor being an input terminal of the driving circuit.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: A high precision receiver with a means to reduce or compensate the skew caused by the receiver's hysteresis by using a dynamic reference that is varied depending on a current output signal. To avoid oscillation, the reference signal can be switched over with a certain delay.

Abstract: A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.

Abstract: A pattern recognition system to qualify valid triggering for digital storage oscilloscopes. Valid trigger qualification may be established from recognition of triggering level and interval time information, as well as other pattern-related information, to start or stop waveform acquisition. Trigger qualification may be established from either a pattern match or a mismatch. The trigger recognition system may be further extended to the occurrence of complex signals, such as those associated with television, rotating machinery, or other phenomena occuring in predetermined or known patterns.

Abstract: A Schmitt trigger circuit includes: an NAND gate receiving a control signal and an input signal; an inverter outputting an inverted signal of an output signal of the NAND gate; first and second P channel MOS transistors and first and second N channel MOS transistors switching a threshold potential of the Schmitt trigger circuit in response to an output signal of the inverter; and a third N channel MOS transistor receiving the control signal at a gate thereof. When the control signal attains L level, the third N channel MOS transistor is rendered non-conductive. Therefore, a through current does not flow through the first-third N channel MOS transistors. Thus, Schmitt width can be freely designed and power consumption will be small.

Abstract: A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: A CMOS latch with improved immunity to soft errors resulting from energetic particle strikes is disclosed. In one embodiment two Schmitt triggers are cross-coupled to hold a logic state. The significant hysteresis of the Schmitt triggers improves the resistance of the latch to induced soft errors. In a further embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of both the pullup and pulldown networks of the Schmitt trigger thereby creating significant hysteresis. In another embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of only one of either the pullup or pulldown network of the Schmitt trigger thereby creating significant hysteresis.

Abstract: A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.

Abstract: A threshold amplifier receives a logic supply voltage and a ground voltage and includes a Schmitt trigger comprising an inverter stage and a hysteresis stage connected to the inverter stage for setting a high and a low hysteresis threshold. A disabling circuit disables the hysteresis stage as a function of a level of the logic supply voltage. The threshold amplifier further includes a detection circuit for detecting the level of the logic supply voltage with respect to a detection threshold, and for activating the disabling circuit for disabling the hysteresis stage when the level of the logic supply voltage is below the detection threshold.

Abstract: A system having a first device and a second device coupled to a single wire bus is described. The second device is operable to receive power from the single wire bus that is due to the first device driving the bus. The second device also communicates with the first device using the single wire bus.

Abstract: A reference voltage is moved dynamically towards a voltage level of the last received value. The movement takes place over a predetermined fraction of a bit-time. The amount of movement is limited so that successive logical values don't result in an unusable reference voltage level. When the output of a receiver changes, a state machine sequences the selection of analog reference voltage inputs to a multiplexer to move an output reference voltage towards a steady-state signal voltage level for the value that was just received. When the sequence is complete, the state machine keeps the last value selected on the output until the output of the receiver changes value.

Abstract: A method is described that involves directing a signal through a hysteresis comparator. Then, determining if an output signal of the hysteresis comparator, in response to the signal, is an AC signal or a DC signal. Then, deactivating a signal reception unit that receives the signal if the hysteresis comparator output signal corresponds to a DC signal; or, activating the signal reception unit if the hysteresis comparator output signal corresponds to an AC signal.

Abstract: An apparatus for generating an amplified effect in an asymmetrical hysteretic system is disclosed. The asymmetrical hysteretic system comprises a transponent, a bias that externally grades the transponent, an energy source that drives the transponent, and a small stimulus amplified by a gain factor of the transponent. A method for generating an amplified effect in an asymmetrical hysteretic system is also disclosed.

Abstract: A loss of signal condition is evaluated for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. Two hysteresis modes are used to ensure the hysteresis at low LOS threshold levels is sufficient. The first mode uses hysteresis for the signal strength threshold level that is proportional to the LOS threshold level when the LOS threshold level is above a predetermined level. The second mode employs fixed hysteresis for the signal strength threshold level when the LOS threshold level is below the predetermined level. The hysteresis provides a signal strength threshold level that has a greater magnitude on deassertion of a loss of signal indication than on assertion of the loss of signal indication.

Abstract: A hysteresis comparing device with constant hysteresis width, which can respectively receive a first signal and a second signal and can output a digital signal. The hysteresis comparing device includes a threshold voltage generator, a multiplexer, and a next stage comparator. The threshold voltage generator is used to receive the first signal and output an upper threshold voltage and a lower threshold voltage. The multiplexer is used to receive the upper threshold voltage and the lower threshold voltage, and output a multiplexing signal according to the digital signal. The multiplexing signal is either the upper threshold voltage or the lower threshold voltage. The next stage comparator has one terminal used to receive the multiplexing signal, and another terminal used to receive the second signal. The next stage comparator outputs the digital signal. The hysteresis comparing device with constant hysteresis width can suppress the effect from the glitch.

Abstract: A tri-state Schmitt trigger inverting device having multiple tri-state controller switching devices between a conventional voltage mode Schmitt trigger its voltage supply rails. When an enabling signal to the tri-state controller switching devices is set to a first level, the tri-state Schmitt trigger functions as a standard logic inverter. When a complementary enabling signal is received at the tri-state controller switching devices, the connections to the high voltage rail and low voltage rail of the tri-state Schmitt trigger are turned off, and the output of the tri-state Schmitt trigger is a high impedance. Thus, the device is a single stage tri-state Schmitt inverter having optimal hysteresis characteristics with minimal power consumption.

Abstract: A CMOS Schmitt Trigger circuit design provides a relatively high speed device having a tight, substantially monotonic hysteresis characteristic which is substantially independent of fabrication process parameters and can be used with relatively wide power supply designs, including operating a relatively low Vcc. Tight trip point variation is maintained in conjunction with process, voltage, and temperature changes. The circuit is adaptable for forming an integrated circuit buffer element.

Abstract: A current pulse receiving circuit suitable for converting a current pulse converted by a photodetector from a light pulse received in optical communications and outputting a logic level voltage pulse with an accurate pulse width is disclosed. When an output signal from a current-to-voltage converter circuit is detected to have a large amplitude by a large signal detection circuit, an amount of offset cancellation of a DC cancellation circuit is decreased to limit the amplitude of the output signal from the current-to-voltage converter circuit. Since the amplitude of an input signal of an amplifier circuit is limited, tail characteristics at a trailing edge of a pulse are small and an output is provided at an output terminal with an accurate pulse width.

Abstract: The present invention provides a circuit which is configured to apply variable hysteresis to an input signal, where the level of hysteresis applied to the input signal is dependent upon the frequency of the input signal. Use of this circuit in a vehicle's anti-lock braking system allows for more efficient and effective braking.

Abstract: By turning OFF a PMOS transistor 15a of a feedback inverter 15 as the signal level at an input node 6 gradually changes from the “L” to “H” level, a high-level output from the feedback inverter 15 to an intermediate node 7 is limited, or by tuning OFF an NMOS transistor 15b of the feedback inverter 15 as the signal level at the input node gradually changes from the “H” to “L” level, a low-level output from the feedback inverter 15 to the intermediate node 7 is limited. Hence, the hysteresis width can be narrowed by limiting the output to the intermediate node 7 from the feedback inverter 15 which functions to expand the hysteresis width.

Abstract: A two-terminal switch circuit (1) for inclusion in series with a load (20) across a voltage supply (63) for periodically energizing the load (20) from the supply (63) comprises a controllable switch (4) connected between the terminals (2,3), a resistance (8) and a capacitor (9) connected in series between the terminals (2,3), and a voltage threshold responsive arrangement (26) the output signal/input signal characteristic of which exhibits hysteresis. The voltage threshold responsive arrangement (26) has a signal input (27) connected to the common point (12) of the resistance (8) and the capacitor (9), and a signal output (28) connected to a control input (13) of the controllable switch (4). A power supply input (29) of the voltage threshold responsive arrangement (26) is also connected to the common point (12) of the resistance (8) and the capacitor (9) so that the voltage threshold responsive arrangement (26) is powered from across the capacitor (9).

Abstract: A voltage comparator with hysteresis that includes a differential amplifier, voltage divider circuits and a current mirror circuit. The input terminals of the two differential amplifier circuit branches are biased at unequal potentials by the voltage divider circuits. One voltage divider output voltage is fixed and the other is variable. The input terminal of the differential amplifier circuit branch biased at the fixed potential receives an AC-coupled input signal voltage. The sum of the input signal voltage and the fixed bias voltage is compared against the variable bias voltage. A current mirror circuit, which is activated during conduction by the differential amplifier circuit branch biased at the variable potential, shunts a portion of the current used by the voltage divider circuit that generates the variable potential. This causes the variable voltage divider output voltage to change, thereby introducing hysteresis into the voltage comparison performed by the differential amplifier.

Abstract: An integrated circuit and method utilizes a differential input receiver having a first input that receives an input signal. A reference voltage adjustment circuit produces a variable reference signal for the second input of a differential input receiver. A feedback path is provided from the output of the differential input receiver to an input of the reference voltage adjustment circuit. The reference voltage adjustment circuit dynamically varies the variable reference voltage signal to facilitate hysteresis. The variable reference voltage signal is lowered in the case of a high input signal, and raised in the case of a low input signal.

Abstract: A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.