Abstract: A delay line provides a variable delay in the clock path and increases the operating frequency range through the use of delay stages which have non-uniform propagation delay with respect to one another. The range of operating frequency is increased by keeping the delay stages with the minimum propagation delay in the center of the delay line while the delay stages with the maximum propagation delay are toward the ends of the delay line.

Abstract: Delay circuitry includes a phase-locked loop or PLL for comparing the phase of a reference clock applied thereto with that of another clock to be compared to generate a control signal having a value corresponding to the phase difference between the phases of the reference clock and other clock, for generating the other clock using at least a plurality of delay elements connected into a loop, a time delay provided by each of the plurality of delay elements being controlled by the control signal, and for changing the value of the control signal so that the other clock is made to be in phase with the reference clock.

Abstract: The invention is to provide a programmable delay element that can produce a variable delay with many different delay combinations. The invention creates a variable delay through logic gates. A plurality of transmission gates are used to transfer a signal through a plurality of fixed delay lines. Four parallel coupled signal paths, each path having a fixed delay, form the basis of the invention. By selecting a path or by serially adding successive paths, the desired delay of the signal present on the delay line can be achieved.

Abstract: A variable delay circuit comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements, according to a number of the first variable delay elements; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.

Abstract: A circuit for measuring a propagation time of an edge of a signal between an input and an output of a logic cell. The circuit includes a plurality of logic cells of a first type that are electrically coupled in a series, and a plurality of multiplexers, each having a selection input, first and second data inputs, and an output. Each of the plurality of logic cells has a first input and an output, the output of each logic cell in the series being respectively electrically coupled to the first input of a next logic cell in the series. The output of a last logic cell in the series is electrically coupled to the first input of a first logic cell in the series to form a ring. The selection input of each multiplexer of the plurality of multiplexers is electrically coupled to the output of one logic cell in the series, with the output of each multiplexer being electrically coupled to the first input of the next logic cell in the series.

Abstract: A delay locked loop circuit, in accordance with the invention, includes a delay line for providing a delay through the delay line in accordance with a control signal, the delay line being connected across an input node and an output node. A delay element is connected to the input node, the delay element for providing a predetermined delay value to an input signal from the input node to provide a delayed input signal. A phase comparator is connected to the output node and the delay element for comparing phase differences between an output signal and the delayed input signal and for outputting the control signal to the delay line such that the delay line provides the predetermined delay value to the delay line across the input and output nodes.

Abstract: A pipelined programmable digital pulse delay system (10) that is capable of processing multiple input pulses simultaneously, each with a unique programmed delay value, includes a plurality of pulse delay units (12, 14, 16), a plurality of buffer registers (18, 20, 22, 24), and a commutator unit 26. The buffer registers (18, 20, 22, 24) each store a delay control word corresponding to a single pulse currently being processed in the system (10). The plurality of pulse delay units (12, 14, 16) each reference a corresponding buffer register (18, 20, 22, 24) for an appropriate delay control value when a particular pulse is about to be received by the pulse delay unit. After the pulse has passed an operative point in the pulse delay unit, the unit then retrieves a delay control value from another buffer register (18, 20, 22, 24) for use with a next input pulse. Thus, pipelined operation is achieved in the system (10).

Abstract: In a semiconductor device capable of obtaining an optimum delay time, a plurality of delay circuits are connected in series to one another through points of connections between two adjacent ones of the delay circuits to produce a plurality of reference delay signals derived from the delay circuits. One of the reference delay signals is decided as the optimum delay time with reference to a practical condition. Thus, the delay time can be varied in the semiconductor device.

Abstract: A variable loading circuit for controlling signal transmission on a signal line in an integrated circuit includes a capacitor. A loading control circuit is responsive to a control signal to variably couple the signal line and a signal node through the capacitor and thereby vary signal transmission time on the signal line. In embodiments of the present invention, the loading control circuit includes a series combination of a fuse and one or more switches. The one or more switches are responsive to respective control signals to variably couple the signal line to the signal node through the fuse and the capacitor. The variable loading circuits can be used to reduce skew among signals in systems where signal timing is critical. Related methods are also described.

Abstract: An embodiment of an edge placement device is supplied with transition data to generate transitions during a pixel time period corresponding to the transition data. The transition data is supplied by pulse code logic that converts pixel data to the transition data. The embodiment of an edge placement device includes first edge placement logic coupled to taps from a first clock delay chain and second edge placement logic coupled to taps of a second clock phase delay chain. Also included is a phase splitter that generate a first and a second clock phase coupled, respectively, to the first and the second clock delay chain from a clock corresponding to a pixel time period. The first and the second clock phase have rising edges on alternate cycles of the clock. The first and the second edge placement logic each include a plurality of D flip flops.

Abstract: Phase locked loop integrated circuits include a phase detection circuit, a variable delay device and a delay control circuit. The variable delay device and delay control circuit provide improved characteristics by increasing the signal frequency bandwidth of the delay locked loop integrated circuit in a preferred manner. The phase detection circuit is configured to perform the functions of comparing first and second periodic signals and generating a phase control signal (e.g., VCON1) having a first property (e.g., magnitude) that is proportional to a difference in phase between the first and second periodic signals. The delay control circuit is responsive to the phase control signal VCON1 and generates a delay control signal that is provided to the variable delay device. The delay control circuit may comprise a counter, a first comparator, a second comparator and a shift register. The variable delay device includes a variable delay line and a compensation delay device.

Abstract: The present invention provides a time delay system that generates a selectable asynchronous time delayed signal from an incoming signal using a pulse having a minimum pulse width and stop-startable oscillator. The time delay system of the present invention produces a minimum data dependency error which is independent of the repetition rate of the incoming signal, the substrate settling time, and the length of the time delay of the delayed signal.

Abstract: A delay line, in accordance with the invention, includes a plurality of delay elements connecting an input and an output, the delay elements for causing a delay to be introduced to a signal passing through the delay elements. A voltage device is included for regulating power to the plurality of delay elements, the voltage device being adjustable to provide at least one predetermined voltage to the delay elements such that the delay in the delay elements is modified according to the predetermined voltage(s). The delay line may be employed in a delay locked loop, a clock circuit or other circuits.

Abstract: A precision trim circuit for a tuneable delay line is provided. The precision trim circuit provides delays greater than the base delay of the tuneable delay line. By using larger delays than conventional trim circuits, the precision trim circuit of the present invention can use components that react to process and environmental variations in the same manner as the components of the tuneable delay line. Specifically, one embodiment of the precision trim circuit comprises a first delay element providing a delay greater than or equal to the base delay of the tuneable delay line. The precision trim circuit also comprises a second delay element providing a greater delay than the first delay element. A multiplexer coupled to the first delay element and the second delay element is used to select the amount of delay provided by the precision trim circuit. Other embodiments include additional delay elements providing varying delay values.

Abstract: A delay locked loop includes a delay circuit capable of generating an output clock and further capable of generating a GATE signal in response to an aliased condition. A phase detector is coupled to the delay circuit and is capable of comparing a phase difference between a reference clock and the output clock from the delay circuit and generating a pump up signal if the output clock is lagging the reference clock. The phase detector is capable of generating a pump down signal if the output clock is leading the reference clock. A charge pump is coupled to the phase detector and is capable of generating a control voltage for controlling the delay provided to the output clock and capable of pulling up the control voltage in response to the GATE signal.

Abstract: A variable width pulse generator. The pulse generator includes a pulse circuit responsive to a reset signal to provide a pulse circuit signal. A variable delay reset loop path, coupled to the pulse circuit, is responsive to the pulse circuit signal to provide the reset signal. A control signal may vary the width of a pulse generated by the circuit by varying the length of a delay associated with the reset loop path. Both a coarse control signal, such as a signal that selectively removes a logic element in the reset loop path, and a fine control signal, such as a signal that controls a tunable delay element in the reset loop path, may be used to adjust the pulse width.

Abstract: A pulse width modulation circuit utilizes a clock divider to generate a plurality of clocks to be used by a plurality of delay blocks. Each delay block has plurality of delay elements each of which receives one the plurality of clocks. Each delay block receives a delay data, selects a number of the plurality of clocks based on the delay data and activates the respective delay elements for delaying its input signal.

Abstract: A synchronous delay circuit system comprises an input buffer having a first delay time and receiving an external clock, a clock driver having a second delay time and for an internal clock, a dummy delay circuit having a delay time equal to a sum of the first delay time and the second delay time, a first delay circuit array formed of a predetermined number of delay circuits having a predetermined delay time, for measuring a time difference of a constant period from an output of the dummy delay circuit, a second delay circuit array formed of a predetermined number of delay circuits having a predetermined delay time, for reproducing the measured time difference to output the reproduced time difference to the clock driver, a circuit for measuring the frequency of the external clock to output a frequency measurement signal, and a delay time control circuit responding to the frequency measurement signal to control the traveling speed of a pulse or a signal edge in the first delay circuit array and in the second del

Abstract: A variable delay circuit comprises: a variable delay part having n (≧2) cascade-connected delay parts, each of which has a delay element, a selecting circuit for selecting whether an input signal is allowed to pass through the delay element, and an OR gate for outputting an output of the selected delay element or the input signal; and a control part for selecting at least one of the plurality of delay parts on the basis of desired delay time information to transmit a control signal for operating so that the selecting circuit in the selected delay part selects a corresponding one of the delay elements, wherein a designed delay time value Dk of the delay element of a number k (1≦k≦n) delay part meets the following conditions. Thus, it is possible to provide a smaller circuit scale of a variable delay circuit.

Abstract: A circuit with a delay stage formed by an invertor having high-impedance transistors and, connected in series therewith, an invertor having low-impedance transistors MOS capacitors are provided between the gates of the transistors of the low-impedance invertor and the output of the delay stage. By means of this circuit, delay stages with steep edges can be realized with comparatively less outlay on components.

Abstract: A time delay apparatus using a transfer conductance. The time delay apparatus using an all-band pass filter can constitute the all-band pass filter having a required time delay with maintaining a frequency gain of an input signal by using a transfer conductance and the low frequency pass filter and easily control an amount of the time delay by varying the transfer conductance of the MOS transistor from outside.

Abstract: An edge triggered adjustable delay line circuit to determine the difference in time between a transition of a first signal and a transition of the second signal; a variably additive delay line circuit that will delay an input signal by a delay factor that is the sum of a multiplicity of variable delay factors; and a timing synchronization circuit to synchronize an internal timing signal with an external timing signal within one timing cycle is described. The timing synchronization circuit will utilize the edge triggered delay line and the variably additive delay line circuits to determine the synchronization parameters to synchronize the internal timing signal with the external timing signal.

Abstract: A delay circuit based on gate delay enables precise adjustment of a delay value. The delay circuit is composed of a plurality of p-channel transistors and n-channel transistors connected in series which are provided with capabilities that differ, ranging from the transistors closer to a power supply to the transistors closer to an output end so as to change the output drive capability and the input capacity independently, thereby improving the adjustment accuracy of the delay value of the circuit.

Abstract: A circuit and method for selectively and dynamically delaying a signal is presented. A series of delay modules are used to provide progressively finer delays. A multiplexer is used after each delay module to select one of a plurality of signals to pass on to a subsequent delay module. Each multiplexer is controlled by a control signal which can vary in time so that different delays can be selected for different portions of the signal to be delayed. By providing the proper control signals to the multiplexers any delay corresponding to a sum of the available individual delays generated by the individual delay modules is possible. The circuit and method are particularly useful for imposing individual delay times on the pulses in a logic level signal.

Abstract: Variable delay module (100) includes a clock generator (110), input A/D converter (120), buffering circuit (190), and output D/A converter (160). Clock generator (110) varies the output sampling rate of output D/A converter (160) relative to the input sampling rate of input A/D converter (120). Variable delay module (100) also uses a linear digital delay buffering circuit (190) to create a continuous delay of an analog signal through the module. Separate clocks (112, 114) are used to control the input and output stages of variable delay module (100). The second clock is asynchronous and continuously varying relative to the first clock. The second clock is generated using the coherent difference between the first clock and an autonomously generated reference phase (time) delay.

Abstract: The present invention provides a method for controlling a timing of a digital component having an impedance-input terminal. The method includes determining an impedance level present at the impedance-input terminal, and delaying the timing of the digital component based on the impedance level. The present invention also provides a digital component and a system, where the digital component includes an impedance-input terminal and an impedance matching circuit that is capable of determining an impedance level present at the impedance-input terminal. The digital component also includes a delay circuit that is capable of delaying a timing of the digital component based on the impedance level.

Abstract: A high resolution delay line includes a coarse delay having a minimum period of delay and a fine delay having a total delay, wherein the total delay is equal to or greater than half the minimum period. Each delay can be implemented in analog or digital form and the delay line can be implemented with one portion in analog form and the remainder in digital form. The digital delay can provide a delay upward of 1,500 milliseconds. The fine delay provides a resolution of ten microseconds or less. An unknown delay is measured by coupling a signal into two channels, wherein the first channel includes the unknown delay and the second channel includes the coarse delay and the fine delay. The output signals from the channels are correlated while adjusting the coarse delay for maximum correlation and then adjusting the fine delay for maximum correlation.

Abstract: To generate a signal delay, a current source, a reference voltage generator and a comparator are turned on. Once turned on, the current source raises the voltage across an initially discharged capacitor to a minimum required threshold. The comparator then compares the capacitor voltage to the reference voltage thereby to generate the delay signal. Thereafter, the current source, the reference voltage generator and substantial blocks of circuitry in the comparator are switched off to reduce quiescent power consumption.

Abstract: A delay circuit is provided for delaying signals. The delay circuit includes: at least one inverter having a time delay; at least one current source coupled to the at least one inverter, the at least one current source providing charging current to the at least one inverter; and a voltage biasing circuit coupled to the at least one current source, the voltage biasing circuit providing a biasing voltage to the at least one current source such that the at least one current source varies the charging current so as to maintain the time delay of the at least one inverter substantially constant.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: A ring oscillator is formed by connecting three or more odd gate circuits in a ring. Each gate circuit includes a precharge dynamic gate. An output signal from the precharge dynamic gate of one gate circuit is used to precharge the precharge dynamic gates of all the remaining gate circuits. In measuring the gate delay time of the ring oscillator formed by connecting, in a ring, three or more odd gate circuits each including a precharge dynamic gate, the oscillation frequency of the ring oscillator is measured, and the reciprocal of the oscillation frequency is divided by the number of gate circuits constituting the ring oscillator.

Abstract: A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.

Abstract: An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

Abstract: An apparatus that includes a driver circuit and an active load circuit coupled to an output of the driver circuit. The active load circuit is configured to actively adjust the slew rate of a signal outputted by the driver circuit.

Abstract: The present invention provides an apparatus and method for repairing or improving the behavior of a tunable circuit of an integrated circuit (IC) when a target parameter exceeds a predetermined range due to a design and/or fabrication problem. The tunable circuit includes one or more tuning controllers for tuning a corresponding number of target circuits. Each tuning controller includes one or more registers and an optional decoder. Each target circuit includes a tunable portion and a functional portion. The functional portion can have one or more of a wide variety of functions including but not limited to logical gates, buffers, signal generators and amplifiers. The selectable parameters of the tunable circuit include timing delays, trip voltages, rise/fall times and/or output impedances. When a circuit designer wishes to tune the target parameter, an appropriate tuning pattern is latched into registers of the tuning controller.

Abstract: A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator.

Abstract: A delay circuit is constituted by connecting a plurality of delay elements in series, each delay element is constituted by a pMOS transistor P1 and a nMOS transistor N1 having a larger driving capability than P1 and by a nMOS transistor N2 and a pMOS transistor P2 having a larger driving capability than N2, an input signal is applied to the gate of the transistor P1, a precharge signal is applied to the gate of the transistor N1, an inverted signal of the precharge signal is applied to the gate of the transistor P2, the gate of the transistor N2 is connected to an intermediate node A, an input signal S.sub.IN is input to each delay element as the precharge signal, and when the input signal S.sub.IN is at a high level, the node A is in the state of a low level and the output terminal OUT is in the state of a high level, the falling edge of the input signal S.sub.IN is sequentially propagated by delay elements, and thus a delay signal is obtained.

Abstract: A circuit to vary a frequency of an input clock is disclosed. The circuit includes a delay generator to generate at least two delayed clocks from the input clock and a select circuit coupled to receive the at least two delayed clocks and provide an output clock from one of the at least two delayed clocks. The select circuit switches the output clock from the one of the at least two delayed clocks to the other of the at least two delayed clocks on a first edge.

Abstract: Time-delay circuits are realized with first and second capacitors, a differential amplifier, a programmable current source and a differential pair of transistors. The current source directs first and second currents to the first and second capacitors and the differential pair steers a third current of the current source to either selected one of the capacitors to provide charging and discharging currents to the capacitors. The differential amplifier generates a delayed output pulse in response to voltages of the first and second capacitors. The capacitors are preferably formed by the interconnection system of an integrated circuit, i.e., the metallic circuit paths that are typically carried on an integrated-circuit substrate. N+1 of the delay circuits are combined with a phase comparator to form an interpolator that responds to an input data pulse by generating N output data pulses that span a period between the input data pulse and a successive input data pulse.

Abstract: A high resolution variable time delay circuit is disclosed. In one embodiment, a current digital to analog converter (DAC) is used to sequentially charge two capacitors having similar capacitance construction. A threshold level capacitor provides the threshold level to a comparator, and a ramping capacitor is used for ramping to the threshold to provide a delay time. The comparator provides a delayed pulse using the threshold level provided by the threshold level capacitor and the ramp provided by the ramping capacitor. Thus, resolution is better than that provided by digital elements alone. This circuit also automatically cancels errors due to capacitance variations and unit current variation of the DAC introduced during the manufacturing process. In another embodiment a single capacitor is used in combination with two current DACs and a comparator to provide a controllable time delay.

Abstract: A timing signal synchronization circuit to align an internal timing clock within an integrated circuit with an external system clock with minimum skew and within one cycle of the external system clock is disclosed. A timing signal synchronization circuit has an input buffer subcircuit to receive and delay the external system clock. A fixed delay line circuit is connected to the input buffer subcircuit to delay the received external system clock by a second delay factor to create a first timing signal. The first timing signal is the input to a first and a second measurement delay line. Each will respectively measure a first part and a second part of a period of the first timing signal. A first latch array will receive the measurement and create a first latch signal. A second latch array will receive the measurement and create a second latch signal.

Abstract: A programmable phase shifter includes a tapped delay line for successively delaying a periodic reference signal to produce a set of phase distributed tap signals. A multiplexer selects one of the tap signals as input to a programmable delay circuit which further delays the selected tap signal to produce an output signal that is phase shifted from the reference signal. A programmable data converter converts input data indicting a desired phase shift between the reference signal and the output signal into data for controlling the multiplexer selection and the amount of delay provided by the programmable delay circuit. The relationship between conversion table input and output data is adjusted so that the period of the output signal has a desired linear relationship to the input data value.

Abstract: An adjustable delay circuit for digital signals includes a series circuit which is disposed between two supply potentials and has at least a first transistor of a first conduction type and second and third transistors of a second conduction type. Control connections of the first and second transistors are connected to a signal input of the delay circuit. One connection of the first transistor, which is remote from the first supply potential, is connected to a signal output. A fourth transistor of the second conduction type is connected in parallel with the third transistor. A first control input is connected to a control connection of the third transistor and a second control input is connected to a control connection of the fourth transistor. The control inputs are used to adjust the delay time of the delay circuit.

Abstract: A programmable phase adjuster spans a clock signal's period with N linearly distributed phase steps. The resulting phase adjust resolution is finer than that of an inverter delay for a given process. Enhancement of the phase resolution of a phase picker CRM architecture enables use of the architecture for recovering clock signals from high data rate data streams in a way that minimizes power and area and allows optimization for multi-channel applications.

Abstract: Apparatus for supplying a signal after a predetermined time delay comprises circuitry for generating a base delay signal that is synchronized to a stable master oscillator insensitive to changes in at least one environmental variable. A vernier signal delay circuit provides delay increments smaller than those available from the base delay signal, the delay increments being sensitive to said at least one environmental variable. Storage circuitry is provided for storing information related to the duration of the delay increments as function of at least one environmental variable for which correction is to be supplied. Sensing circuitry is provided for sensing the at least one environmental variable for which correction is to be provided to supply a sensed at least one environmental variable.

Abstract: A time delay generator (20) includes a threshold generator (30), a ramp generator (32) and a comparator (34). The threshold generator provides a fixed threshold at one input of the comparator while the ramp generator provides at the other input a ramp signal whose slope is programmable. The ramp generator includes current switches (86 and 90) and a current converter (74). In response to input and range signals, the current switches provide a programmed input current and a programmed range current. The current converter generates a ramp current that is proportional to the range current and inversely proportional to the input current and couples that ramp current to an integrating ramp capacitor. The structure of the time delay generator facilitates noise filtering of the threshold signal and positioning of the threshold signal away from ramp nonlinearities.

Abstract: An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition.

Abstract: In accordance with this invention there is provided a circuit for delaying a selected edge of an input signal for use in a deep sub-micron process semiconductor device, the circuit comprising an inverter element having an input and output node, a load element comprising resistive and capacitive (RC) elements a first transistor element, coupled to the RC load element and selectively operable to couple the RC element to the output node upon receipt of the selected edge of the input signal and for decoupling the RC element from the output node upon receipt of an opposite edge of the input signal, whereby a delay is introduced by the load element on the selected edge of the input signal with little negative effect on the opposite edge of the input signal.

Abstract: An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter etc. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.

Abstract: A controlled delay circuit having a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third signals generated in the first gate chain and representing the time difference, is used to provide an appropriate delay time from an input to an output depending on the time difference. The controlled delay circuit is capable of properly controlling the timing of the control signal according to the period of the control signal.