Abstract: A configurable voltage bias circuit is used to control gate delays in buffers by adjusting the supply voltage of the buffers. The programmable voltage bias circuit includes a configurable voltage divider, which receives an input supply voltage and generates an output supply voltage, and a configurable resistance circuit, which is coupled between the configurable voltage divider and ground. By using a temperature dependent reference voltage to generate the input supply voltage, the output supply voltage is also made to be dependent upon temperature. The programmable voltage bias circuit of the present invention uses the temperature dependence of the output supply voltage to make the gate delays of the buffer temperature-independent.

Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Abstract: Provided are a delay stage and a delay circuit that are insensitive to an operating voltage and have a constant delay time irrespective of a time interval between input signal pulses. The delay stage includes a first inverter that inverts an input signal, a first capacitor having one end connected to a first voltage node, a first switch that is connected between the other end of the first capacitor and an output terminal of the first inverter and is turned on in response to a control signal, a second inverter that inverts an output signal of the first inverter, a second capacitor having one end connected to a second voltage node, and a second switch that is connected between the other end of the second capacitor and an output terminal of the second inverter and is turned on in response to an inverted signal of the control signal.

Abstract: Methods of and apparatuses for matching the signal delay, clock timing, frequency response, gain, offset, and/or transfer function of signal pathways in electrical circuits such as, for example, time-interleaved and pipelined circuits using analog-valued floating-gate MOSFETs are disclosed. The methods and apparatuses disclosed are applicable to a variety of circuits, including but not limited to, sample-and-hold or track-and-hold circuits, quadrature mixers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog or digital filters, and amplifiers.

Abstract: A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.

Abstract: A dynamic phase adjustment circuit that includes a multi-tap delay line that receives a clock input signal. The multi-tap delay line includes an initial portion that is adjustable, and final portion after the adjustable portion. A number of registers receive the same data. However, the clock signal that causes the registers to sample is received from a corresponding delay element in the final portion of the multi-tap delay line. An edge detect and data decision circuit receives the sampled data values from each of the registers. Sampling resolution is improved over the PLL-based dynamic phase adjustment circuit since the clock signal is delayed using delay elements, which can be made with relatively small delays. Furthermore, the circuit does not contain excessive circuit elements thereby allowing the dynamic phase adjustment circuit to be contained in a small area.

Abstract: A delay locked loop for use in an integrated circuit device includes a coarse delay chain in series with a micro-stepped delay chain. The coarse delay chain includes a plurality of coarse delay units configured for selectively providing a coarse delay with respect to an input clock signal, and the micro-stepped delay chain is configured for selectively providing a fine delay adjustment with respect to the input clock signal. The micro-stepped delay chain further includes a plurality of parallel signal paths, wherein one or more of the parallel signal paths are capacitively loaded so as to provide the fine delay adjustment.

Abstract: A voltage controlled oscillator (VCO) for use in a personal area network synthesizer includes a delay cell (100), a first current amplifier (201, 203) for amplifying an input current, a resister capacitor (RC) tuning network (207, 209, 211) for varying the amount of amplification and delay of an output of the first current amplifier. A second current amplifier (213, 215) is then used for amplifying an output current from the RC tuning network. The invention includes a unique composite voltage variable capacitor (CVVC) (300) for precisely tuning the amount of delay presented by the delay cell. The unique topology of the delay cell (100) allows it to be readily used in voltage controlled oscillators (VCOs) operable at frequencies above 1 GHz.

Abstract: Digital delay-locked loops (DLLs) and methods are provided for signal frequency multiplication. Analog delay elements of typical frequency-multiplying DLLs are replaced with digital and digitally-controlled elements including a variable delay line. The number of unit delay elements in the delay line can be selected to produce a desired output signal delay. Phase-mixing of multiple variable delay line outputs achieves finer delay-time adjustments.

Abstract: The present invention relates to a semiconductor device; and, more particularly, to a delay adjusting circuit which is required to adjust a delay time of an internal circuit in a test mode and required to verify a characteristic and a margin of the semiconductor device. The delay adjusting apparatus according to the present invention comprises: a normal delayer for delaying an input signal from an external circuit; a delay time storage for maintaining a predetermined delay time produced by a control signal and delaying the input signal based on the predetermined delay time; and a selector for selectively outputting one of output signals from the normal delayer and the delay time storage in response to a test mode signal.

Abstract: A delay unit for providing an output signal delayed by a delay time with respect to a periodic signal received at its input, the delay unit comprises a first delay cell adapted to receive the periodic signal and to provide as output a first delayed signal corresponding to the input periodic signal but delayed by a variable first delay time. A selection unit receives the first delayed signal and a second signal derived from the periodic signal. A control unit controls the selection unit in order to select one of the first delayed signal and the second signal as the output signal of the delay unit, and further controls the first delay time of the first delay cell.

Abstract: A variable-delay signal generator circuit includes a delay chain and an interpolator circuit. The delay chain produces multiple multi-phase signals, where each of the multi-phase signals represents a delayed version of an input event signal. Each of the multi-phase signals is separated from consecutive signals by a first phase increment. The interpolator circuit includes multiple interpolator blocks, where each block receives a multi-phase signal. The interpolator circuit interpolates between consecutive interpolator blocks, to produce an output signal that represents a modified-delay version of the input event signal. The output signal is delayed to one of multiple phase delays that exist between consecutive multi-phase signals, inclusive. To produce the output signal, a variable current source within each interpolator block is adjusted, based on a current source select signal. The current source select signal is produced by a bias circuit, which includes a split current source.

Abstract: An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.

Abstract: A variable delay circuit comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements, according to a number of the first variable delay elements; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.

Abstract: A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2N is described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2N clocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.

Abstract: A delay circuit having an adjustable delay resolution is provided. The delay circuit has a path through which a signal transmits, a field effect transistor whose source region and drain region are connected to the path, and an impressed voltage control unit which controls a voltage to be impressed to the gate electrode of the field effect transistor. The impressed voltage control unit may be a digital analog converter.

Abstract: A delay adjusting circuit that can minimize a delay at selectors even when the number of delay stages and the number of selector stages are increased, to enable a stable and speedy operation. As selectors S in a delay producing circuit (11), 2:1 selectors, each of the type that selectively outputs one from two inputs, may be used which are connected to input/output portions of N-stage delay elements D1 to DN for enabling delayed output of an even-stage delayed clock signal (Even) and an odd-stage delayed clock signal (Odd). In this case, the 2:1 selectors are arranged in a two-stage configuration including the for-even-stage selectors (S1, S3, . . . , Sn, S(n+2)) and the for-odd-stage selectors (S2, . . . , S(n+1), S(n+3)). The even-stage delayed clock signal (Even) is obtained through the first-stage selector S1. The odd-stage delayed clock signal (Odd) is obtained through the second-stage selector S2.

Abstract: Techniques for dynamically shifting the phase of clock signals are provided. A circuit generates a plurality of periodic clock signals. Each clock signal has the same period, the same duty cycle, and a different phase. The clock signals are provided to the inputs of two multiplexers. The output signals of the multiplexers are transmitted to a phase selection circuit that generations phase selection signals. The multiplexers each select one of the clock signals in response to the phase selection signals. When the phase selection signals change value, each multiplexer selects a different clock signal in order to shift the phase of its output signal forward or backward by an incremental value. A directional signal determines whether the multiplexers shift the phases of their output signals forward or backward in time.

Abstract: An electronic system includes a deskewing circuit configured to measure a delay and generate a synchronized signal according to the measured delay. The deskewing circuit may be configured to detect an overflow condition and respond accordingly, for example by asserting an overflow signal. Further, the deskewing circuit may be additionally or alternatively configured to detect successful measurement of the delay and respond, for example by executing a power saving and/or noise reducing procedure.

Abstract: The device for controlling a setup/hold time of an input signal can change a setup/hold time of various control signals applied from an input buffer without physically changing the control device. The device for controlling a setup/hold time of an input signal has transmission gates for performing selectively switching operations according to a decoded test mode control signal, thereby selectively using a signal delay device in driving of drivers to appropriately control the setup/hold time of various control signals applied from a global bus line. Accordingly, the device for controlling a setup/hold time of an input signal can provide a technique which can optimize the setup/hold time at a small cost in comparison with a physical metal option control system.

Abstract: A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

Abstract: The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array 10 for carrying out fine adjustment of the delay time interval of the input signal, capacitances 60 to 63 and 70 to 73 connected to the output side of a specified gate in the first gate array via first switching device 40 to 43, a second gate array 20 for carrying out rough adjustment of the delay time interval of the input signal; and a control device 30 that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array 20.

Abstract: Phase modulating systems and methods for modulating the phase of a signal are based on a digital control signal used to select one of a plurality of carriers having different phase angles. In order to reduce the number of short delays that have to be applied to the original signal for obtaining the plurality of carriers, it is proposed that delay elements are arranged in a matrix form. Alternatively, phase shifts are realized by digital frequency dividers instead of by delay elements. Further alternatively or in addition, part of the required delay is approximated or realized by an analog phase shifter. In case the phase modulating system is to be employed for modulating signals of different frequencies, the digital control signal is scaled with a factor associated to the respective frequency in order to change the addressing range for selecting a carrier from among the plurality of carriers.

Abstract: A ring oscillator stage includes two differential transistor pairs configured to add an adjustable amount of delay to a differential input signal. Each differential pair is biased with a bias current transistor; the bias current transistor is “protected” by a voltage-clamping transistor that limits the drain voltage of the bias current transistor. The voltage-clamping transistors enable use of a power supply voltage (VDD) that would otherwise exceed the reliability breakdown voltage limit of the bias current transistors.

Abstract: Embodiments are provided in which a method for delaying a strobe signal for a first pre-specified amount of time is described. A test signal is sent through a first number of delay books and a test is done as to whether it takes the test signal approximately a second pre-specified amount of time to pass the first number of delay books. Then, the number of delay books is increased or decreased by one at a time and until the number of delay books reaches a second number where it takes the test signal approximately the second pre-specified amount of time to pass the second number of delay books. From the second number, a third number of delay books is determined which is needed to cause a propagation delay approximately equal to the first pre-specified amount of time. Finally, the strobe signal is passed through the third number of delay books.

Abstract: The invention relates to a digital signal delay device (101) for converting a signal (IN) into a corresponding delayed signal (OUT), comprising a plurality of signal delay elements (103a, 103b, 103c) connected in series, wherein, as a function of the desired delay of the delayed signal (OUT), the output signal of a particular signal delay element (103a, 103b, 103c) is used for generating the delayed signal (OUT), and wherein the signal delay elements (103a, 103b, 103c) each comprise one single inverter (105, 106, 107) only.

Abstract: A delay circuit delays an input signal to produce an output signal. The input and output signals have a delay which is based on a signal relationship between the input signal and a reference signal. The delay circuit includes configurable devices to vary the reference signal to adjust the delay between the input and output signals.

Abstract: An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18).

Abstract: Two first delay signals Q30 and Q34 are generated such that edges thereof are delayed by a first delay time Td1 in relation to the rising edge of a clock signal CLK. Two second delay signals Q32 and Q36 are also generated such that edges thereof are delayed by a second delay time Td2 in relation to the trailing edge of the clock signal CLK. A pulse signal Sout is generated as a result of logic operations performed on the first delay signals Q30 and Q34 and the second delayed signals Q32 and Q36.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to wake-up the second circuit in response to an input signal. The input signal generally comprises a programmable delay value.

Abstract: A digital control variable delay circuit includes n amplitude control units which are connected in parallel and each of which receives a pair of input clock signals to be supplied to a differential pair and receives m-bit digital control signals, and a waveform shaping unit which is connected to the outputs of the n amplitude control units. Each amplitude control unit is capable of varying the amplitude of each of the pair of clock signals into (m+1) values using the m-bit digital control signals, and outputs a pair of amplitude-varied clock signals. The waveform shaping unit receives a pair of added clock signals obtained by adding and combining the pairs of amplitude-varied clock signals outputted from the n amplitude control units and outputs a pair of resultant clock signals as output signals.

Abstract: A system for coordinating the timing of a data strobe with data supplied by a memory module to the memory controller read data FIFO of a processor-based system, providing multiple calibration modes. A calibration PDL (programmable delay line) is used to reiteratively test the time taken for a test data strobe to traverse a portion of the memory controller circuit, and to generate a calibration value based upon the time taken. The calibration procedure may be initiated in any one of several modes, including: according to a predetermined schedule; implemented in software; in response to changes in environmental factors such as temperature or voltages sampled at one or more locations; in response to a software-driven trigger; or in response to a user-initiated trigger, communicated to a system of the invention either by input via a user interface to the processor-based system or by a software command.

Abstract: A method and apparatus for delay tuning an integrated circuit which includes a delay element that includes a plurality of delay stages interconnected in a cascaded relationship, each stage imposing an incremental delay upon the input signal when enabled, the delay element receives a selection signal that determines how many of the delay stages are enabled. By varying the select signal, the delay element imposes, a variable delay upon the input signal for testing and evaluation.

Abstract: In a semiconductor integrated circuit, the internal clock that is synchronized to the external clock is counted to output data according to desired specification of the integrated circuit and clock counting in high frequency operation is made be possible by using parallel internal clocks having various delay times. Particularly, reduction of margin of the clock count due to error between the delay time in the delaying circuit and the time to be compensated can be prevented by independently counting the internal clock and the inverted internal clock.

Abstract: An electronic circuit includes delay selection units each associated with a flip-flop or other circuit element. The delay selection unit for a given one of the circuit elements is coupled between a source of a clock or other signal and a corresponding input of the circuit element, and is controllable to provide one of a number of selectable delays for the signal. One or more of the delay selection units are controlled so as to select a particular one of the selectable delays for each of the units. In an illustrative embodiment, the particular delays may be determined at least in part based on the solution of an integer nonlinear program in which the plurality of delays for a given one of the delay selection units are arranged substantially in a monotonically increasing manner and each of at least a subset of the selectable delays for the given one of the delay selection units is specified by upper and lower bounds on the corresponding delay.

Abstract: Balanced programmable delay element that has a variable incremental delay. A first inverter is provided that has a first electrode for receiving an input signal, a second electrode, a third electrode, and a fourth electrode for providing an output signal and that has a propagation delay that is dependent on a first current. A second inverter is provided that has a first electrode coupled to the fourth electrode of the first inverter for receiving the output signal of the first inverter, a second electrode, a third electrode, and a fourth electrode for providing an output signal and that has a propagation delay that is dependent on a second current. A current switch is coupled to the first inverter, the second inverter, receives at least two control signals, and responsive thereto, selectively varies the incremental delay of the delay element.

Abstract: An apparatus for minimizing a skew occurring due to a change of data pattern by previously recognizing data pattern before data is outputted from the semiconductor device. The apparatus of compensating for a phase delay in a semiconductor device having a delay locked loop (DLL) for generating DLL clock includes: a data pattern detection block for detecting patterns of data loaded on data line and determining delay compensation amount of the data inputted to data output driver based on the detected data patterns; and a delay compensation block for compensating for phase delay of clock relating to the DLL clock inputted to the data output driver under a control of an output signal of the data pattern detection block.

Abstract: Method and apparatus for reducing power dissipation and jitter in a delay line is described. The delay line includes a plurality of delay elements. At least one of the plurality of delay elements includes a gate terminal configured to receive gate control signals for activating or deactivating one or more of the delay elements. The delay line further includes gate control circuitry for providing gate control signals to the gate terminal of at least one of the plurality of delay elements.

Abstract: A synchronization circuit includes a first and second phase-shifting path circuit, with each generates a phase-shifted signal responsive to an input signal and the phase-shifted signal having respective fine and coarse phase shifts relative to the input signal. Each phase-shifting path circuit adjusts the coarse and fine phase shifts responsive to control signals. A selection circuit outputs one of the phase-shifted signals responsive to a selection signal. A control circuit monitors a phase shift between the input signal and the output phase-shifted signal and develops the selection and control signals to select one of the phase-shifting path circuits and to adjust the fine phase shift of the selected path circuit and the fine and coarse phase shifts of the other path circuit. When the fine delay of the selected phase-shifting path circuit has a threshold value, the control circuit develops the selection signal to select the other phase-shifting circuit.

Abstract: The present invention relates to a semiconductor device; and, more particularly, to a delay adjusting circuit which is required to adjust a delay time of an internal circuit in a test mode and required to verify a characteristic and a margin of the semiconductor device. The delay adjusting apparatus according to the present invention comprises: a normal delayer for delaying an input signal from an external circuit; a delay time storage for maintaining a predetermined delay time produced by a control signal and delaying the input signal based on the predetermined delay time; and a selector for selectively outputting one of output signals from the normal delayer and the delay time storage in response to a test mode signal.

Abstract: A synchronous mirror delay includes a ring oscillator that generates a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal. In response to an input clock signal, a model delay line generates a model delayed clock signal having a model delay relative to the input clock signal. A coarse delay circuit generates a coarse delay count responsive to the oscillator, input, and model delayed clock signals, and activates a coarse delay enable signal responsive to the delay count being equal to a reference count value. A fine delay circuit latches the tap clock signals and develops a fine delay from the latched signals, and activates a fine delay enable signal having the fine delay in response to the coarse delay enable signal. An output circuit generates a delayed clock signal responsive to the coarse and fine delay enable signals going active.

Abstract: A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a delay in the first circuit, a delay control block for controlling an internal source potential based on the estimated delay for controlling the source potential for the second circuit so that the signal delay from the second circuit has small variations of delay time. The integrated circuit can be formed on a reasonable specification, and achieves a lower dissipation and a higher reliability.

Abstract: A latch includes an inverter; a pass transistor having a first terminal coupled to an input of the inverter and a second terminal coupled to a programming voltage; a first capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a first predetermined voltage; and a second capacitor having a first terminal coupled to the input of the inverter and a second terminal coupled to a second predetermined voltage; wherein each of the first and second capacitors uses an antifuse.

Abstract: In general terms, the present invention is a voltage-controlled delay line (VCDL) comprising a series of delay cells outputting a clock output signal having a delay relative to a clock input signal input to the series of delay cells. A duty-cycle correction section corrects the duty cycle of the clock output signal by providing opposite current outputs which are fed back to the series of delay cells to substantially simultaneously charge and discharge current of the series of delay cells in opposite directions. A control current input to the series of delay cells controls the amount of the delay. A voltage-to-current converter converts a control voltage into the control current so that the delay changes substantially linearly as the control voltage changes. The method for using the VCDL to produce linear delay is also included. The VCDL can be used in a delay-locked loop (DLL).

Abstract: Described are methods and circuits for aligning data and clock signals. Methods in accordance with some embodiments separate incoming data into three differently timed data signals: an early signal, an intermediate signal, and a late signal. The timing of the three data signals can be collectively moved with respect to the clock signal. In addition, the temporal spacing between the three signals can be adjusted so that the early and late signals define a window encompassing the intermediate signal. The three signals are aligned with respect to the clock edge to center the intermediate data signal on the clock edge. The early and late signals can be monitored to identify changes in the relative timing of the clock and data signals. Some embodiments automatically alter the timing of the data and/or clock signals to keep the intermediate data signal centered on the clock edge.

Abstract: A programmable delay circuit having a plurality of course delay stages (coupled in series fashion) and a fine delay stage having a plurality of parallel organized delay paths is described, wherein each of the parallel organized delay paths is adapted to receive input from a common course delay stage and to delay a signal for a different specified amount of time. The programmable delay circuit may provide a relatively large overall signal delay (provided primarily by the course delay stages), while also providing a fine temporal resolution (provided primarily by the fine delay stage).

Abstract: A clock pulse generator for generating at least two clocked pulse signals from a global clock signal is provided. The clock pulse generator includes at least one input for receiving a clock signal having a rising and a falling edge and a mechanism for selectably delaying a rising edge of a pulse signal synchronized to the falling edge of the clock signal. The clock pulse generator further includes a first selectable duration pulse synchronized to the rising edge of the clock signal and a second selectable duration pulse synchronized to the selectably delayed rising edge. The clock pulse generator also includes a glitch avoidance circuit to remove glitches in the clock signal before it is used.

Abstract: A device for the comparison of two resistors is based upon analog information carried by currents. The device includes a measurement circuit for extracting the currents from the two resistors to be compared, and copies the currents to a parallel analog-digital converter that carries out the division of the extracted currents. The device converts the ratio of the extracted currents into a digital code that is the image of the ratio of the two resistors. The ratio is constantly re-updated as a function of environmental parameters of the circuit, such as the operating temperature. Also disclosed is a system for correcting the value of integrated compensated resistors. The system implements a device of this kind that does not use a reference voltage generator.

Abstract: A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.

Abstract: According to the present invention, a variable delay circuit includes a delay circuit unit group, a control unit and an offset delay amount memory group. The delay circuit unit group includes a plurality of delay circuit units, and the plurality of delay circuit units includes two paths having different delay amounts. The offset delay amount memory group includes a plurality of offset delay amount memories, and offset delay amounts corresponding to delay amounts of the first paths of the corresponding delay circuit units are set in the plurality of offset delay amount memories. The control unit includes a plurality of subtracting units, and the plurality of subtracting units select paths of the delay circuit units through which an input signal may pass by using a delay setting value and offset delay amounts. It is possible to reduce volume of the circuit and remove a table since the path is selected by calculation.