Abstract: Disclosed is a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., by performing coarse period adjustment in advance. A plurality of delay sensing circuits having slightly overlapping operating ranges and different centers of operation are connected in parallel with respect to a an input clock signal, which is passed through the delay sensing circuits. The period of the clock is sensed coarsely in short periods using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.

Abstract: A delay stage for use in a voltage-controlled delay chain of a delay locked loop or in a voltage-controlled ring oscillator of a phase locked loop has pullup and pulldown transistors driven by a first input to the delay stage, at least one of which is in series with a delay control transistor, and a second pullup and pulldown transistor gated by a second input to the delay stage. When used in a delay chain, the first input is driven by a signal that leads the second input to the delay stage.

Abstract: A fixed frequency clock generator generates and outputs a fixed frequency clock by using a number of fixed delay units and a number of inverters that both are connected in series alternately and evenly. More particularly, the fixed delay unit involves two fixed current sources and two controlling switchers, plus an inverter that controls a charging and a discharging of a capacitor. Then the electric potential of the capacitor and a stable voltage source respectively send the current to the comparator. The time of charging and discharging of the capacitor is fixed, therefore the time of the electric potential of the capacitor is fixed for reach to the fixed voltage source, and the sequence of the output signal of the comparator is also fixed. In the above description, the fixed delay unit generates the fixed frequency.

Abstract: A comparison circuit may be fabricated along with a primary circuit on a semiconductor substrate. The propagation delay of a comparison signal across a first path of circuit elements is compared to propagation delays of the comparison signal across a second path of delay elements. As a semiconductor fabrication process varies, the relative propagation delays across the first and second paths will vary in a manner correlative to the process variations. By monitoring the relative propagation delays, the fabrication process may be controlled to ensure that the process does not vary to an undesirable extent. Also, various programmable delay elements may be fabricated into the primary circuit, and these programmable delay elements may be activated and/or deactivated in response to the relative propagation delays of the comparison circuit.

Abstract: A clock multiplier (40) comprises a digital phase lock loop circuit having a single variable delay stage (44) for generating high and low phases for the output clocks. The variable delay stage (44) includes a commutator 64 which chooses between the signal propagating on first and second delay paths (52 and 54). The delay on the delay paths can be incrementally adjusted using capacitors (58 and 61) selectively enabled between the path and ground. If the variable delay is insufficient to lock the output to the reference clock, a prescaler (72) automatically divides the output as needed. A stutter mode prevents short pulses, caused by a transition of the reference clock arriving shortly after the transition of the output clock to a low state, from being passed to the clock multiplying circuitry. The clock multiplier (40) may use a free running mode after lock is obtained, where adjustments are made relative to the degree of difference between the output clock and the reference clock.

Abstract: An integrated circuit having a locking circuit and method using the same are provided. The locking circuit includes a time-to-digital converter. The time-to-digital converter includes first and second delay chains, each for delaying one of two input signals at predetermined intervals. The time-to-digital converter also includes first and second phase comparators, each for comparing the delayed signal with the other signal and generating a digital signal. The locking circuit converts the phase difference between a feedback signal and an internal clock signal into a delay control signal group using the time-to-digital converter. The delay control signal group controls the delay time of a mirror delay circuit to rapidly minimize the phase difference between the feedback signal and the internal clock signal.

Abstract: A digital delay interpolator adapted to receive a first clock signal and a second clock signal, the second clock signal having a transition at a time that is delayed with respect to the time of a transition of the first clock signal, and to provide an output clock signal having a transition at a time intermediate the time of the transition of the first clock signal and the time of the transition of the second clock signal. The interpolator includes a first plurality of selectively enabled delay circuits and a second plurality of selectively enabled delay circuits, the first plurality of delay circuits having an input port being adapted to receive the first clock signal, and the second plurality of delay circuits having an input port being adapted to receive the second clock signal. The first plurality of delay circuits and the second plurality of delay circuits have outputs connected together to form the output of the digital delay interpolator.

Abstract: A voltage-controlled CMOS delay cell includes a pair of inverters and a pair of load cells. The load cells are controllable by independent N and P bias control voltages to vary the delay of the delay cell. Symmetric P and N load capacitors in the delay cells, together with the N and P bias control voltages, provide effective rejection of noise on the power supply rails and enable the delay cell to generate symmetric low-going and high-going delays. The P bias control voltage is generated from the N bias control voltage by a closed-loop voltage control circuit. Also described are a voltage-controlled load cell, an integrated circuit, an electronic system, and a data processing system that incorporate one or more of the symmetric CMOS voltage-controlled delay cells.

Abstract: The delay time of a variable delay circuit is set to a desired value by: sequentially applying a plurality of clocks of different frequencies to a variable delay circuit; finding, for each clock, the amount of change in delay time with respect to change in a delay time selection signal, which is a signal for setting the delay time of the variable delay circuit; finding a linear coefficient of the characteristic of the delay time of the variable delay circuit with respect to the delay time selection signal from the difference in the amounts of change with respect to the difference in clock frequencies; finding an amount of offset with respect to the delay time selection signal that pertains to the variable delay circuit from the amounts of change and frequencies of the clocks; and finding the delay time selection signal from the linear coefficient and the difference between the desired delay time and the offset amount.

Abstract: A sync signal generating circuit has a first I/O replica for delaying an external clock signal, a comparator replica with a variable delay time for delaying an output of the first I/O replica, a first ramp-voltage generating circuit for outputting a first voltage whose potential level begins to rise at a time of transition of a level of the output of the comparator replica and stops rising at a predetermined timing, a second ramp-voltage generating circuit for outputting a second voltage whose potential level begins to rise after the rising of the potential level of the first voltage stops, a voltage comparator for comparing the first and second voltages and outputting an internal clock signal, a second I/O replica for delaying the internal clock signal with a delay time substantially equal to the delay time of the first I/O replica, and a phase comparator for comparing a phase of an output of the second I/O replica and a phase of an input to the first I/O replica.

Abstract: A precision delay system allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry. The system allows the use of delay elements with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. A single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. Further, only one delay line is required to implement the DLL circuit. Therefore, the DLL of the present invention is both quick to “lock in” a clock signal and efficient in the use of hardware resources. Further, the present DLL is very accurate, because the same delay line is used to calculate the necessary additional delay and to generate the output clock signal.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system filter includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A delay circuit including a plurality of interpolators connected in cascade. Each of the interpolators receives a reference clock signal and a clock signal output from the preceding interpolator. One of the interpolators generates a clock signal whose transition edge is between the transition edge of the reference clock signal and the transition edge of the clock signal. The subsequent interpolators operate as delay stages, thereby generating a delayed clock signal delaying from the reference clock signal by a predetermined time. It is possible to make smaller the minimum unit of a delay adjustment to the delayed clock signal by using the interpolators.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: In a multiplying circuit for providing a pulsed output clock signal having a frequency that is a multiple of a pulsed input clock signal, a delay of a digital delay line is initialized by initializing a counter when an external reset signal is input and when the number of pulses of the output clock signal from the clock generator is smaller than a predetermined multiplier. The delay of the digital delay line is set to a minimum value immediately following the initialization and then increased gradually in order to output the desired output clock signal.

Abstract: A delay circuit in accordance with the present invention provides high-resolution changes in the time delay by utilizing a slope controller that generates an intermediate signal having sloping edges in response to edges in an input signal. A delay time controller generates an output signal having edges that begin when the level of the intermediate signal reaches a certain level. The overall time delay of the delay circuit can be varied by varying the slope of the edges of the intermediate signal, or by varying the level of the intermediate signal at which the delay time controller begins generating an edge in the output signal, or by varying both parameters. The slope controller and delay time controller can be realized with a plurality of tri-state inverters coupled in parallel for operating responsive to one or more select signals. By implementing the inverters with pull-up and pull-down transistors having different sizes, the overall time delay can be varied with very high resolution.

Abstract: A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (“DLL”) circuits in integrated circuit (“IC”) devices such as double data rate (“DDR”) dynamic random access memory (“DRAM”), static random access memory (“SRAM”), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter.

Abstract: An integrated circuit has a plurality of signal paths, at least one of which has a delay cell. The delay cell has an input terminal for receiving an signal from the signal path, and a plurality of delay paths for generating a corresponding plurality of delayed signals delayed by different delays from the input signal. At least one of the delay paths employs two different-delay subpaths coupled in parallel to provide a delayed signal delayed by an interpolated delay. A multiplexer (MUX) of the delay cell provides one of the delayed signals as an output signal to the signal path based on a control input signal applied to the multiplexer.

Abstract: A circuit comprising an oscillator, a reference path, and a feedback path. The oscillator may have a reference input receiving a reference signal, a feedback input receiving a feedback signal, and an output. The reference path may provide the reference signal from a reference clock input. The feedback path may provide the feedback signal from the oscillator loop output. At least one of the reference path and the feedback path comprises a programmable delay circuit.

Abstract: A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A semiconductor device includes a timing-stabilization circuit which adjusts a phase of the synchronization clock signal. The semiconductor device further includes a control circuit which suspends the adjustment of the phase of the synchronization clock by the timing-stabilization circuit during a time period when the data is output from an output circuit.

Abstract: A clock qualification circuit used to selectively enable a clock edge to transfer new delay data from a first-in-first-out (FIFO) circuit in a precision delay line circuit. The circuit qualifies the clock without generating undesirable pulses (glitches) and causing false loading of new delay data in a timing on the fly delay line implementation.

Abstract: A delay locked loop (DLL) circuit (10) having an internal clock signal (D3) with positive and negative clock edges locked with an externally applied clock signal (D1) is provided. The DLL circuit (10) can include first phase decision circuit (1), a second phase decision circuit (2), an arbitrary phase generator circuit (3), and a variable pulse width circuit (4). First phase decision circuit (1) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D4) that may indicate whether a first edge of internal clock signal (D3) is to be sped-up or delayed. Arbitrary phase generator circuit (3) may provide a phase shifted signal based on phase decision signal (D4). Second phase decision circuit (2) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D5) that may indicate whether a second edge of internal clock signal (D3) is to be sped-up or delayed.

Abstract: An improved edge-triggered fully digital delay locked loop (DLL), which maintains reliable synchronization from startup and in spite of system clock jitter is described. An internal clock signal is synchronized with a reference clock signal by propagating the reference clock signal through a variable digital delay path. A wide phase detection region surrounds a selected rising edge of the internal clock signal. The DLL loop is open as long as the internal clock signal and a target edge of the reference clock signal are not simultaneously within the phase detection region. To achieve a DLL locked condition, the variable delay is increased from a minimum setting until the edge of the phase detection region is shifted in time just past the target edge of the reference clock. Once the DLL loop has been closed, a clock jitter filter is enabled to reject reference clock jitter effects on the DLL locked condition.

Abstract: The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay element supply line to a voltage on a current control node connected to a voltage controlled current source. An RC compensating circuit may be coupled to the current control node.

Abstract: A receiver circuit in a system for transferring data signals among integrated circuits or logic circuit blocks includes a receiving interface for allowing the data signal to be received at a correct timing. The receiving interface includes a detecting circuit for detecting whether or not a signal to be received has arrived at a detecting timing determined on the basis of a clock signal providing a timing base for signal receiving operation, a variable delay circuit inserted in a signal transfer path whose delay factor is controlled in dependence on the result of detection performed by the detecting circuit, and a flip-flop circuit for latching the signal outputted from the variable delay circuit in synchronism with the clock signal.

Abstract: A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals (“beat” and “clock”) wherein the period PB of the beat signal and the period PC of the clock signal are related by the expression PB=PC(N+1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.

Abstract: The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are inactivated. Not operating unnecessary delay stages can prevent wasteful power consumption.

Abstract: A delay circuit that is insensitive to variations in an input signal voltage level has a voltage clamp at its input terminal to fix the input voltage level so as to remove the sensitivity of the delay circuit to the variations in the input signal voltage level and the power supply voltage source. A voltage independent delay circuit is composed of a first inverter circuit, a voltage clamping circuit, a delay capacitor, and a second inverter circuit. The first inverter circuit has an input terminal and an output terminal. A first output signal at the output terminal is an inverse of an input signal at the input terminal. The voltage clamping circuit is connected between the output terminal and the input terminal of the first inverter circuit to fix a voltage swing of input signal to a first voltage level. The delay capacitor connected to the output terminal of the first inverter to establish a transition time of the first output signal.

Abstract: An initial phase control for an oscillator such as a differential ring voltage-controlled oscillator is disclosed. The initial phase control generally comprises a current source circuit coupled to a first node of the delay cell and a current provider. The current source circuit and current provider are preferably selectively and synchronously in an on or off state such that when the current source circuit and current provider are in an on state, the current source circuit draws a current through the first node of the delay cell and the current provider provides current through a second node of the delay cell. A method for controlling a delay cell and an initial phase control for a differential ring oscillator having a plurality of delay cells in a ring configuration are also disclosed.

Abstract: A variable delay circuit includes a ramp voltage generating unit having a storage capacitor, a charging transistor for charging the capacitor and a constant-current source for discharging the capacitor, and a comparator for comparing the output of the ramp voltage generating circuit against a voltage setting to output a delayed signal. The electric charge flowing out from the output node of the ramp voltage generating unit through the charging transistor during generating the ramp voltage is compensated by a compensating capacitor to output a linear ramp voltage.

Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Abstract: A system and method for providing a programmable delay to an input signal in a device requiring setup and hold times for input signal, such as a DRAM device. In one embodiment, the programmable delay network 5 comprises a plurality of delay devices and at least one fuse connected between the input of the delay network 5 and the output of the delay network 5. Each fuse can connect in series with at least one delay device in such a manner that opening a fuse, or a combination of fuses, changes the amount of delay time the input signal experiences through the delay network.

Abstract: A delay time control circuit comprises a delay circuit composed of 2n series-connected unit delay circuits each including a pair of series-connected, first and second inverters, where n is an integer equal to or more than 2, buffer circuits each connected to an output of each of the first and second inverters of the unit delay circuits of the delay circuit, 2n−1 first connection lines each connecting between outputs of adjacent ones of the buffer circuits connected to the second inverters and 2n−2 second connection lines each connecting between adjacent ones of the first connection lines. In response to an input signal input to the first inverter of first one of the unit delay circuit, an output signal delayed with respect to the input signal is obtained through one of the first connection lines and one of the second connection lines.

Abstract: A digital delay interpolator adapted to receive a first clock signal and a second clock signal, the second clock signal having a transition at a time that is delayed with respect to the time of a transition of the first clock signal, and to provide an output clock signal having a transition at a time intermediate the time of the transition of the first clock signal and the time of the transition of the second clock signal. The interpolator includes a first plurality of selectively enabled delay circuits and a second plurality of selectively enabled delay circuits, the first plurality of delay circuits having an input port being adapted to receive the first clock signal, and the second plurality of delay circuits having an input port being adapted to receive the second clock signal. The first plurality of delay circuits and the second plurality of delay circuits have outputs connected together to form the output of the digital delay interpolator.

Abstract: A variable delay section comprises a gate element and a plurality of (N) delay elements for delaying the signal change on the output of the gate element. A difference between a first delay provided by n-th delay section and a second delay provided by (n+1)th delay section is constant for any of n's between 1 and N−1. A plurality of variable delay sections are cascaded to form a frequency multiplier, with the output of the last stage variable delay section being fed-back to the input of the first stage variable delay section through a selector. The other input of the selector is connected to the input of the variable delay circuit to allow the internal signal to pass the variable delay sections for K times.

Abstract: A DLL (delay locked loop) circuit includes a signal propagation system and a delay control system. The signal propagation system includes a delay circuit which delays a reference clock signal based on a delay control signal to generate a delayed clock signal. The delay control system includes a sampling circuit, a phase comparing circuit and a delay control circuit. The sampling circuit outputs a first clock signal having a pulse corresponding to one of n (n is an integer more than 1) pulses of the delayed clock signal. The phase comparing circuit compares the first clock signal as a first comparison input signal and the reference clock signal as a second comparison input signal in phase to output a phase difference. The delay control circuit generates the delay control signal based on the phase difference from the phase comparing circuit to output to the delay circuit of the signal propagation system.

Abstract: A variable delay circuit generates a controlling clock signal by delaying a reference clock signal by a predetermined time. A dummy circuit delays the controlling clock signal by a predetermined time to generate a delayed clock signal. A phase comparator compares the delayed clock signal and the reference clock signal in phase. A delay control circuit adjusts the delay time of the variable delay circuit in accordance with a plurality of phase comparison results from the phase comparator, to have the delayed clock signal coincide with the reference clock signal in phase. Performing a single phase adjustment corresponding to a plurality of phase comparison results, prevents a delay in feeding back the controlling clock signal (delayed clock signal) transmitted through the dummy circuit to the phase comparator. This avoids extra operations of the delay control circuit and the variable delay circuit. Thus, jitter in the controlling clock signal is reduced.

Abstract: A signal processing circuit includes a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal and a leading edge of a feedback signal and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal. Because the first and second intermediate output signals are based on the phase difference between the reference signal and the leading and trailing edges of a feedback signal, respectively, and the first and second intermediate output signals are not derived from the reference signal, the jitter that may be introduced into the first and second intermediate output signals may be reduced.

Abstract: An internal clock generation circuit according to the present invention includes a phase comparator, a shift register, a filter, a monitor circuit, and a plurality of delay lines such as first and second delay lines. The first delay line has delay steps each larger than that of the second delay line. The first delay line is first used to generate a clock minimized in phase difference with respect to an external clock. The clock signal is inputted to the second delay line to perform fine adjustment to the phase difference.

Abstract: The present invention discloses an input buffer which can improve the properties of a setup time and a hold time of an input signal. When the setup time is important, a path of a short delay time is employed, and when the hold time is important, a path of a long delay time is used. Therefore, the internal setup time/hold time may be suitably selected in the system application conditions. For this, the input buffer includes: a buffer for receiving a signal through an input pin; a plurality of delay units for delaying the signal inputted from the buffer by a different delay time; and a selecting unit for selectively outputting one of the output signals from the plurality of delay units according to an externally-inputted reference signal and the logic variation of the input signal from the buffer.

Abstract: A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that delays a reference clock applied to its input by a plurality of respective delays. Two of the clock signals in the sequence are applied to a phase detector so that the signals at the outputs of the delay line have predetermined phases relative to each other. The outer delay-locked loop is formed by a voltage controlled delay circuit that delays the command clock by a voltage controlled delay to provide the reference clock to the delay line of the inner delay-locked loop. The outer delay-locked loop also includes a phase detector that compares the command clock to one of the clock signals in the sequence generated by the delay line. The outer delay-locked loop thus locks one of the clock signals in the sequence to the command clock.

Abstract: A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a delay in the first circuit, a delay control block for controlling an internal source potential based on the estimated delay for controlling the source potential for the second circuit so that the signal delay from the second circuit has small variations of delay time. The integrated circuit can be formed on a reasonable specification, and achieves a lower dissipation and a higher reliability.

Abstract: Balanced-delay programmable logic array and a method for balancing programmable logic array delays provide improved performance in circuits employing programmable logic. By adding transistors to the programming plane that do not form part of the logic implementation, the capacitance on each of the input logic lines can be balanced, substantially reducing the skew between signals entering the final logic gates. This provides programmable logic arrays that may implement asynchronous logic in applications where skew was previously prohibitive and further increases the reliability of state evaluations in synchronous logic.

Abstract: A signal processor connected to a charge-coupled device includes a plurality of delay lines with different delay times connected to a node on a signal line extending from the charge-coupled device to an output terminal of the signal processor, and a selector connected to the plurality of delay lines for selecting an optimum one of the plurality of delay lines. As a result, an effective signal time period of a time delay-free signal inputted into an input terminal of a selected one of the delay lines is superimposed with a field through time period of a delayed signal reciprocally transmitted through the selected one of the delay lines and returned to the input terminal of the selected one of the delay lines.

Abstract: In an integrated circuit, a system and method of programmably controlling the delay between a second clock signal with respect to a first clock signal after fabricating the integrated circuit. Prior to fabrication, a programmable delay group is formed and will be included in the integrated circuit. The programmable delay group includes a plurality of parallel coupled sets of delay stages. Each set having at least one delay stage. For the sets having more than one delay stage, the delay stages are serially coupled. After fabrication of the integrated circuit and in operation, the first clock signal is applied to one end of each of the sets of delay stages. The enable signals are generated and applied to the programmable delay group in order to enable one of the sets of delay stages. The enabled set delays the first clock signal, thereby producing the second clock signal at the other end of the enabled set and hereby controlling the delay of the second clock signal.

Abstract: A circuit and method configured to generate a variable impedance. The circuit may comprise a voltage controlled resistor configured to generate the variable impedance in response to (i) a first transistor configured to receive a first control signal and (ii) a bias transistor configured to receive a bias signal. In one example, the variable impedance may be generated in further response to a clamp transistor.

Abstract: A comparison circuit may be fabricated along with a primary circuit on a semiconductor substrate. The propagation delay of a comparison signal across a first path of circuit elements is compared to propagation delays of the comparison signal across a second path of delay elements. As a semiconductor fabrication process varies, the relative propagation delays across the first and second paths will vary in a manner correlative to the process variations. By monitoring the relative propagation delays, the fabrication process may be controlled to ensure that the process does not vary to an undesirable extent. Also, various programmable delay elements may be fabricated into the primary circuit, and these programmable delay elements may be activated and/or deactivated in response to the relative propagation delays of the comparison circuit.