Abstract: A delay line comprised of analog delay elements each having a selectively adjusted coarse and fine delay portion is described. The coarse delay portion receives an input clock signal and generates a ramp signal having a slope based on a predetermined coarse delay setting. The fine delay portion generates a threshold voltage based on a predetermined fine delay setting. A comparator compares the coarse delay ramp signal voltage with the fine delay threshold voltage and generates an output clock signal when the ramp signal voltage surpasses the fine delay threshold voltage. The coarse delay is linearly adjustable based on a 32-bit binary input signal and the fine delay is binary-weight adjusted based on a 5-bit binary input signal. Both the coarse and fine delay portions are controlled by delay line control circuitry which compares a feedback version of the output clock signal with the input clock signal and provides control signals to increment or decrement coarse and fine delay in the delay line.

Abstract: A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation where the gate and metal capacitance in a circuit vary independently across a process window. This is accomplished by regarding the inverting stage in a clock distribution system as a buildup mirror and applying the tracking principles of proportional composition. Loads are reflected through this mirror and resized by the buildup factor to extend Shoji balancing from just one process parameter setting to the entire process window.

Abstract: The system and methods describe a computer system implementing an adjustable control signal path whose length may be precisely adjusted to control timing of a control signal that propagates along the path. One such adjustable signal path has two clusters of possible signal paths. Each of the signal paths in each cluster has a length, and the overall length of the control signal path may be adjusted by selectively implementing one signal path from each of the clusters by electrically connecting that path into the electrical circuit by the selective installation of zero ohm resistors. In this way, a system designer may design several possible signal path lengths on to a motherboard or printed circuit card, and implement the path length which provides the most precise signal timing adjustment.

Abstract: A variable delay circuit comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements, according to a number of the first variable delay elements; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.

Abstract: An circuit and method for minimizing clock skew in an integrated circuit. The circuit is configured as a combination of delay elements and connection matrices that by connecting input and output pins in the connection matrix the circuit designer can select the required delay value. The connection matrices are defined in the circuit synthesis process as non routable areas therefore the programmable delay cells are programed after the circuit design is complete without requiring the circuit to be re routed. By inserting standard programmable delay cells in the clock tree the circuit designer can build in adjustable compensation for a wide range of clock skew.

Abstract: A delay system includes a first filter configured for receiving a selected input signal and a first mechanism for activating the first filter to produce a delayed output signal which is a function of a selected input signal. The delay system further includes a second filter configured for receiving a signal from said first filter to apply an additional delay to the signal received by said first filter, and a second mechanism for activating the second filter to produce a delayed signal which is a function of a signal received from the first filter. The delay system further comprises a divider system for tracking times from a clock reference. The delay system implements a method of delaying a received signal by sampling a selected signal with a predetermined clock signal and producing the selected signal at a time delayed to the extent of a comparison of a reduced frequency clock with a predetermined value.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i.e., the value of the current or capacitance) can be changed to achieve a desired amount of the delay applied to the input clock signal.

Abstract: A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.

Abstract: An electronic circuit and method for processing a signal, including a variable-delay transmission gate for receiving a binary input signal and propagating a delayed binary output signal corresponding to the input signal. The propagation delay in the transmission gate is controlled by two complimentary, non-binary, control signals from a current mirror that is driven by a PVT-compensated voltage follower.

Abstract: A phase adjustment circuit has a signal path having a plurality of phase adjustment elements coupled together. Each of the phase adjustment elements of the plurality has a first path and a second path. The second path of each of the phase adjustment elements of the plurality adds a smaller amount of phase adjustment to the signal path than the first path of each of the phase adjustment elements of the plurality. The amount of phase adjustment added by each of the phase adjustment elements of the plurality is cumulative. The phase adjustment circuit also has a selection circuit coupled to each of the phase adjustment elements of the plurality to provide selection of either the first path or the second path of each of the phase adjustment elements of the plurality.

Abstract: A delayed signal generation circuit comprises a first delay circuit having a plurality of delay elements connected in series, the first delay circuit delaying a reference signal applied thereto, a second delay circuit having a plurality of delay elements connected in series each of which sends out an output signal which is delayed with respect to an input signal applied to the second delay circuit, a detector unit, responsive to the reference signal applied to the first delay circuit, for detecting a number of delay elements of the first delay circuit which send out an output signal that is delayed with respect to the reference signal after a lapse of a predetermined time interval, and a selection unit for selecting one delay element from among the plurality of delay elements of the second delay circuit according to the number of delay elements of the first delay circuit which is detected by the detector unit, and for sending out the output signal from the selected delay element of the second delay circuit as

Abstract: A digital phase interpolator including a plurality of delay stages to control delay time of an output signal from first and second input signals having different phase delays. The plurality of delay stages are connected serially, have a same internal structure, determine corresponding axes for interpolation in each stage, and each includes a first inverting section for inverting first and second signal inputs from the previous stage, a phase blender for blending outputs of the first inverting section, a second inverting section for inverting outputs of the first inverting section, and a multiplexer for generating input signals for the next stage in response to a selection signal for determining phase delay time of the output signal of the phase interpolator. Total area and current may be reduced by the present invention because the number of inverters comprising each stage is equal.

Abstract: A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns.

Abstract: A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. In a first mode, the DLL circuit counts and stores a first number of delays necessary to synchronize the two signals. In some embodiments, the circuit also stores a second value representing the number of unit delays in one clock period. In a second mode, the DLL circuit uses the first stored value to add the correct number of unit delays to the input clock signal. In some embodiments, the second stored value is used to generate phased output signals.

Abstract: A method of controlling a clock signal in a clock distribution network, by detecting an error in a duty cycle of the clock signal, and dynamically adjusting the body voltage of one or more devices in the clock distribution network, based on the detected error. Where the electronic device is a p-type device, the adjustment may be performed by reducing the body voltage of the p-type device with respect to a supply voltage. Where the electronic device is an n-type device, the adjustment may be performed by increasing the body voltage of the n-type device with respect to a reference plane. The invention may be implemented digitally, that is, with the body voltage of the electronic device being adjusted by selectively connecting a body contact of the device to one of several discrete voltages using a multiplexer.

Abstract: An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

Abstract: A DLL circuit includes a delay line having a configuration with delay stages receiving alternate complementary clock signals ECK and /ECK having an adjusted phase difference therebetween. A capacitor can be used to adjust the phase difference between signals ECK and /ECK to allow the delay line to provide an amount of delay varying minutely. Preferably, for a fast clock, delay adjustment starts with a shift register having an initial value providing an intermediate amount of delay, and for a slow clock, delay adjustment starts with the shift register having an initial value providing a minimal amount of delay. There can be provided a semiconductor device provided with a DLL circuit accommodating a fast clock with reduced jitter.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: The timing circuit includes at least one delay element and its supply voltage is obtained from an active current source. The current source is a current mirror which is driven by a differential amplifier. The differential amplifier compares a voltage on the delay element supply line to a voltage on a current control node connected to a voltage controlled current source. An RC compensating circuit may be coupled to the current control node.

Abstract: A plurality of output circuits for supplying current are connected to an output terminal A of a pre-stage circuit. The output circuit, which connects to a switching timing delay mechanism including a delay circuit, performs switching at a timing when current reaches a saturation region. The current is supplied from the output circuit not including the switching timing delay mechanism. Hence, it is possible to keep the output impedance characteristics of an output terminal B constant and to readily realize impedance matching with load.

Abstract: A method compensates a phase delay of a clock signal used in a data communications system. First, a plurality of delayed clock signals are provided by modifying the amount of delay of the clock signal. In synchronization with one of the delayed clock signals, one or more test data signals and their address signals are sequentially issued and sent to a storage device. In synchronization with the original clock signal, each test data signal is stored in an area that its address signal indicates and then, upon receipt of the address signal at a predetermined time of the original clock signal, a data signal which corresponds to the address signal is read and sent to a controller. At a predetermined time of the delayed clock signal, a data signal is received from the storage device and it is checked whether or not each test data signal and the received data signal are the same.

Abstract: A programmable delay circuit (100) maximizes processor bandwidth to external peripherals by eliminating wait state addition as the only means to satisfy timing requirements. Circuit (100) includes a programmable delay chain (102) connected to a hysteresis circuit (150). A processor control signal is fed into the programmable delay chain (102) which includes at least one switch (104-116) and at least one resistive element (118-126) connected together. A first feedback circuit (128) connects the output of the programmable delay chain (102) to the input (IN2) of the first embodiment (100) to keep the falling edge of the control signal the same without any significant added delay. The hysteresis circuit (150) which provides a stable signal connects to an output driver (180) for driving the processor control signal.

Abstract: A delay stage used in a ring-type voltage-controlled oscillator has an inverter, a memory element, and tuning circuitry. The memory element is coupled to the output of the inverter to delay the time before the inverter's output begins to switch states in response to the inverter's input switching states. The tuning circuitry receives a control voltage and is coupled to the inverter to alter the strength of the inverter without altering the strength of the memory element. Altering the strength of the tuning circuitry alters the delay of the delay stage, and hence the frequency of the VCO's operation. Because the strength of the memory element is not altered, the speed at which the inverter's output switches remains substantially constant at all tuned frequencies. The switching speed is primarily dictated by the FT of the process.

Abstract: An object of the present invention is to simply and rapidly adjust a delay time of a delayed clock signal in accordance with a change in frequency of an input clock signal. The present invention comprises: a pulse generating circuit for generating a pulse signal PULSE with a trailing edge of an input clock signal as a reference; an inverter chain consisting of a plurality of inverters; a pair of inverter chains for sequentially delaying output signals from the pulse generating circuit; a plurality of NOR gates for adjusting a delay time of each inverter in the inverter chain; and a plurality of NAND gates for similarly adjusting a delay time of each inverter in the inverter chain. Since the delay time of the delayed clock signal in a next cycle is set based on the pulse signal generated based on a trailing edge of the input clock signal, even if a cycle of the input clock signal varies, the delay time of the delayed clock signal can be rapidly changed in accordance with this variation.

Abstract: A method and apparatus for stretching and/or shortening a clock cycle uses a multiplexor stage, in which a multiplexor switches between a normal clock signal and a delayed clock signal. Further, a method and apparatus for generating a plurality of stretched and/or shortened clock cycles uses a multiplexor stage in which a multiplexor successively switches between a normal clock signal and a plurality of delayed clock signals. Further, a method and apparatus for removing a clock cycle uses a multiplexor stage, in which a multiplexor switches between either a normal clock signal or a delayed clock signal and a grounded signal.

Abstract: In a semiconductor integrated circuit device, for realizing high speed, as well as superior product yield rate and usability, while reducing circuit scale and improving on product yield rate and reliability thereof, a main circuit, constructed with CMOS elements, is coupled to a speed monitor circuit for forming a speed signal corresponding to an operating speed thereof and to a substrate bias controller for supplying corresponding substrate bias voltages to the main circuit in response to the speed monitor circuit.

Abstract: A delay time control circuit controls delay times without a significant increase of power consumption or circuit components. The delay time control circuit for controlling delay times in a logic circuit includes a delay circuit having a plurality of serially connected gates which forms a ring oscillator by connecting a last gate to a first gate to create a closed loop, a pulse generator for generating a fixed pulse width signal every time when receiving an oscillation signal from the ring oscillator, an integrator which integrates an output signal of the pulse generator to produce an average voltage indicating a duty cycle of the output signal, and a delay time control voltage generator which compares the average voltage and a reference voltage indicating a delay time for the logic circuit and generates a voltage which is applied to the logic circuit.

Abstract: A timing generation circuit includes: a delay section including a plurality of delay circuits for sequentially transferring a clock signal therethrough, wherein the clock signal is delayed by a predetermined amount of time before being output from one of the plurality of delay circuits in the delay section; and a control circuit for changing a delay time of at least one of the plurality of delay circuits in the delay section in accordance with a frequency of the clock signal.

Abstract: In a delay circuit, a semiconductor integrated circuit device containing the delay circuit, and a delay method that are excellent for adding delay times onto input signals appropriately and accurately generating delay pulses and delay signals having predetermined delay times without requiring waveform modification or delay based on parasitic elements or the like, in the buffer section of a selecting switch section, a PMOS transistor and an NMOS transistor are connected to form an output terminal. The gates are connected to an individual delayed output terminal of a delay section. The PMOS transistor is connected in series to a PMOS transistor and to a power supply voltage. In the same way, the NMOS transistor is connected in series to an NMOS transistor and to a ground potential. A control signal is input to the gate of the PMOS transistor, while an inverted signal of the control signal is input to the gate of the NMOS transistor. A selecting section is formed by the transistors.

Abstract: The variable delay circuit has a delay circuit and a selector. The delay circuit is formed of a plurality of delay stages connected in cascade. The delay circuit receives an input signal at the initial delay stage and respectively outputs a delayed signal which is the input signal delayed, from the delay stages. The selector receives the delayed signals and selecting signals respectively corresponding to the delayed signals. The selector selects the delayed signal corresponding to an activated selecting signal and outputs the selected signal as a delayed output signal. The delay stage(s) subsequent to the delay stage outputting the delayed signal selected by the selector is/are inactivated. Not operating unnecessary delay stages can prevent wasteful power consumption.

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Abstract: A feedback controlled substrate bias generator having a substrate bias level sensing circuit, a charge pump circuit and an improved oscillator is disclosed. The substrate bias level sensing circuit is coupled to a semiconductor substrate for sensing a bias voltage of the semiconductor substrate and outputting a control signal in response to the sensed bias voltage. The charge pump circuit is coupled to the semiconductor substrate and the substrate bias level sensing circuit for receiving a clock pulse and the control signal and supplying the bias voltage to the semiconductor substrate in response to the received signals. The improved oscillator is coupled to the charge pump circuit for generating the clock pulse. The improved oscillator has a loop circuit having a plurality of serially and circularly coupled inverters each of which has a source terminal applied to voltage from a voltage source, an input terminal for receiving an input signal and an output terminal for outputting an output signal.

Abstract: A stable internal clock signal generator capable of suppressing an oscillation caused by a fluctuation in a power source or the like. A shift register 14 stores a binary comparison result indicating whether a phase obtained by a comparison carried out through a phase comparing circuit 13 past (n+1) times is advanced or delayed, a phase control circuit 15 outputs, as a phase control signal to a phase variable circuit 12, the larger number of comparison results obtained by carrying out the comparison (n+1) times, and the phase variable circuit 12 adjusts the phase of an internal clock signal intclk based on the input phase control signal.

Abstract: An electronic circuit and method for processing a signal, including a variable-delay transmission gate for receiving a binary input signal and propagating a delayed binary output signal corresponding to the input signal. The propagation delay in the transmission gate is controlled by two complimentary, non-binary, control signals front a current mirror that is driven by a PVT-compensated voltage follower.

Abstract: The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a “COMPARE” value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.

Abstract: A programmable delay in an AFE of an imaging system which can vary both the pulse position and the pulse width. The pulse width and position are controlled by providing separate programmable delay circuits for the rising and falling edges of the desired timing signal. Combining logic then combines the outputs of the two delay circuits to produce an output clock with separately delayed rising and falling edges.

Abstract: A programmable delay element having a fine delay circuit with fractional units of delay. The fine delay circuit has a fine delay circuit with a plurality of selectable delay paths, each delay path having an associated delay interval. The fine delay element is electrically-coupled to a data terminal for receiving and delaying an input signal. A control circuit is electrically-coupled to the fine delay circuit to select the delay path for the input signal. In a further aspect of the invention, the fine delay circuit is electrically-coupled to a coarse delay circuit having a plurality of selectable delay blocks in a repetitive block configuration. The coarse delay circuit is electrically-coupled to a second data terminal for receiving and inserting a second signal through said fine delay circuit. The control circuit is electrically-coupled to the selective delay path of the fine delay circuit and the coarse delay circuit such that either a fine delay, a coarse delay, or a coarse and a fine delay can be selected.

Abstract: The delay signal generating apparatus according to the present invention for outputting a delay signal obtained by delaying a reference signal includes: a phase shift device capable of outputting a plurality of shift signals having phases shifted from a phase of the reference signal by different shift amounts, respectively; and a shift signal selector capable of selecting one of the shift signals that has a phase shifted by a predetermined shift amount and outputting the selected shift signal.

Abstract: A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i.e., the value of the current or capacitance) can be changed to achieve a desired amount of the delay applied to the input clock signal.

Abstract: Circuitry that provides additional delay to early arriving signals such that all data signals arrive at a receiving latch with same path delay. The delay of a forwarded clock reference is also controlled such that the capturing clock edge will be optimally positioned near quadrature (depending on latch setup/hold requirements). The circuitry continuously adapts to data and clock path delay changes and digital filtering of phase measurements reduce errors brought on by jittering data edges. The circuitry utilizes only the minimum amount of delay necessary to achieve objective thereby limiting any unintended jitter. Particularly, this programmable differential delay circuit with fine delay adjustment is designed to allow the skew between ASICS to be minimized. This includes skew between data bits, between data bits and clocks as well as minimizing the overall skew in a channel between ASICS.

Abstract: A delay-locked loop circuit (DLL) includes a delay line with a delay which can be varied in a controlled manner to delay a periodic input signal having a period T, and a control circuit for controlling the delay line to lock the delay to the period T. The delay line supplies to the control circuit a plurality of periodic signals each delayed relative to the periodic input signal by a respective fraction of the delay. The control circuit includes a sequence-detector circuit which can periodically detect in the delayed signals characteristic sequences of digital values indicative of the delay. The control circuit can bring about a reduction or an increase in the delay for locking to the period T based upon the detected types of characteristic sequences.

Abstract: A method for dynamically selecting an input threshold on an input pin comprising the steps of (A) generating one or more control signals from a user selectable register and (B) selecting the input threshold from a plurality of thresholds in response to at least one of the control signals.

Abstract: A receiver circuit in a system for transferring data signals among integrated circuits or logic circuit blocks includes a receiving interface for allowing the data signal to be received at a correct timing. The receiving interface includes a detecting circuit for detecting whether or not a signal to be received has arrived at a detecting timing determined on the basis of a clock signal providing a timing base for signal receiving operation, a variable delay circuit inserted in a signal transfer path whose delay factor is controlled in dependence on the result of detection performed by the detecting circuit, and a flip-flop circuit for latching the signal outputted from the variable delay circuit in synchronism with the clock signal.

Abstract: In a synchronous delay circuit including a first delay circuit array which is constituted of a plurality of cascade-connected delay circuit stages, and a second delay circuit array which is constituted of a plurality of cascade-connected delay circuit stages arranged to have a signal propagating direction opposite to that of the first delay circuit array. Each of the delay circuit stages of the first and second delay circuit arrays includes a CMOS inverter receiving an input signal. A P-channel MOS transistor of the CMOS inverter, a switching P-channel MOS transistor and an additional resistor are connected in series between a power supply line and an output node of the delay circuit stage. An N-channel MOS transistor of the CMOS inverter, a switching N-channel MOS transistor and another additional resistor are connected in series between the ground and the output node of the delay circuit stage.

Abstract: A computer system having an Advance Configuration and Power Interface-compliant, or ACPI, operating system performs certain machine specific tasks before going to a low power state. When the computer operating system indicates that entry into the low power state is desired, a microcontroller embedded in an input/output chip is alerted. Synchronization between the main processor of the computer system and the embedded microcontroller of the ACPI operating system is achieved, reducing the likelihood of system failure on the next boot operation. The embedded microcontroller then also causes the state of devices connected to the input/output chip to be saved. This helps the machine to go to a known state during the resume process.

Abstract: A circuit and method for decreasing the amount of jitter present at the receiver input of high speed data links which uses a driver circuit for input from a high speed data link which comprises a logic circuit having a first section (1) which provides data latches, a second section (2) which provides a circuit generates a pre-destorted output and for compensating for level dependent jitter having an OR function element and a NOR function element each of which is coupled to two inputs and to a variable delay element as an input which provides a bi-modal delay for pulse width pre-distortion, a third section (3) which provides a muxing circuit, and a forth section (4) for clock distribution in the driver circuit. A fifth section is used for logic testing the driver circuit.

Abstract: A clock generator for automatic test equipment employs an improved technique for generating clock signals from a reference clock. To generate a desired clock signal, a clock generator produces a time-quantized signal having a period equal to an integer number of reference clock periods and equal to the desired clock period, plus or minus a quantization error. For each cycle of the desired clock signal, a noise-shaping requantizer processes the quantization error to generate noise-shaping signals. The noise-shaping signals then establish delay values of a variable pipeline delay. The variable pipeline delay adjusts each period of the time-quantized signal by an integer number of reference clock cycles, based upon the noise-shaped signals. The effect of noise shaping the quantization error and selectively delaying the time-quantized signal is to shift jitter in the time-quantized signal from relatively low frequencies to relatively high frequencies.

Abstract: A delay locked loop having improved synchronization times has a variably adjustable delay line which accepts two incoming clock pulses. As each pulse propagates through the delay line an edge of the pulse toggles or retoggles a shift bit corresponding to a delay element. When the first pulse reaches the end of the delay line, the status of the shift bits is frozen, and a starting point for a synchronization sequence begins at the transition point between toggled and retoggled shift bits.