Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

Abstract: An RF switch having an M number of FETs that are stacked in series and coupled between a first end node and a second end node wherein each of the M number of FETs has a gate is disclosed. A resistive network is coupled between a common mode (CM) node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal. Biasing circuitry coupled to the CM node is configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.

Abstract: A high-speed signal generator. A digital signal processing (DSP) block generates a set of N (where N is an integer and N?2) parallel digital sub-band signals, each digital sub-band signal having frequency components within a spectral range between 0 Hz and ±Fs/2. A respective Digital-to-Analog Converter (DAC) processes each digital sub-band signal to generate a corresponding analog sub-band signal, each DAC having a sample rate of Fs. A combiner combines the analog sub-band signals to generate an output analog signal having frequency components within a spectral range between 0 Hz and ±NFs/2.

Abstract: A differential TWE MZM includes a differential driver, first and second capacitors, and first and second terminations. The differential driver includes a first differential output and a second differential output that collectively form a differential pair. The first differential output is DC coupled to a cathode of a first arm optical phase shifter of a TWE MZM. The second differential output is DC coupled to a cathode of a second arm optical phase shifter of the TWE MZM. The first capacitor AC couples the second differential output to an anode of the first arm optical phase shifter. The second capacitor AC couples the first differential output to an anode of the second arm optical phase shifter. The first and second terminations are coupled to the cathode and the anode of, respectively, the first or second arm optical phase shifter.

Abstract: A squelch detector receives a first input signal, a second input signal, a first reference voltage and a second reference voltage. The first input signal and the second input signal are collaboratively defined as a differential input signal pair. The difference between the first reference voltage and the second reference voltage is defined as a squelch threshold. According to the squelch threshold, the squelch detector generates a detected signal to indicate whether the differential input signal pair is valid or not.

Abstract: A mixer includes a first node to which an intermediate frequency (IF) signal is input; first and second transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the first node; a first filter that is connected between the output terminal of the second transistor and the first node and suppresses passage of the IF signal; a second node to which the IF signal is input; third and fourth transistors that respectively have control terminals supplied with local signals having mutually opposite phases and output terminals connected to the second node; a second filter that is connected between the output terminal of the fourth transistor and the second node and suppresses passage of the IF signal; and a combiner combining a signal output from the first node and a signal output from the second node.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: A harmonic rejection mixer is disclosed that is capable of supporting wideband reception without any increase in circuit area. In this apparatus, transistors convert an RF signal to currents. Transistors perform frequency conversion based on the currents from the transistors and local oscillation signals. Transistors distribute the currents from the transistors to all transistors or some transistors based on a predetermined ratio. A load adds up the currents from the transistors and converts the resultant current to a voltage.

Abstract: Waveforms generators include a splitter that splits a digital input signal into a number of split signals each having a split signal frequency bandwidth that is substantially similar to a digital input signal frequency bandwidth. The split signals are mixed with associated digital, harmonic signals to generate a number of digital, mixed signals, which are then converted to analog signals at an effective sample rate that is different from a first order harmonic signal of at least one of the digital, harmonic mixers. A number of analog, harmonic mixers mix the associated analog signals with associated analog, harmonic signals to generate mixed, analog signals. The mixed, analog signals are combined into an output signal having an output signal bandwidth that is greater than a bandwidth of at least one of the number of DACs.

Abstract: A current generator includes first and second current generators and an output current generator. The first current generator has an output for providing a first current, the first current proportional to a difference between a first power supply voltage and a first gate-to-source voltage. The second current generator has an output for providing a second current, the second current proportional to a second gate-to-source voltage. The second gate-to-source voltage is approximately equal to the first gate-to-source voltage. The output current generator provides an output current proportional to a sum of said first current and said second current.

Abstract: A double balanced image reject mixer (IRM) can be configured to comprise: a common radio frequency (RF) port; four mixer devices, each comprising an intermediate frequency (IF) port, an RF port and an local oscillator (LO) port; and a four-way, in-phase splitter/combiner. The four-way, in-phase splitter/combiner can be connected between the RF common port and the RF port of each of the four mixer devices. A method of performing spurious suppression and image reject mixing in a double balanced IRM, can comprise: directly in-phase combining radio frequency (RF) output signals of four mixer devices located in the double balanced IRM; and phase pairing local oscillator (LO) signals and intermediate frequency (IF) signals such that the combination of the phases of the respective IF and LO signals can result in substantially equal phase RF signals at the RF ports of all four mixer devices.

Abstract: The present invention is a low-ripple power supply comprising a clock generator, a plurality of charge pump modules, and an adder unit. The low-ripple power supply inputs each of a plurality of clock signals generated by the clock generator into each of the plurality of charge pump modules. Since each of the plurality of charge pump modules sends the inputted corresponding clock signal into two paths to be inputted into the first and the second charge pump, respectively, and the corresponding clock signal inputted into the second charge pump undergoes an inversion by the inverter, by adding the first voltage outputted by the first charge pump and the second voltage outputted by the second charge pump, the ripples may be eliminated; finally, the adder unit adds the voltages outputted by each of the plurality of charge pump modules to yield a low-ripple DC voltage.

Abstract: A phasing adder and an ultrasound probe are disclosed. According to one implementation, the phasing adder includes a delay charge transferring unit and a delay adding unit. The delay charge transferring unit obtains signal charge in an amount obtained without amplifying according to charge generated in each of a plurality of piezoelectric elements. Each of the plurality of piezoelectric elements includes a piezoelectric body to generate charge according to sound pressure of input ultrasound. The delay charge transferring unit holds the signal charge for a predetermined amount of time. The delay adding unit executes phasing adding of an amount of the signal charge held for the predetermined amount of time in the delay charge transferring unit.

Abstract: A transconductance-enhancing passive frequency mixer comprises a transconductance amplification stage, a frequency mixing stage, and an output transresistance amplifier. The transconductance amplification stage has a pre-amplification transconductance-enhancing structure, so that the transconductance is greatly enhanced, thereby obtaining the same transconductance value at a lower bias current. A radio-frequency current is modulated by the frequency mixing stage to generate an output mid-frequency current signal. The mid-frequency current signal passes through the transresistance amplifier, to form voltage output, and finally obtain a mid-frequency voltage signal. The transresistance amplifier has a transconductance-enhancing structure, thereby further reducing input impedance, and improving current utilization efficiency and port isolation. The frequency mixer has the characteristics of low power consumption, high conversion gain, good port isolation, and the like.

Abstract: An apparatus of a Harmonic Rejection Mixer (HRM) for removing a harmonic component and an operating method thereof are provided. The HRM includes a Local Oscillator (LO), at least one frequency converter, at least two mixers, at least one phase converter, and a combiner. The LO generates an LO signal. The at least one frequency converter multiplies the LO signal using different variables to provide the same to at least two mixers. The at least two mixers convert a frequency band of an input signal using the LO signal provided from the LO and the at least one frequency converter. The at least one phase converter controls a phase of an output signal of at least one other mixer excluding one of the at least two mixers. The combiner combines an output signal of the one mixer with an output signal of the at least one phase converter.

Abstract: Waveforms generators include a splitter that splits a digital input signal into a number of split signals each having a split signal frequency bandwidth that is substantially similar to a digital input signal frequency bandwidth. The split signals are mixed with associated digital, harmonic signals to generate a number of digital, mixed signals, which are then converted to analog signals at an effective sample rate that is different from a first order harmonic signal of at least one of the digital, harmonic mixers. A number of analog, harmonic mixers mix the associated analog signals with associated analog, harmonic signals to generate mixed, analog signals. The mixed, analog signals are combined into an output signal having an output signal bandwidth that is greater than a bandwidth of at least one of the number of DACs.

Abstract: An adder circuit includes first through fourth two-bit adder modules, and first through third result mux blocks for receiving and adding first and second binary values to generate a final sum. A multiplier circuit that multiplies a multiplier and a multiplicand includes a multiplexer, an encoder connected to the multiplexer, a shifter connected to the encoder, and an accumulator connected to the encoder for receiving the multiplier and multiplicand and generating a multiplication product.

Abstract: A method, comprising: receiving a plurality of 2-tuples of asynchronously sampled inputs at an asynchronous to synchronous reconstructor; performing a coarse asynchronous to synchronous conversion using the plurality of 2-tuples to generate a plurality of low precision synchronous outputs; generating a high precision synchronous output, z0, using a plurality of asynchronous 2-tuples, low precision synchronous outputs after it, and its own high precision outputs from previous steps; calculating c0 and c?1 by summing future low precision outputs and the past high precision outputs after they are weighted with the appropriate windowed sinc. values and then subtracted from appropriate asynchronous samples; calculating, the four quantities “s?11”, “s01”, “s00” and “s?10” based on particular values of the windowed sinc. function; and using c0, c?1, s?11, s01, s00 and s?10, the high precision synchronous output of interest, z0 is generated.

Abstract: An improved approach to direction finding using a super delta monopulse beamformer is disclosed. A super delta channel signal that includes direction finding information from two circular delta channels is formed and output by the super delta monopulse beamformer. This super delta channel signal uses only two channels, but is able to realize the accuracy of conventional three channel systems.

Abstract: A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b).

Abstract: A circuit in which a storage function and an arithmetic function are combined is proposed by using a transistor with low off-state current for forming a storage element. When the transistor with low off-state current is used, electric charge can be held, for example, in a node or the like between a source or a drain of the transistor with low off-state current and a gate of another transistor. Thus, the node or the like between one of the source or the drain of the transistor with low off-state current and the gate of the another transistor can be used as a storage element. In addition, leakage current accompanied by the operation of an adder can be reduced considerably. Accordingly, a signal processing circuit consuming less power can be formed.

Abstract: A semiconductor device comprising a first inverter circuit including a first PMOS transistor and a first NMOS transistor, a drain electrode of the first PMOS transistor coupled to a drain electrode of the first NMOS transistor, and a second inverter circuit including a second PMOS transistor and a second NMOS transistor, a drain electrode of the second PMOS transistor coupled to a drain electrode of the second NMOS transistor. A first output voltage pad coupled to gate electrodes of the first and second PMOS and NMOS transistors, and between the drain electrode of the first PMOS transistor and the drain electrode of the NMOS transistor to self-bias the first inverter circuit. A second output voltage pad coupled between the drain electrode of the second PMOS transistor and the drain electrode of the second NMOS transistor.

Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.

Abstract: Embodiments of complementary biasing circuits and related methods are described herein. Other embodiments and related implementations are also disclosed herein.

Abstract: A circuit for digitizing a sum of a first input signal and a plurality of second input signals has a passive adder that sums the second input signals and outputs a summation signal and a multi-bit quantizer circuit. The quanitzer circuit compares the summation signal at a first comparator input with a signal at a second comparator input, which is derived from the first input signal and has an appropriate polarity so that the difference between the summation signal and the signal at the second comparator input is indicative of the sum of the first input signal and the plurality of second input signals. The comparator also produces a comparator output signal based on the sum of the first input signal and the plurality of second input signals. The quantizer circuit also has a control logic block for determining a multi-bit representation of the sum from the comparator output signal.

Abstract: According to one embodiment, there is provided a semiconductor device including a first amplifier and a second amplifier. The first amplifier has an input terminal to receive a first signal and an output terminal to output a second signal. The second amplifier is configured to receive the first signal and a correction data, to generate a correction signal according to the first signal and the correction data, and to output the generated correction signal to the output terminal of the first amplifier so as to add the first signal and the generated correction signal.

Abstract: A circuit for modulating an input signal including a dither signal generator configured to generate a first dither signal having a maximum amplitude, a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal, and a summer configured to sum the dither signal with the deamplified input signal.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: The invention, upon receiving an input signal, sums the absolute values of the difference of each pair of values adjacent to each other within a series of detected signal values to suppress the interference of low-frequency noise. Furthermore, the invention sums the absolute values of the moving averages of the differences of each pair of values adjacent to each other within a series of detected signal values to suppress both the interference of low-frequency noise and the interference of high-frequency noise. No synchronization with the input signal is necessary. The detection can be started at any phase of the input signal.

Abstract: A combined digital output system includes two quantization modules, a common mode counter, a differential mode counter, and a summing module. The quantization modules provide two digital signals, the common mode counter generates a common mode signal according to the digital signals, the differential mode counter generates a differential mode signal according to the two digital signals, and the summing module obtains the common mode signal and the differential mode signal, so as to generate a summing signal.

Abstract: A polar modulator for generating a polar-modulated signal based on amplitude information and phase information includes a phase-locked loop which is implemented to enable a setting of a frequency depending on a control value to obtain a phase-locked loop output signal. The polar modulator further includes a modulation means which is implemented to combine an amplitude modulation signal derived from the amplitude information with the phase-locked loop output signal to generate the polar-modulated signal. The polar modulator further includes a control value generator which is implemented to high-pass filter an amplitude signal derived from the amplitude information, to obtain a high-pass filtered amplitude signal, wherein the control value generator is implemented to combine the high-pass filtered amplitude signal with a phase signal based on the phase information to generate the control value signal representing the control value.

Abstract: The signal processing apparatus contains a first signal transforming circuit and a second signal transforming circuit. The first signal transforming circuit includes four first coupled lines and two second coupled lines, wherein two ends of each first coupled line are configured to carry a first pair of differential signals respectively, each second coupled line is magnetically coupled to two of the first coupled lines in parallel and comprises two signal ports, to which the two ends of each of the magnetically-coupled first coupled lines are placed symmetrically for transferring a second pair of differential signals. The second signal transforming circuit is configured to convert between the second pairs of differential signals at the signal ports and a third pair of differential signals at connecting ports of the second signal transforming circuit.

Abstract: In accordance with an embodiment, the coupling arrangement includes adders for adding a common-mode signal to a differential-mode signal and amplification units for individually and evenly amplifying input signals present on their input terminals, thereby yielding amplified common-and-differential-mode signals. Coupling units with capacitive coupling are configured to pass the amplified common-and-differential-mode signals towards a wire pair.

Abstract: A circuit for performing arithmetic operations includes a differential capacitive transimpedance amplifier (CTIA) and a cross-multiplexer. The cross multiplexer forwards the current to be integrated out of a plurality of current sources either to the positive input port of the differential CTIA for positive integration in direct mode or to the negative input port of the differential CTIA for negative integration in reverse mode.

Abstract: One embodiment of the invention relates to a communication system having an amplitude modulation path, a frequency deviation component, a characterization component, a peak cancellation component and a compensation unit. The amplitude modulation path is configured to provide an amplitude modulation signal. The frequency deviation component is configured to generate a frequency deviation signal. The characterization component is configured to generate characterization coefficients according to the amplitude modulation signal and the frequency deviation signal. The peak cancellation component is configured to identify peaks according to the amplitude modulation signal and generate a peak cancellation signal to compensate for peak distortion by the identified peaks.

Abstract: The present application describes an apparatus and method for improving the performance of ?? modulators functioning as ADCs. In one embodiment, the ?? modulator comprises a plurality of quantizers operating in a round-robin fashion, rather than the single quantizer of the prior art. The use of multiple quantizers allows the ?? modulator to appear to be functioning at a significantly higher rate than a single quantizer allows. In another embodiment, a second-order ?? modulator contains a plurality of control loops, rather than the single control loop of the prior art. The use of multiple control loops allows the ?? modulator to have multiple points of maximum signal-to-noise ratio rather than a single such point as in prior art ?? modulators.

Abstract: A sampling circuit and a receiver with which filter characteristics compatible with the reception of wideband signals can be realized with a high degree of freedom in the setting of the filter characteristics. More specifically, the sampling circuit is capable of removing adjacent interfering wave signals while keeping in-band deviation small. The sampling circuit is equipped with a discrete-time analog processing circuit group, wherein multiple discrete-time analog processing circuits are connected in parallel, a synthesizer that synthesizes the output signals from each of the circuit systems and outputs same, and a digital control unit that outputs control signals. Each of the discrete-time analog processing circuits is configured to include multiple rotate capacitor units, which each includes a main rotate capacitor and a sub-rotate capacitor, and only the main rotate capacitors share electric charge with a buffer capacitor included in the synthesizer.

Abstract: An apparatus and method for splitting a wide band input signal and overlaying multiple frequency bands on each path associated with one or more digitizers. All frequencies from the split signal on each path can be fed to a mixer. The local oscillator of each mixer receives a sum of signals, which can each be set to any arbitrary frequency, as long as an associated matrix determinant of coefficients is non-zero. Each oscillator signal is multiplied by a coefficient, which can represent phase and magnitude, prior to summing the oscillator signals together. Each mixer mixes a combined signal with the input, thereby generating a set of multiple overlaid frequency bands. The digitized signals are processed to substantially reconstruct the original input signal. Thus, the wide band input signal is digitized using multiple individual digitizers. In particular, a system can support two wide band signals using four digitizers of narrower bandwidth.

Abstract: Apparatus and methods provide a differential current buffer. The current buffer has cross-coupled feedback and offers relatively good common-mode rejection and a relatively low and linear input impedance, which can reduce intermodulation distortion. The current buffer can be used in, for example, an RF modulator, such as a quadrature modulator.

Abstract: There is provided a transmitter with a small area and low noise. A direct RF modulation transmitter is constituted by an N-number of input signal delay-attached direct RF converters to which an I digital baseband signal is input, an M-number of input signal delay circuit-attached direct RF converters (DDRCs) to which a Q digital baseband signal is input, a Divide-by-2 divider for generating a differential local signal differing in phase by 90 degrees, an output matching circuit, and a delay control circuit for controlling an input data delay amount for the DDRCs. This transmitter sets delay amounts for the DDRCs using the delay control circuit independently. Particularly when N is set to equal M and the same amount of delay is set for N-number of converters corresponding to the I digital baseband signal and the Q digital baseband signal, noise reduction effect in a predetermined frequency band is heightened.

Abstract: Provided are a direct sampling circuit and a receiver using a discrete time analog process and having a filter effect of a steep attenuation characteristic in a narrow-pass band without lowering a sampling rate. In a discrete time direct sampling circuit (13), the positive phase side and the inverse phase side are both sampled by a local signal for a differential current output of a differential voltage/current conversion unit (1011) and electric charge is accumulated in a charge sampling capacitor. The latest accumulated charge at the positive phase side and charge accumulated at the inverse phase side before a predetermined number of samples are combined with the charge accumulated in a history capacitor (1043) in the past. Thus, it is possible to realize equivalently high-degree FIR filter characteristic.

Abstract: Embodiments of RF and DC switching are described generally herein. Other embodiments may be described and claimed.

Abstract: Apparatus and methods reduce common-mode error. An integrated circuit includes a plurality of signal channels, a first proxy channel, and a subtraction block. The signal channels are configured to receive a plurality of input signals and to generate a plurality of output signals, and each of the signal channels has a substantially similar circuit topology. The first proxy channel has a substantially similar circuit topology as the plurality of signal channels, and includes an output that can vary in relation to a common-mode error of the signal channels. The subtraction block is configured to generate a plurality of modified output signals by using the output of the first proxy channel to reduce the common-mode error of the plurality of output signal channels.

Abstract: A time difference adder included in a system-on-chip (SOC) includes a first register unit and a second register unit. The first register unit is configured to receive first and second input signals having a first time difference, and generate a first output signal in response to a first signal. The second register unit is configured to receive third and fourth input signals having a second time difference, and generate a second output signal having a third time difference with respect to the first output signal in response to the first signal. The third time difference corresponds to a sum of the first time difference and the second time difference.

Abstract: The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular. This signal reproducing device (1) includes: N FETs (61 to 6N) each receiving a common input signal (VIN) at a gate terminal and having a bias voltage (VDD) applied to a drain terminal; and an adder circuit (4) connected to source terminals of the FETs (61 to 6N), for combining currents between the drain terminals and the source terminals of the FETs (61 to 6N) and outputting the resulting current, wherein the FETs (61 to 6N) and the bias voltage (VDD) are set so that a voltage at the gate terminal having the common input signal (VIN) applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the FETs (61 to 6N).

Abstract: A method is provided for improving clock recovery signal jitter in digital communication based on a phase adjustment technique in a phase interpolation. A clock signal is expressed as the combination of two sinusoidal signals. The phase interpolating process determines the amplitude of the first sinusoidal signal, and the amplitude of the second sinusoidal signal that is 90° out of phase from the first sinusoidal signal. The clock signal is then formed by combining first sinusoidal signal with the second sinusoidal signal by choosing the first and second amplitude such that the amplitude of the clock signal is substantially a constant. Modulation of the clock signal amplitude is significantly improved by the disclosed technique over the conventional technique when the sum of the first and second amplitudes of the two sinusoidal functions is kept a constant.

Abstract: An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.

Abstract: This disclosure is directed to techniques for decoding two or more signals that vary sinusoidally with respect to a parameter value to produce a decoded signal that varies linearly with respect to the parameter value. The techniques may include receiving a first signal and a second signal, the first signal varying with respect to a parameter value according to a first sinusoidal function having a period and a first phase, the second signal varying with respect to the parameter value according to a second sinusoidal function having the period and a second phase different from the first phase. The techniques may further include performing one or more arithmetic operations using the first signal, the second signal, and an offset value to generate a third signal that varies linearly with respect to the parameter value for at least one-half of the period of the first signal and the second signal.

Abstract: A combined digital output system includes two quantization modules, a common mode counter, a differential mode counter, and a summing module. The quantization modules provide two digital signals, the common mode counter generates a common mode signal according to the digital signals, the differential mode counter generates a differential mode signal according to the two digital signals, and the summing module obtains the common mode signal and the differential mode signal, so as to generate a summing signal.

Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.