Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.

Abstract: A signal converting circuit includes: a first single-to-differential circuit arranged to generate a first signal having a first polarity and a second signal having a second polarity different from the first polarity; a second single-to-differential circuit arranged to generate a third signal having the second polarity and a fourth signal having the first polarity; and a combining circuit arranged to generate a first combined signal having the first polarity according at least two signals from the first signal, the second signal, the third signal, and the fourth signal, and output an output signal according to at least the first combined signal.

Abstract: Various embodiments of systems and methods for generating local oscillator (LO) signals for a harmonic rejection mixer are provided. One embodiment is a system for generating local oscillator (LO) signals for a harmonic rejection mixer. One such system comprises a local oscillator, a divide-by-N frequency divider, a divide-by-three frequency divider, and a harmonic rejection mixer. The local oscillator is configured to provide a reference frequency signal. The divide-by-N frequency divider is configured to divide the reference frequency signal by a value N and provide an output signal. The divide-by-three frequency divider is configured to receive the output signal of the divide-by-N frequency divider and divide the output signal into three phase-offset signals. The harmonic rejection mixer is configured to receive the three phase-offset signals and eliminate third frequency harmonics.

Abstract: A distributed weighting network that employs a summing line including distributed summing blocks disposed thereon. Each summing block includes a plurality of resistors that define a resistor divider network. Each summing block includes at least three ports having an input port, an output port and at least one signal port. A signal applied to each signal port of the summing blocks is modified in amplitude by the resistor divider network and summed with the signal propagating along the summing line being input to the input port and output from the output port of each summing block to provide a combined signal. The distributed weighting network can be part of a digital-to-analog converter or a QAM modulator.

Abstract: A sampling mixer includes TAs (transconductance amplifiers), an in-phase mixer section connected to the TA and the TA, an opposite-phase mixer section connected in parallel with the in-phase mixer section, and a signal generator for generating a control signal for the in-phase mixer section and the opposite-phase mixer section respectively. The IIR filter using signals that underwent a current conversion by using the different transconductances is constructed, so that the filter characteristic can be designed by a weighting of the transconductance in addition to a capacitance ratio. As a result, the wide-band filter characteristic and the band-pass filter characteristic can be obtained, and deterioration of the receiving sensitivity can be suppressed by designing the filter characteristic suitable for the radio communication system.

Abstract: A filter circuit is constructed of a passive mixer and a frequency response device. The passive mixer generates a frequency-converted signal by mixing an input signal transmitted through a transmission line and a local oscillation signal, and outputs the frequency-converted signal to the frequency response device, thus shifting a frequency characteristic of the frequency response device to high frequency by a local oscillation frequency of the local oscillation signal and applying the frequency characteristic shifted to high frequency on the input signal.

Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.

Abstract: Embodiments of RF and DC switching are described generally herein. Other embodiments may be described and claimed.

Abstract: A noise generator for generating band-limited noise from a plurality of sinusoidal signals at the same level and equidistant frequency position in the noise spectrum is provided. A noise signal has a low crest factor and for this purpose the phase position of each individual sinusoidal signal is determined.

Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.

Abstract: A driver circuit includes a plurality of delay circuits and an inverter. The plurality of delay circuits delay branched driving signals. The inverter inverts at least one of the branched driving signals. At least one of the plurality of delay circuits is at least one variable delay circuit delaying a variable amount of delay. The output driving signal is output by combining the inverted signal of the branched driving signal output via at least one inverter and at least one non-inverted signal of the branched driving signals output from the delay circuits.

Abstract: A driver circuit includes a main driver which receives an input signal and outputs a first signal corresponding to the input signal, a sub driver which receives the input signal and outputs a non-inverted signal and an inverted signal corresponding to the input signal, a differentiating circuit including resistors and a variable capacity condenser, which outputs signals by differentiating the non-inverted signal and the inverted signal, respectively, and an addition unit which outputs a high frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the non-inverted signal, or a low frequency emphasized signal given by adding the output signal of the main driver and the signal given by differentiating the inverted signal.

Abstract: In one embodiment, a method includes generating, by a LCVCO, a first signal having a first phase based on a resonant frequency of a first LC tank; generating, by a second LCVCO, a second periodic signal having a second phase based on a resonant frequency of a second LC tank; determining a phase offset between the first LC tank and the second LC tank based on the first and second signals; generating a first output signal and a second output signal based on the determined phase offset; and adjusting the phase offset such that the phase offset is substantially equal to a predetermined phase offset. In one embodiment, the adjusting comprises modulating a first impedance of the first LC tank based on the first output signal, and/or modulating a second impedance of the second LC tank based on the second output signal.

Abstract: The present invention is intended to achieve a transconductance amplifier and a voltage/current converting method which can provide a sufficient amplitude and a high degree of design freedom. The method comprises the steps of converting a first voltage signal to a first current signal; converting a second voltage signal to a second current signal; obtaining the common-mode components of the first and second current signals; and subtracting the common-mode components from the first and second current signals to obtain third and fourth signals, and further, subtracting the fourth current signal from the third current signal to generate a first output, while subtracting the third current signal from the fourth current signal to generate a second output.

Abstract: According to one embodiment of the invention, a summing circuit comprises a first transmitter, a second transmitter, a first current offset circuit and a first transconductance amplifier. The first current offset circuit is coupled to the emitters of the first and second transistors. The first transconductance amplifier is coupled to the first current offset circuit.

Abstract: Provided is an output apparatus that outputs an output signal corresponding to an input signal, comprising a plurality of drivers that each output an intermediate signal having a waveform corresponding to the input signal; an adding section that adds together the intermediate signals output from the drivers and outputs the result as the output signal; and a control section that controls a difference in delay amount, which is from when the input signal begins to change to when the intermediate signal begins to change, among the drivers according to a designated slew rate.

Abstract: A heterodyne dual-slope frequency generation method for the load change of the power supply, which comprises a power transformer, a feedback control circuit, and a dual-slope charge-discharge circuit. The power supply generates different charge current to fit different operating mode through the feedback control circuit, feedback voltage generated into power transformer, and passes through the dual-slope charge-discharge circuit in accordance with the different outer load device and the different outer voltage rising speed. When the outer loading is changed, the feedback control circuit detects error voltage, feeds through power transformer, further changes the supplied current, and finally automatically adjusts the driving current and the output power.

Abstract: A first mixer circuit mixes a first center frequency signal with a first local oscillation signal to generate a second mixed signal, and mixes the first center frequency signal with a second local oscillation signal to generate a first mixed signal, and a second mixer circuit mixes a second center frequency signal with the first local oscillation signal to generate a fourth mixed signal, and mixes the second center frequency signal with the second local oscillation signal to generate a third mixed signal. An adder and subtracter circuit subtracts the third mixed signal from the second mixed signal to output a signal of subtraction result as a first upper side band signal, and adds the first mixed signal to the fourth mixed signal to output a signal of addition result as a second upper side band signal different in phase from the first upper side band signal by 90 degrees.

Abstract: A bias-shaping circuit for adjusting power consumption in a frequency divider to a temperature-dependent minimum includes a temperature-dependent bias source for producing a temperature-dependent bias. The bias is combined with an input signal to create an output bias. The output bias changes in response to a change in temperature to compensate for at least a portion of a temperature-induced change in the frequency divider, thereby adjusting power consumption in the frequency divider to a temperature-dependent minimum.

Abstract: A power limiting circuit includes: a maximum value prediction filter section (MVPFS) interpolating data of one branched digital input signal; a maximum value detection section detecting maximum value of an output of the MVPFS and a time detection position thereof every constant period; a threshold subtraction section subtracting a threshold from detected maximum value and outputting a peak signal (zero when the subtraction result is negative); a coefficient selection section weighting the peak signal according to time detection position; a complex filter section limiting the weighted peak signal within a band of the input signal; a filter coefficient calculation section calculating filter coefficients of the complex filter section; a delay adjustment section delaying another of the branched input signals by a time period required for calculating the band-limited peak signal; and a subtraction section subtracting the band-limited peak signal from the other of the branched input signals subjected to delay.

Abstract: To provide an adder capable of obtaining an addition signal of a plurality of high frequency signals, and also a power combiner, a quadrature modulator, a quadrature demodulator, a power amplifier, a transmitter, and a wireless communicator, each of which uses the adder. Impedances (Zg, Zh) seen from a common output point (P3) of a plurality of first impedance circuits (110a, 110b) toward respective input terminals (102a, 102b) are set so that high frequency currents (Ig, Ih) are approximately zero. An impedance (Zs) seen from a first connection point (P1) toward the input terminals (102a, 102b) is set so that a high frequency current (Is) is approximately zero. An impedance (Zc) seen from the first connection point (P1) toward a circuit (150) is set so that a high frequency current (Ic) is approximately zero. An impedance (Zm) seen from a second connection point (P2) toward a power supply is set so that a high frequency current (Im) is approximately zero.

Abstract: A differential signal generation circuit includes: an inverter array configured to sequentially invert an input signal to generate a plurality of delayed signals; and a phase mixer configured to mix a phase of a first delayed signal and a phase of a second delayed signal among the plurality of delayed signals at a preset mixing ratio to generate a first differential signal. The first delayed signal has a first delay from the input signal and the second delayed signal has a second delay from the input signal. The differential signal generation circuit is configured to generate a third delayed signal having a third delay from the input signal corresponding to a medium of the first and second delays, and the third delayed signal is further delayed to generate a second differential signal.

Abstract: A radio frequency (RF) circuit includes a power supply configured to generate a plurality of voltages, a plurality of power amplifiers, each having an RF output port and a power supply input port, a switch network having a plurality of input ports coupled to the power supply and a plurality of switch network output ports coupled to the power supply input ports of the plurality of power amplifiers, wherein the switch network is configured to output selected ones of the plurality of voltages from the plurality of switch network output ports, at least two of the switch network output port voltages capable of being different ones of the plurality of voltages, and an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit.

Abstract: A radio frequency (RF) modulator includes: converting means for up-converting a first and second baseband signals into a first and second up-converted signals with a reference clock, wherein a phase difference between the first and second baseband signals substantially equals 180°/N; and combining means for combining the first and second up-converted signals to generate an output signal.

Abstract: A peaking circuit according to the present invention includes amplifiers connected in multiple stages and feedback circuits for feedback to an input from two or more output points with different gains as seen from the input. The peaking circuit is configured to be able to change an amount of feedback of the feedback circuits.

Abstract: A signal converting circuit includes: a first single-to-differential circuit arranged to generate a first signal having a first polarization and a second signal having a second polarization different from the first polarization; a second single-to-differential circuit arranged to generate a third signal having the second polarization and a fourth signal having the first polarization; and a combining circuit arranged to generate a first combined signal having the first polarization according at least two signals from the first signal, the second signal, the third signal, and the fourth signal, and output an output signal according to at least the first combined signal.

Abstract: A sampling mixer includes TAs (transconductance amplifiers), an in-phase mixer section connected to the TA and the TA, an opposite-phase mixer section connected in parallel with the in-phase mixer section, and a signal generator for generating a control signal for the in-phase mixer section and the opposite-phase mixer section respectively. The IIR filter using signals that underwent a current conversion by using the different transconductances is constructed, so that the filter characteristic can be designed by a weighting of the transconductance in addition to a capacitance ratio. As a result, the wide-band filter characteristic and the band-pass filter characteristic can be obtained, and deterioration of the receiving sensitivity can be suppressed by designing the filter characteristic suitable for the radio communication system.

Abstract: A method for modifying a characteristic of a representation of a complex-valued signal which comprises at least a representation of a first and a second complex-valued symbol comprising deriving a relative phase angle between the representation of the first and the second complex-valued symbols. The method further comprises combining a representation of a complex-valued enhancement pulse and the representation of the complex-valued signal to obtain a representation of a first and a second corrected complex-valued symbol, wherein the enhancement pulse is chosen such that the relative phase angle between the first and second corrected symbols is smaller than a predetermined threshold.

Abstract: A single sideband mixer circuit includes a voltage controlled oscillator operable a tunable frequency f1. The mixer circuit outputs a frequency signal at a frequency f1±f2. A tracking filter operates to filter the frequency signal and generate a first output signal at the frequency f1±f2. A resonance frequency fr of the tracking filter is tunable to substantially match the frequency f1±f2 of the frequency signal. The output signal of the tracking filter may be processed by a phase lock loop circuit to generate a control signal for controlling the setting of the tunable frequency f1 and resonance frequency fr. Alternatively, the output signal of the tracking filter may be divided and the divided signal processed by a phase lock loop circuit to generate the control signal for controlling setting of the tunable frequency f1 and resonance frequency fr.

Abstract: A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.

Abstract: To provide a power amplification device that can amplify an input signal having an envelope variation with high power-added efficiency in a wide frequency range, and a transmission device and a communication device using the power amplification device. A first orthogonal signal (Sd1) is generated by performing vector subtraction between first and second fundamental signals (Su1 and Su2) having the same amplitude and a phase difference ?? (0 degrees<??<180 degrees) therebetween. First and second fundamental signals are generated based on an input signal (Sin). A second orthogonal signal (Sd2) is generated by performing vector addition between the first and second fundamental signals (Su1 and Su2). First and second constant envelope signals (S1 and S2) are generated by performing vector addition between the second fundamental signal (Su2) and first and second constant envelope vector generation signals (e and ?e) obtained based on the first fundamental signal (Su1).

Abstract: Provided is a power voltage forming device which can correct an offset voltage of a high-frequency power amplifier without degrading distortion characteristic of a high-frequency power amplifier. The power voltage forming device (100) includes: a level adjusting unit (103) which adjusts the level of input data subjected to analog conversion, according to an output level control value for controlling the output level of the high-frequency power amplifier (200); an analog adder (104) which performs analog addition of the offset data subjected to the analog conversion, to the signal after the level adjustment; a digital adder (101) which performs digital addition of the offset data to the input data before the analog conversion; and a selection unit (106) which selects whether to perform addition by the analog adder (104) or addition by the digital adder (101) according to the output level control value.

Abstract: A harmonic rejection mixer includes a differential in-phase signal path and a differential quadrature signal path, a shared differential transconductor for generating a shared transconductor output signal from a mixer input signal, a first selective mixing circuit disposed in the differential quadrature signal path and coupled to the shared differential transconductor, and a second selective mixing circuit disposed in the differential in-phase signal path and coupled to the shared differential transconductor, the first selective mixing circuit is controlled by a first selective control signal and the second selective mixing circuit is controlled by a second selective control signal to selectively supply the shared transconductor output signal to the differential quadrature signal path and the differential in-phase signal path, respectively.

Abstract: A frequency conversion circuit configured to mix a first input signal (RF+,RF?) at a first frequency with a second input signal (LO+,LO?) at a second frequency to provide an output intermediate frequency signal (IFout), the circuit comprising: first and second mixing modules , each mixing module comprising a voltage to current converter configured to receive the first input signal (RF+,RF?) and connected to a Gilbert mixer configured to receive the second input signal (LO+,LO?); an intermediate frequency output circuit having inputs connected to receive an intermediate frequency current signal (IF+,IF?) from outputs of each of the Gilbert mixers and an output configured to provide the output intermediate frequency voltage signal (IFout), wherein the first and second mixing modules comprise transistors which are complementary to each other.

Abstract: A charge domain filter circuit includes a first signal output portion, at least one second signal output, portion, a third signal output portion, and an adder portion. The first signal output portion outputs a first signal that is sampled at a specified time interval. Each second signal, output portion outputs a second signal that is sampled after a specified delay after the first signal is sampled. Where a plurality of the second signal output portions is included, the second signals are sampled in succession. The third signal output portion outputs a third signal that is sampled after a specified delay after the last second signal is sampled. The adder portion adds the first, second, and third signals together and outputs the result. The capacitance ratio of the sampling capacitors in the first signal output portion and the second signal output portion is one of continuously or discretely varied.

Abstract: Provided is an information processing apparatus which includes a first module including a signal addition unit that generates an addition signal by adding a data signal to a clock, a signal subtraction unit that generates a subtraction signal by subtracting the data signal from the clock, a first signal transmission unit that transmits the addition signal through a first transmission line, and a second signal transmission unit that transmits the subtraction signal through a second transmission line, and a second module including a data component extraction unit that extracts a component of the data signal by subtracting the subtraction signal received through the second transmission line from the addition signal received through the first transmission line, and a clock component extraction unit that extracts a component of the clock by adding the subtraction signal received through the second transmission line to the addition signal received through the first transmission line.

Abstract: A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal.

Abstract: In a case where two constant envelope signals corresponding to an input signal are generated through analog signal processing, variation in detection sensitivities of amplitudes of those signals is suppressed. At least one of a mixer (24) for detecting an amplitude of a first intermediate signal S1 and a mixer (26) for detecting an amplitude of a second intermediate signal S2 detects an amplitude of a given reference signal, and sampling hold circuits (36, 38) hold a voltage related to those amplitudes. Then, detection sensitivities of the mixer (24, 26) are corrected based on the held voltage.

Abstract: An output device includes a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal, and a controller. The noise driver (i) sets an output end thereof at high impedance when not supplied with an enable signal, and (ii) varies an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The controller controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched.

Abstract: A circuit arrangement for signal mixing. One embodiment provides a circuit arrangement for mixing an input signal with at least one carrier signal. The circuit arrangement includes a current source and a current sink. The current source and the current sink have a mixer core coupled between them which provides cross-coupling between mixer input connections and mixer output connections.

Abstract: A variable transconductance device for a mixer apparatus is provided. The apparatus includes at least one variable current source circuit having a plurality of selectively enabled current source stages. Each of the current source stages, when enabled, is actuable to establish a conductive path between a first supply level and an output terminal. The device further includes at least one variable transconductance circuit having a plurality of selectively enabled transconductance stages. Each transconductance stage, when enabled, is actuable to establish a conductive path between a second supply level and the output terminal. An output current signal is generated at the output terminal responsive to actuation of the variable transconductance circuit by an input voltage signal, whereby the output current signal exhibits a power gain adjustably determined responsive to the numbers of current source and transconductance stages selectively enabled.

Abstract: Systems and methods for digital upconversion of digital signals are provided. In one embodiment, the system includes a digital frequency adjustment system and a digital to analog conversion system. In a feature of the embodiment, the digital frequency adjustment system consists of set of digital upconversion and upsample elements that shift upwards the frequency of baseband signals. In a further feature of the embodiment, a tree structure of sets of upsample and upconversion elements is used. In another embodiment, the system includes digital and analog frequency adjustment systems in which the frequencies of the input signals are partially upshifted within both the digital and analog domains. Methods for digital upconversion of digital signals are also provided.

Abstract: A harmonic rejection mixer unit is provided which comprises an input (RF), at least one harmonic rejection unit (HRU) with at least two transistor units (T3a, T3b; T4a, T4b) for multiplying an input signal from the input (RF) with a multiplication signal (ELO). The harmonic rejection mixer unit furthermore comprises a transistor control signal generating unit (GGU) for generating transistor control signals (GS1-GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) of the at least one harmonic rejection unit (HRU) by deriving the transistor control signals (GS1-GS4) from a local oscillator signal (LO). The transistor control signals (GS3, GS4) for the at least two transistor units (T3a, T3b; T4a, T4b) are generated with a duty cycle of <50% and are generated such that the shape of the multiplication signal ELO) is achieved by a constructive summation of the output signals from the transistor units (T3a, T3b; T4a, T4b).

Abstract: A mixer device includes a differential circuit, a transconductance circuit, and a selecting circuit. The differential circuit receives a differential input signal and generates a differential output signal. The transconductance circuit is coupled to the differential circuit, receives a plurality of radio frequency input signals, and determines to mix at least one of the radio frequency input signals with the differential input signal according to an enable signal. The selecting circuit receives a control signal and generates the enable signal according to the control signal.

Abstract: An adjustable chaotic signal generator using pulse modulation for UWB communications, and a chaotic signal generating method thereof are provided. The chaotic signal generator for UWB communications includes a plurality of pulse generators which generates pulses of different frequencies; at least one combiner which combines the pulses generated at the pulse generators; and a plurality of local oscillators which receives signals from the combiner, respectively, and generates a chaotic signal by increasing the received signals to different frequency bands. Accordingly, a plurality of users can conduct the radio communications in a specific wireless communication range at the same time by generating the chaotic signal that can be split to the multiple channels. Also, the chaotic signal generator is structured using devices integratable on an integrated circuit.

Abstract: According to one embodiment of the invention, a programmable finite impulse response (FIR) filter is implemented with differential isolation circuits to isolate parasitic capacitance from attenuating an output signal at both a first and second differential output terminals of the FIR filter. The FIR includes a summing circuit that provides operational advantages to the FIR filter.

Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.

Abstract: Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.

Abstract: A mixer circuit designed for low voltage operation with rail-to-rail local signals. First and second transistors form a first input section to produce a first signal. Third and fourth transistors form a second input section to produce a second signal. Fifth and sixth transistors form a third input section to produce a third signal. Seventh and eighth transistors form a fourth input section to produce a fourth signal. A differential RF input signal drives the first, third, fifth, and seventh transistors, while a differential local signal drives the second, fourth, sixth, and eighth transistors. Ninth and tenth transistors form a positive output section to produce a non-inverted output signal. Eleventh and twelfth transistors form a negative output section to produce an inverted output signal. The ninth to twelfth transistors are driven by the first to fourth signals, respectively.

Abstract: A voltage generating circuit including first and second voltage sources, and a subtracting circuit. The subtraction circuit is configured as a differential amplifier including an op-amp and four resistors, with an inverting input terminal of the op-amp connected to the second voltage source via a first resistor, a second resistor connected between the inverting input terminal and an output terminal of the op-amp, a non-inverting input terminal of the op-amp connected to the first voltage source via a third resistor of the same size as the second resistor, the non-inverting input terminal of the op-amp connected to a reference potential terminal via a fourth resistor of the same size as the first resistor, the first voltage from the first voltage source and the second voltage from the second voltage source inputted to the subtracting circuit, and the subtracting circuit outputting a third voltage having a positive temperature coefficient.