Abstract: A frequency converter converts a first current signal having a first frequency into a second current signal having a second frequency different fro the first frequency. The frequency converter includes an adder and a switching circuit. The adder adds the first current signal and a reference current signal to output a third current signal. The switching circuit passes only that portion of the third current signal larger in magnitude than a threshold current to output the second current signal.

Abstract: A low-voltage constrained coefficient adaptation and multiplication is provided. To provide the constrained coefficient adaptation, an adder adds an adaptive differential control voltage to a forcing differential control voltage to provide an effective coefficient. The adder is configured such that the forcing differential control voltage can prevent the adaptive differential control voltage from producing a sign change in the effective coefficient.

Abstract: The synthesizer and method provide a relatively wideband swept frequency signal and include generating a first swept frequency signal with a first generator, and successively switching between different frequency signals with a second generator. Such switching creates undesired phase discontinuities in the output swept frequency signal. The first swept frequency signal is combined with the successively switched different frequency signals to produce the relatively wideband swept frequency signal, and the second generator is calibrated to reduce the undesired phase discontinuities during switching based upon the output swept frequency signal.

Abstract: An RMS-to-DC converter implements the difference of squares function using two squaring cells operating in opposition to attain a balance. Each of the squaring cells is implemented as a grounded-base transistor and a two-transistor current mirror. The emitter of the grounded-base transistor is coupled to the input terminal of the current mirror at a node which receives the input signal. The collector of the grounded-base transistor and the output of current mirror are coupled together to generate an output current having a square-law relationship to the input signal. One of the squaring cells receives the input signal and operates at high frequencies (HF), while the other receives a feedback signal and operates in a quasi-DC mode. In a measurement node, a nulling circuit closes a feedback loop around the DC squaring cell to null the output currents from the squaring cells.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: The assembly formed by the amplifier 34, the transistor 36 and the capacitor 28 fulfills the function of the amplifier 8 and the impedance 10 of the device shown in FIG. 4.

Abstract: A mobility proportion current generator comprises a voltage adder including a first MOS transistor, the voltage adder adding a voltage whose temperature dependency is small with respect to the mobility and a threshold voltage of the first MOS transistor to output a sum voltage, and a second MOS transistor including whose drain terminal is connected to a constant potential point, the sum voltage of the voltage adder being applied between the gate terminal and the source terminal of the second MOS transistor to output a current proportional to the mobility being output from the drain terminal thereof.

Abstract: A phase-locked loop includes a phase detector which receives an input signal and a first internal periodic signal and provides a phase signal indicative of a phase difference between the input signal and the internal signal. A rotator then receives the phase signal and provides first and second periodic signals each having a frequency that is a function of the phase difference, the first and second periodic signals being 90 degrees out of phase with each other. An interpolator circuit then linearly combines the first and second periodic signals with third and fourth periodic signals to provide the first internal periodic signal. The interpolator circuit may provide a second internal periodic signal that is 90 degrees out of phase relative to the first internal periodic signal. The phase-locked loop may further include a low-pass filter provided between the phase detector and the rotator.

Abstract: Offset adjustments for both differential and single-ended measurements are accomplished in the same probe or system. Different variable offsets are provided for the positive and negative inputs of a differential amplifier, and a variable offset adjustment is provided to remove differential amplifier output offset. Common mode and reduced dynamic range problems for both differential and single-ended measurements are eliminated. All or desired portions of required functions may be implemented using discrete or DSP approaches.

Abstract: A digitally controlled frequency synthesizer has a first direct digital synthesizer that generates a first phase-coherent, time-varying frequency, and a second direct digital synthesizer that generates an offset frequency waveform. A plurality of cascaded frequency converters successively combine the offset frequency waveform with a reference frequency waveform to produce a plurality of waveforms having respectively different frequencies. A switch switches between the plurality of waveforms produced by the cascaded frequency converters to realize a second waveform. The operation of the second direct digital synthesizer is controlled so as to maintain phase continuity between respective ones of the plurality of waveforms contained in the second waveform as output by the switch. A mixer multiplies the first waveform by the second waveform to produce a time-varying output frequency.

Abstract: A mobility proportion current generator comprises a voltage adder including a first MOS transistor, the voltage adder adding a voltage whose temperature dependency is small with respect to the mobility and a threshold voltage of the first MOS transistor to output a sum voltage, and a second MOS transistor including whose drain terminal is connected to a constant potential point, the sum voltage of the voltage adder being applied between the gate terminal and the source terminal of the second MOS transistor to output a current proportional to the mobility being output from the drain terminal thereof.

Abstract: A voltage subtractor/adder circuit has a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: A mixer circuit according to the present invention includes a first differential transistor pair of two transistors, a second differential transistor pair of two transistors, an impedance element connected to the first differential transistor pair, an impedance element connected to the second differential transistor pair, an inductor connected to nodes A, B, a current source connected to node A, a current source connected to node B, and a capacitor. A mixer circuit with high conversion gain and small distortion can be obtained.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: A method and an apparatus for dynamically varying a clock frequency in a processor to adapt to VCC voltage changes. The method of one embodiment includes sampling a supply voltage at a plurality of locations. The values of said supply voltage are communicated to a clock generator. A clock frequency of a clock signal generated from the clock generator is adjusted in response to an evaluation of the sampled values of the supply voltage.

Abstract: An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.

Abstract: A sub-harmonic mixer comprises two field effect transistors in which the sources of the transistors are connected together and the drains of the transistors are connected together. The mixer includes signal generating means for generating a local oscillator (LO) signal coupled to the gate of one of the FETs. Circuit means is provided for maintaining the potential of the gate of the other FET at a substantially constant value relative to the local oscillator signal applied to the gate of the driven FET, and the FET's are arranged to permit the local oscillator signal applied to gate of the driven FET to drive a voltage across the gate-source of both FET's. An input and output port is coupled to the drains for receiving input signals for the mixer and outputting output signals from the mixer.

Abstract: A pair of resistors, having substantially equivalent resistance are arranged in series so that two data output lines of a differential data driver are connected to the ends of the series of resistors, the potentials of the two output signals ((D+)data output signal and (D−)data output signal) from the differential data driver are resistively divided to detect the sum of the potentials of the two signals. Based on the voltage of the combined signal, the acceptability of the differential signals of the differential data driver is determined.

Abstract: An image reject mixer for a low power battery operated radio telephone application. First and second doubly balance mixer circuits are connected to receive a differential radio frequency signal. Each of the doubly balance mixer circuits receives a local oscillator signal and a complimentary quadrature local oscillator signal. A first and second differential current produced by the first and second doubly balance mixture are combined in a quadrature combining circuit. The quadrature combining circuit adds an additional 90° of phase shift between the pairs of signals produced by each doubly balance mixture, so that the mixture output signals are added in a phase quadrature relationship thereby canceling unwanted spur and image components contained in the respective mixer output circuits.

Abstract: An integrated circuit (10) includes a thermal shutdown circuit that incorporates hysteresis for shutting down a functional circuit (13) when its temperature exceeds a predefined value. First and second current sources (18, 17) respectively produce first and second reference currents (IREF1, IREF2) representative of first and second die temperatures of the integrated circuit. A current mirror (14) has an input (19) for summing the first and second reference currents and an output (15) for providing a mirror current (IMIRROR). A detection circuit (12) has an output coupled to the output of the current mirror for sinking the mirror current to produce a detection signal (VDET) as a function of the first and second die temperatures.

Abstract: A voltage mode logarithmic amplifier comprising: a first gain stage for providing an amplified rectified voltage signal responsive to an input voltage signal; a second gain stage for providing a further amplified rectified signal responsive to the input voltage signal; and an output node for producing an output voltage signal responsive to the amplified rectified voltage signal and the further amplified rectified voltage signal. The amplifier further includes: a self-biased replica stage operative to provide a voltage offset signal responsive to temperature; and a differential amplifier operative to receive the voltage offset signal and provide a temperature corrected output voltage signal responsive to the input voltage signal, wherein the differential amplifier is communicatively coupled to both the first gain stage and the second gain stage.

Abstract: Disclosed are a phase blender for generating an output voltage having a phase difference with respect to first and second input voltages having a phase difference and a multi-phase generator using the same. The phase blender has first and second phase delay units having phases corresponding to the phases of the first and second input voltages respectively, an intermediate phase output unit for outputting third and fourth output voltages having an intermediate phase of the first and second input voltages, and an output selection unit for selecting and outputting two of various output voltages. The multi-phase generator is constituted with the phase blenders connected in series, so that the phase blender of the final stage in the multi-phase generator outputs one of various output voltages having an intermediate phase of the first and second input voltages. Therefore, a multi-phase generator is provided which has a small power consumption.

Abstract: The present invention relates to a weighted mean calculation circuit that comprises an inverting amplifier; a plurality of capacitors C1 through Cn connected to the input terminal thereof; switches SW1 through SWn that connect the capacitors C1 through Cn to the input and output terminals of the inverting amplifier; and a switch SW0 that is provided between the input and output of the inverting amplifier. A signal voltage is applied to respective capacitors while making the SW0 conductive when inputting a signal, and the capacitors C1 through Cn are connected in parallel between the input and output of the inverting amplifier while making the SW0 non-conductive when outputting a signal, whereby an output signal Vout is read, and a weighted mean value output that does not include any offset and is normalized as a normal polarity output can be obtained.

Abstract: A mixer circuit (21) includes first (31) and second (32) transconductance amplifiers, a switching circuit (34), and an oscillator processing stage (36). The transconductance amplifiers (31,32) generate differential current signals in response to modulated signals having different carrier frequencies. The oscillator processing stage (36) generates a local oscillator signal from a reference oscillator signal. The switching circuit (34) switches the differential current signals at the frequency of local oscillator signal to generate an intermediate frequency output signal.

Abstract: A method and apparatus for synthesizing an approximation to a sine wave comprising generating a number of pulse width modulated signals, each having a predetermine duty cycle and being the same frequency as each other, from a clock signal. The generated pulse width modulated signals are then combined to produce an approximation to a sine wave having the same frequency as the pulse width modulated signals. The clock signal is provided by an oscillator arranged to produce clock signals over a continuous range of frequencies so that approximations to a sine wave can be produced over a continuous range of frequencies.

Abstract: A current summing circuit includes an active cascode pair of transistors having a source-drain junction connected to a summing node to receive an input current at the source-drain junction to output an output current at a source of a transistor of the active cascode pair of transistors.

Abstract: An analog calculation circuit in a filter circuit is corrected in the calculation error by estimating the error from a calculation result of known inputs and known multiplier. A multiplier is changed according to the estimated error. The filter circuit has a voltage to current converter at an input side and a current to voltage converter at an output side and a calculation of current is performed therein.

Abstract: A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Abstract: The device and method monitor the current delivered to a load through a power transistor including a sense transistor. The circuit includes a disturbances attenuating circuit that has a differential stage, and first, second and third stages referenced to ground, the respective input nodes of which are connected in common to an output node of the differential stage. The third stage is formed by a transistor identical to a transistor of the first stage and delivers a current signal through a current terminal thereof, proportional to the current being delivered to the load.

Abstract: Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage.

Abstract: A mixer circuit having a high conversion gain which is excellent in linearity comprises an amplifier (1A) for amplifying one of two signals to be mixed with each other. The amplifier (1A) comprises a low-pass filter (14) not damping an input voltage (v1) of a frequency (f1) on a negative feedback circuit for its output. Due to the low-pass filter (14), it is possible to reduce harmonics by increasing the feedback amount as the frequency is increased.

Abstract: An analog multiplier circuit utilizes a dual feedback structure, in which two multiplier core sections can be progressively enabled or disabled to varying degrees, thereby providing variable gain while maintaining constant bandwidth. The multipliers are preferably controlled by a pair of ratiometric gain control signals in a manner that provides very accurate end-point gain. A summing device combines the outputs from the multipliers to generate a final output signal that is buffered and fed back to the multipliers through two separate feedback paths. The circuit can operate as a video keyer that linearly selects between two input signals applied to the multipliers. Alternatively, the circuit can be operated as a variable gain amplifier (two quadrant multiplier) when one of the two inputs is not used. Each of the multipliers is preferably implemented with sets of differential transistor pairs having complementary symmetry and a Class AB current conveyor input.

Abstract: By taking advantage of the ability to control the phase relationship between a processor's output (or portions of a processor's output) and the phase of the pre-processed signal (in a particular frequency range or ranges, a controlled accentuation or enhancement of the processor's effect can be realized. In one embodiment this is achieved by providing a gain control circuit that receives and selectively amplifies the input signal prior to it being summed with the processor's output.

Abstract: The invention relates to a device for generating digital control signals having the following features: an oscillator (10), which has a digital output two storage means (20, 30) for storing the value of digitally coded variables, which each have a clock input (22, 31) connected to the digital output (11) of the oscillator (10), a data input (21, 32) and a data output (23, 33) an adder (40) which has two data inputs (41, 42), a data output (43) and a carry output (44), where the first data input (41) of the adder (40) is connected to the data output (23) of the first storage means (20), the second data input (42) of the adder (40) is connected to the data output (33) of the second storage means (30), the data output (43) of the adder (40) is connected to the data input (32) of the second storage means (30), and the carry output (44) of the adder (40) is connected to a pulse divider (50).

Abstract: A voltage subtractor/adder circuit comprises a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

Abstract: An electrode wiring structure is disclosed which realizes a semiconductor apparatus as a power semiconductor module with the current path set as shortest as possible and uniformly. The semiconductor apparatus includes: a plurality of semiconductor devices mounted in one array or more on a substrate; a main current electrode mounted along the array(s) of the semiconductor devices, and commonly connected to each of the plurality of semiconductor devices through the substrate. The substrate is connected to the main current electrode through a plurality of wires arranged along the array(s) at equal or substantially equal distances.

Abstract: An arrangement for selecting the largest of a plurality of input currents (pma (k-1), pmb (k-1)) and adding a further current (Ibmk) to the selected current, the arrangement comprising: a plurality of inputs (901, 902) for receiving said input currents; a further input (905) for receiving said further current; an output (906, 907) for delivering an output current proportional to the sum of the largest of the input currents and the further current; means for feeding each of the received input currents to the main current conducting path of a respective transistor, (T900, T902) each of the transistors having its control electrode connected to a common point; a respective follower transistor (T901, T903) connected between the input and the common point; and a mirror transistor (T904) having its control electrode connected to the common point for producing a current whose value is related to that of the largest input current.

Abstract: A signal reception apparatus in the spread spectrum communication system requires only a small amount of circuitry and consumes a small amount of electric power. A quadrature detector decomposes received signals into in-phase components and quadrature components, and supplies them to a complex-type matched filter. The complex-type matched filter de-spreads the in-phase components and the quadrature components and sends them to a multi-path selector. The multi-path selector selects, from among the received de-spread signals, multiple paths having high levels of signal electric powers and sends the received signals of the selected paths to multiple phase correction blocks. Analog operation circuits calculate phase errors of the received signals of two successive pilot symbol blocks for each path. An analog operation circuit corrects the phases of the received signals of the information symbol block that has been received between the two successive pilot symbol blocks.

Abstract: The invention presents a circuit by which control of the output amplitude of digital analog converters can be carried out at high speed and with high precision. A first digital signal that is the same as the input signal and a second digital signal of a value slightly smaller than an input signal provided from a high-speed processor are selectively applied to plural D-A converters and the output therefrom is added. By changing the ratio with which the first digital signal and the second digital signal are selected, it is possible to control the analog output amplitude.

Abstract: A multiple differential pair circuit is disclosed having a transconductance, gm, proportional to the bias current, I0, for any transistor technology. The transistors utilized to construct each of the differential transistor pairs in a multiple differential pair circuit operate in a non-exponential voltage-current (V-I) region. As multiple differential pair circuits are linearized, the effective transconductance, gm, becomes (i) linearly dependent on bias current, and (ii) insensitive to the voltage-current (V-I) characteristics of the utilized devices. Methods and apparatus are disclosed that provide a linear transconductance, gm, with respect to the bias current, I0, using differential pairs of transistors where each transistor operates in a non-exponential voltage-current (V-I) region, such as MOS transistors.

Abstract: An integrated circuit has a first circuit section and a second circuit section. The first circuit section has a local ground and is coupled to an external ground of a power supply for the first circuit section. The first circuit section adds an offset potential to the local ground potential when the first circuit section is on, due to an IR drop between the local ground and the external ground. The second circuit section has a signal-generating device and an offset correction circuit. The signal-generating device is referenced to the local ground potential and provides an output signal related to an input signal applied thereto. The offset correction circuit subtracts an offset adjust value from one of the input signal and the output signal to reduce offset error in the output signal caused by switching the first circuit section on and off.

Abstract: The computational circuit adds a drain current of a first MIS transistor which is driven by inputting a signal obtained by superimposing an AC signal to a DC voltage, and a drain current of a second MIS transistor which is driven by inputting a signal obtained by superimposing the same AC signal as above but reversal in phase to the DC voltage, and subtracts a drain current of a third MIS transistor driven by supplying the DC voltage to the gate thereof so as to erase DC components of the outputs of the first and second MIS transistors. Thereby, it is possible to produce a current in proportional to square of the AC signal.

Abstract: A method and circuit for automatically centering the control loop bias current by sensing and “memorizing” the total steady state bias current used by the function block (VGA or VCO) through the use of both digital and analog memory elements. The present invention uses an auto-centering, high-impedance current driver to supply the bias current. This current driver cancels out offset currents by exploiting the high output impedance nature of a CMOS current driver using cascoded or resistor source de-generated FET devices.

Abstract: An RMS-to-DC converter implements the difference of squares function using two squaring cells operating in opposition to attain a balance. Each of the squaring cells is implemented as a grounded-base transistor and a two-transistor current mirror. The emitter of the grounded-base transistor is coupled to the input terminal of the current mirror at a node which receives the input signal. The collector of the grounded-base transistor and the output of current mirror are coupled together to generate an output current having a square-law relationship to the input signal. One of the squaring cells receives the input signal and operates at high frequencies (HF), while the other receives a feedback signal and operates in a quasi-DC mode. In a measurement node, a nulling circuit closes a feedback loop around the DC squaring cell to null the output currents from the squaring cells.

Abstract: There is disclosed a semiconductor device in which capacitor means are connected to multiple input terminals via latch means, and the terminals on one side of the capacitor means are commonly connected to the input of a sense amplifier, thereby attaining a reduction of the circuit scale, improvement of the operation speed, saving of the consumption power, reduction of the manufacturing cost, and improvement of the manufacturing yield.

Abstract: A signal processing circuit is disclosed. The signal processing circuit comprises a sensor for receiving a voltage and providing a first signal based on at least one parameter. The signal processing circuit further includes a first digital to analog converter (DAC) for providing a supply voltage to the summer and a second DAC for providing a voltage (V.sub.tc) which is dependent upon the supply voltage and a variation in temperature of the supply voltage. The signal processing circuit also includes a summer coupled to the first and second DACs for receiving the first signal and providing a first output and a gain circuit for receiving the first output and providing an output voltage. In accordance with the system and method of the present invention, a voltage V.sub.tc which is dependent on the supply voltage and a variation in temperature of the supply voltage can be utilized advantageously to minimize the number of DACs in the signal processing system.

Abstract: In accordance with the present invention, an adder tree structure includes at least two adder stages. In the circuit and method according to the present invention, the first of the two adder stages generates two bits of a common weight and other more significant bits of a weight one bit more significant than the two bits of the common weight. The second of the two adder stages includes an adder that receives the more significant bits generated in the first of the two adder stages. The second adder stage also includes an AND gate which receives and logically AND's the two bits of the common weight to generate a carry-in bit for the adder in the second stage. The above adder tree structure and adding method have an advantage of permitting more input terminals of adders to contain information about the input values to the adder tree structure. Therefore, the adders are used more efficiently and less adders are required to perform a specific function.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.