Abstract: An analog median filter for rejecting isolated impulse noise while preserving signal step changes in image processing. The analog median filter includes a number of transconductance amplifiers with additional CMOS inverters coupled to the outputs of the amplifiers. The outputs of the inverters are coupled together in a feedback loop configuration with the amplifiers. The CMOS inverters act as a type of additional current source for the amplifiers, so as to sharpen the corners of the transfer curve at various current levels. The low gain of the inverters improve the stability of the output range. Because inverters are used, the feedback loop is coupled to the noninverting inputs of the amplifiers, while the input signals are coupled to the inverting inputs of the amplifiers.

Abstract: An OTA having a completely linear transconductance characteristic or a squarer having an accurate square-law characteristic is provided, which is comprised of first and second differential circuits. The first differential circuit has a first differential pair of first and second MOSFETs whose sources are coupled together and a third MOSFET serving as a bypass transistor for the first differential pair. The first differential pair is driven by a first constant tail current. The second MOSFET is driven by a first constant driving current. The second differential circuit has a second differential pair of fourth and fifth MOSFETs whose sources are coupled together and a sixth MOSFET serving as a bypass transistor for the second differential pair. The second differential pair is driven by a second constant tail current. The fifth MOSFET is driven by a second constant driving current.

Abstract: The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

Abstract: A quadrature mixer architecture that mixes the in-phase and quadrature phases within the same cell. The input voltage is applied to the base of a voltage conversion transistor, which converts the input voltage into a bias current on the collector of the voltage conversion transistor. Four mixer transistors have their emitters connected to the collector of the drive transistor so as to receive the bias current. The bases of a first pair of the upper transistors are fed with the in-phase components (e.g., 0 and 180.degree.), while the bases of the other pair of transistors are fed with the quadrature phase components (e.g., 90 and -90.degree. of a local oscillator). The collectors of the mixer transistors are taken as the four output components of the circuit, I.sub.out, I.sub.out.sbsb.--, Q.sub.out, and Q.sub.out.sbsb.--.

Abstract: A signal processor utilizes a globally nonlinearly coupled array of nonlinear dynamic elements. In one embodiment of the invention, these elements take the form of bistable overdamped oscillators. The processor exploits the phenomenon of stochastic resonance to amplify a weak periodic signal embedded in noise. In this signal processor, a system or plurality of nonlinearly coupled overdamped oscillators is subject to a weak periodic signal embedded in a noise background. For communication or detection applications, this weak signal component is the signal of interest. A reference oscillator is chosen from the plurality of overdamped oscillators, and is given a time scale for relaxation that is longer than the remaining oscillators. The output of the reference oscillator is analyzed for signal processing purposes in response to the signal and noise.

Abstract: A device for monitoring chip temperature of a switch output stage having a switch element (100, 106) that has a first circuit (10) for generating a signal (pv.sub.on) corresponding to the dissipated power of the switch element (100-106) during an on state. The device has a second circuit (20) for generating a signal (pv.sub.1, pv.sub.2 ; pv'.sub.1) corresponding to the dissipated power of the switch element (100-106) during a turn-on and/or turn-off event. The device further has a summer (40) that sums the signals (pv.sub.on, pv.sub.1, pv.sub.2 ; pv.sub.on pv'.sub.1) of the first and second circuits (10, 20) in weighted fashion and outputs a sum signal (pv.sub.sum) corresponding to the dissipated power of the switch element (100-106). The device also has an integrator (60) that responds to the sum signal (pv.sub.sum) and outputs an output signal (th) corresponding to the chip temperature of the switch element (100-106).

Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.

Abstract: A semiconductor operational circuit conducts real-time analog vector operations to permit the determination of the center of gravity of an image of a moving object. The circuit employs a first processing stage utilizing CMOS source follower circuits to perform weighted linear sum operations on the analog signals. A second processing stage utilizes comparator circuitry to perform comparison operations involving data from the weighted-sum and non-weighted-sum operations. A third processing stage utilizes exclusive OR gates to provide digital data outputs based on the comparison operation results.

Abstract: A device for comparing two DC voltages (U.sub.1, U.sub.2) comprises a voltage comparator (3) having two inputs (9, 11). One of the two voltages (U.sub.1, U.sub.2) to be compared to each other is fed directly into one of the inputs (9, 11). The other voltage enters a voltage-conversion device (2) in which the voltage to be compared is superimposed with the DC voltage (8) so that a DC voltage arises at the output (7) of the voltage-conversion device (2), which voltage periodically fluctuates back and forth between an upper and a lower amplitude value in the cycle of the square-wave signal (8). The distance between the two amplitude values corresponds to the tolerance band within which the two voltages (U.sub.1, U.sub.2) to be compared with one another must be identical.

Abstract: A semiconductor arithemetic circuit which performs calculation of an analog vector with a high accuracy at a high speed.

Abstract: Hybrid differential pairs and methods of their hybridization by connecting and operating in parallel a degenerated differential pair with a multitanh. Proper matching of the degenerated differential pair and the multitanh results in higher linearity levels than can be attained with either approach individually. Also, the hybrid benefits from reduced process variation when compared with prior multitanh solutions. Increased gain, increased linearity, reduced noise and reduced supply current can all be achieved in a manufacturable fashion using the invention.

Abstract: A circuit for generating an output signal used for driving a grounded load is provided. The circuit provides an output signal without glitches or spikes. The circuit also outputs a drive signal with enhanced responsiveness in transitioning from one output value level to another output value level. The circuit includes a plurality of control devices for providing respective output signals responsive to respective control signals. The base of a PNP transistor is coupled to the output of the control devices and acts as a buffer. The emitter of the PNP transistor is coupled to a voltage source and the collector is coupled to a grounded load for providing the drive current. Alternatively, an NPN transistor and current source provides the drive current to the grounded load. The circuitry may be used in an optical disk drive with the load and ground being a laser diode used for providing a laser beam in reading/writing an optical disk.

Abstract: Signal generating apparatus comprises a linear series of Hall-effect switches (44) arranged as a plurality of linear arrays in discrete probes (46a, 46b . . . 46n) which are butted end to end. Each switch is closed when in proximity of an actuating magnet (40) movable along the series of switches. In each array a resistance chain (66) is linked at intervals to the switches. Movement of the magnet along an array thereby gives a progressively changing voltage on an output line (5) from the resistance chain as a cumulative signal indicating the position of the magnet. When the magnet moves from one array to the succeeding array after generating a maximum cumulative signal from said one array, that signal is maintained by a latch connection (56) between the two arrays. A cumulative signal representing the magnet position relative to the complete series of switches can thus be generated.

Abstract: In a differential circuit including first and second transistors, a constant current circuit causes a constant current to flow through the first transistor. A variable current circuit causes a variable current to flow through the second transistor. A differential input voltage is given to drive the first and the second transistors and to produce an output signal in the form of an output current which may be either a differential output current across two output electrodes or a variable output current flowing through an output electrode. Each of the first and the second transistors may be bipolar transistors or MOSFET's. A relationship between the differential input voltage and the output signal is specified by a peculiar characteristic dependent on the bipolar transistors or the MOSFET's. Therefore, the differential circuit may be incorporated in an LSI circuit.

Abstract: A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

Abstract: An input signal of frequency tolerance A is combined with a reference first signal having a frequency tolerance B to develop a second signal having a combined frequency tolerance of -A and B . The input signal is combined with the second signal to offset and cancel the A and -A frequency tolerances to produce an output signal having a B frequency tolerance.

Abstract: A voltage subtracter circuit of the present invention includes a constant current source 1, a first MOS transistor pair 2, one end of which is connected to a source voltage terminal, and a second MOS transistor pair 3, one end of which is connected to the constant current source 1. A first differential input voltage is applied between the gate terminals of the first transistor pair 2, and a second differential input voltage is applied between the gate terminals of the second transistor pair 3. Output terminals V1 and V2 are connected to the connecting point between the first and second transistor pairs 2 and 3. From these nodes V1 and V2, a differential voltage between the first differential input voltage and a differential voltage proportional to the second differential input voltage is outputted.

Abstract: An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

Abstract: A phase lock loop circuit includes an oscillator, a digital mixer, a comparator, a loop amplifier, and a low-pass filter. The oscillator has an oscillation frequency controlled by a control voltage. The digital mixer is constituted by a digital element to output a difference frequency signal between an oscillation output from the oscillator and an input mixing signal. The comparator compares at least the phase of the difference frequency signal output from the digital mixer with that of a reference frequency signal, and outputs a difference signal. The loop amplifier and the low-pass filter generate the control voltage for the voltage controlled oscillator on the basis of the difference signal output from the comparator.

Abstract: A voltage level shift circuit has a first input receiving a first voltage signal and a second input receiving a second voltage signal. The voltage level shift circuit is structured to generate an output voltage at an output terminal which is equal to a sum of the first and second voltage signals. The first voltage signal may be varied to vary a shift of the second voltage signal.

Abstract: The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.

Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.

Abstract: A semiconductor integrated circuit device includes a variable current source 2. This device further includes a control circuit 1, 10 causing the current source to change the value of the current produced therefrom in response to a set of control signals, and a shift register 13 serially receiving control data and produces the set of control signals in a parallel form.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction in performed by two MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: A differential-to-single-ended converter comprising a resistor network (205) and an operational amplifier is introduced. In comparison to prior art converters, a resistor (250) placed between the non-inverting input (264) of the operational amplifier (260) and the negative input terminal (202) of the converter (200). The common mode voltage (V.sub.nii ') at the non-inverting input (264) does not depend on the differential input voltage (V.sub.in.sup.#) of the converter (200) and has low fluctuations. This allows the use of an operational amplifier (260) with low CMRR and makes the converter (200) suitable for low voltage applications.

Abstract: In a summing comparator (10) in which one differential input voltage received by one differential pair (18) is dependent on temperature variations, such as across a resistor (12) with a large temperature coefficient, the dependence on temperature is offset by introducing cancelling temperature dependence in the other differential pairs (14, 16).

Abstract: A variable electronic resistor (16), which can be varied by a control signal (Ust) at the control input (15), contains two parallel, signal paths (1 and 2) with identical components, of which one signal path carries a phase inverted input transmission signal and the other signal path carries a non phase inverted input transmission signal and which are additively joined at the output side. Each signal path contains a charge carrier channel (3) and a signal transmission stage (7) with a low impedance current input, located downstream of the output electrode (5) in the signal path of the charge carrier channel. The resistor of the charge carrier channel can be varied by a control voltage (Ust), which is common to both charge carrier channels, in a control electrode (14) of the semiconductor components (4).

Abstract: A degenerated differential pair waveform builder has a single ramp generator control circuit and a plurality of differential pairs. A trigger input is generated and input to the ramp generator control circuit. The ramp generator control circuit then generates a differential signal which is output to each of the differential pairs through a positive edge signal node and a negative edge signal node. Each differential pair then generates an output in response to the differential signal output from the ramp generator control circuit. The outputs from the differential pairs are combined in a summing circuit which outputs a composite waveform. Each differential pair has an associated ramp time which is dependent upon the value of the resistance in its emitter circuit. The ramp time of each differential pair directly affects the slope of its resulting output waveform.

Abstract: A method and apparatus for generating an AC voltage with user defined inductance and resistance values in series therewith is described. The output voltage of the AC source is sampled and a signal indicative of the total current being generated is derived. The signal is scaled to model a series resistance and scaled and differentiated to model a series inductance. The modelled series resistance and inductance are then combined with the output voltage. Different inductances and resistances can be modelled merely by changing the user's input to the microcontroller that controls the operation of the present invention.

Abstract: A weighted addition circuit contains a plurality of resistances, each of which is connected to a common output at one terminal and to different input voltages at the other terminal. The voltage at the common output terminal is a balance voltage of the input resistances. The common output terminal is connected to an amplifier having an odd number of stages of inverters and a feedback resistance connecting the output of the last inverter stage to the input of the first inverter stage. Grounded low pass capacitors and/or balance resistors are also be included in the amplifier to improve the stability of the circuit and prevent undesirable oscillation. Providing a circuit containing a balance voltage of the parallel-connected input resistances allows for precise weighted addition of any number of inputs while still maintaining a small and simple circuit structure.

Abstract: Addition is performed by a capacitive coupling or resistive coupling. A quantizing circuit is realized by plurality of thresholding circuits receiving an analog input voltages. Subtraction is performed by to MOSs of anti-polarity inputted analog input voltages to gates.

Abstract: A common mode controlled signal multiplier includes a pair of interconnected differential amplifiers, each of which receives a common mode signal and an input signal and generates one phase of a differential output signal. In one of the differential amplifiers, the common mode signal is applied to the input terminal of each transistor, while the input signal is applied differentially to the input terminals of the transistors. In the other differential amplifier, an inverse phase of the common mode signal is applied to the input terminal of each transistor, while the input signal is applied differentially to the input terminals of the transistors. The differential amplifiers together generate the differential output signal, with such differential output signal having output frequencies including a sum of and a difference between the frequencies of the common mode signal and the input signal.

Abstract: AC coupling is effected by a feedback circuit that detects a DC component in the coupled signal, and adjusts a DC subtraction signal accordingly. In one embodiment, a digital signal processor (DSP) analyzes the coupled signal for a remaining DC component, and controls the subtraction signal. Use of a DSP allows dynamic control of parameters including AC cutoff frequency, gain, and transfer function. Another embodiment provides accurately phase matched AC coupling across two or more signal channels.

Abstract: A driver circuit for a laser diode includes a prebiasing amplifier for providing a prebiasing current, a second amplifier for amplifying an input signal to provide an output current signal, and a third amplifier for amplifying the sum of the current output signal and the prebiasing current. In one embodiment, the third amplifier includes first and second current mirrors. In another embodiment, a capacitor couples one output of the second amplifier to an inverting input of the third amplifier, so as to increase the effective gain of the third amplifier.

Abstract: A method and apparatus for integrating a plurality of analog input signals. A first integrator(725) having a first pole frequency integrates a first of the input signals and a second integrator(730) having a second pole frequency different than the first pole frequency integrates a second of the input signals. A summer(735) is connected to the first and second integrators to then sum the integrated first and second signals and provide a composite integrated signal prior to transmitting a communications signal.

Abstract: A monolithic microwave semiconductor integrated circuit including a bias stabilizing circuit of a current mirror type formed of a bias control transistor formed of an enhancement mode compound semiconductor field effect transistor and a biased transistor formed of an enhancement mode compound semiconductor field effect transistor.

Abstract: A computational circuit that includes a first capacitive coupling that connects a plurality of analog input voltages to a first inverter. The first inverter is connected to a second inverter through a connecting capacitance. A first feedback capacitance connects the output of the first inverter to its input, and a second feedback capacitance connects the output of the second inverter to its input. A first additional capacitance is operatively connected between ground and the first capacitive coupling, and a second additional capacitance is connected between ground and the connecting capacitance. The values of the first and second additional capacitances is selected such that the closed-loop gains of the first and second inverters are substantially equal.

Abstract: A four-quadrant three-input multiplier is disclosed. The three-input multiplier, which finds the product of a first input signal, a second input signal, and a third input signal, includes four differential transconductance amplifiers and two loads. Transistors in the differential pair of each differential transconductance amplifier are operated in the subthreshold region. Four linear-combination signals are individually fed into one input terminal of the four differential transconductance amplifiers. A linear-combination circuit configuration is also disclosed and can be used to generate the required linear-combination signals.

Abstract: A computational circuit wherein addition is performed by a capacitive coupling or resistive coupling circuit. A quantizing circuit is realized by plurality of thresholding circuit receiving analog input voltages. Each thresholding circuit includes an inverter and a capacitive coupling circuit.

Abstract: A comparator circuit in an analog computational device includes a complement circuit that receives a first analog input. The complement circuit outputs a quantized complement of the first input to first and second addition circuits. A second analog input is also provided to the first and second addition circuits. The first and second addition circuits add the complement circuit output to the second analog input and provide a low output if the result of the addition exceeds threshold values set for the first and second addition circuits. The outputs of the first and second addition circuits are provided to a judging circuit to determine which is greater.

Abstract: An apparatus for generating a sensing signal from a generally periodic multi-phase AC signal is set forth. The apparatus utilizes a plurality of integrator circuits, a single integrator circuit being respectively associated with each phase of the AC signal. The integrator circuits each generate an integrated signal from the respective phase of the AC signal by integrating the respective phase during a time period between sloping transitions of the respective phase. A reset circuit is respectively associated with each integrator circuit for resetting each integrator circuit at the sloping transitions of the respective phase. The integrated outputs are summed by a summing circuit to form the sensing signal.

Abstract: The invention makes it possible to drive a halftone image device and achieve high halftone reproduction by allowing at least one of the leading and trailing edges of a pulse width-modulated signal applied to a recording head, or forming amplitude- and width-modulated pulses, respectively, as driving pulses for placing one dot under halftone control, and changing a pulse width change of pulse width modulation in a stepwise manner, using the pulse width of the amplitude-modulated pulse as a unit pulse width.

Abstract: A non-linear circuit having a transfer characteristic which is adjustable per amplitude segment of an input signal (Yi) includes a segmenting circuit (11 . . . 15, 21 . . . 25) for obtaining a plurality of amplitude segment signals (Y1 . . . Y5) from the input signal (Yi), and a non-linear segment amplifier circuit (31 . . . 35) coupled to the segmenting circuit (11 . . . 15, 21 . . . 25) for separately multiplying segments (Y1 . . . Y5) of the input signal (Yi) by respective segment gain factors (HM1 . . . HM5) in dependence upon a common gain factor (HMa) derived from the segment gain factors (HM1 . . . HM5) and on the basis of the amplitude segment signals (Y1 . . . Y5) for supplying a signal (Y"s) which is adjustable per amplitude segment of the input signal (Yi). The non-linear circuit may also include an output circuit (37, 39) coupled to the non-linear segment amplifier circuit (31 . . .

Abstract: A low power analog absolute differencing circuit and architecture is disclosed. The circuit includes an integrating amplifier with an input node connected to a common integration line. The common integration line is connected to a set of analog comparison circuits to form an analog vector absolute differencing circuit row. Each of the analog comparison circuits compares a first analog signal to a second analog signal to produce an absolute difference signal. The absolute difference signal from each analog comparison circuit is transmitted in the form of charge drawn from the common integration line. The integrating amplifier provides an integration sum corresponding to the sum of the absolute difference signals. The analog absolute differencing architecture includes a set of analog vector absolute differencing circuit rows arranged to form an analog absolute difference computing array. The analog absolute difference computing array is loaded with a data block input array and a data frame input array.

Abstract: A filter boost preattenuator provides controlled, rapid variable signal preattenuation at the input of a filter to optimally compensate for the absolute gain increase of the filter caused by increasing the high frequency boost level of the filter. The amplitude of the filter output exhibits very little change during boost variations that dynamically occur in applications such as data and servo signal recovery in disk drives. Using the present invention, disk space overhead needed to allow for readjustment of the automatic gain control system of a read/write channel is minimized. In the present invention, the feedforward signal provided from the variable gain boost circuit is applied to a feedback circuit and subtracted from the system input. The feedback forces a drop in the overall gain of the filter that increases with boost gain.

Abstract: A small high speed averaging circuit includes a plurality of CMOS transistor pairs with substantially equal characteristics. Their voltage follower outputs are connected to a common output. A mean value is generated at the common output of the CMOS transistor pairs.

Abstract: A vector summation device includes a squaring circuit for receiving a number of input voltage signals, and a square-root circuit having first and second current terminals connected electrically to the squaring unit. The squaring circuit receives first and second current signals respectively from the first and second current terminals of the square-root circuit. The difference between the current values of the first and second current signals is proportional to the sum of the squares of the voltage values of the input voltage signals. The square-root circuit generates an output voltage signal with a voltage value that is proportional to the square-root of the difference between the current values of the first and second current signals.

Abstract: A switchable constant gain summer circuit (10) has been provided. The summer circuit selectively amplifies a plurality of input signals while maintaining a constant dc current flowing through a load which maintains a constant gain for the summer circuit. The summer circuit includes a plurality of amplifier circuits (12, 16) being respectively responsive to a plurality of input signals wherein each one of amplifier circuits has a control input and common first and second outputs for respectively providing first and second output signals. A plurality of control means (14, 18) responsive to a plurality of control signals is included for alternately providing first and second voltages to each one of the control inputs of the amplifier circuits. A load circuit (20) is coupled to the common first and second outputs of the amplifier circuits wherein a DC bias through the load circuit is substantially constant.

Abstract: A novel compensation device for conditioning or generating signals to have an arbitrarily defined shape, produced to an arbitrarily specified accuracy. The device comprises a plurality of bounded polynomial function generators having outputs summed into a summing network to produce a signal which is the composite of the effects of all of the polynomial generators. Accuracy is achieved through the use of fusible link trimming of the compensation circuits, which are configured to provide mathematically well-behaved polynomial functions with predictable responses to the programming, and which produce effects only over desired segments of the range of interest. The result is a monotonic signal with no discontinuities, which can be made arbitrarily close to a specified signal.