Abstract: A circuit includes a multi-tanh cell having a common-emitter node to receive a bias current, and an extra transistor coupled to the common-emitter node to dynamically divert a portion of the bias current from the multi-tanh cell. The circuit may be arranged as a multiplier with an input network arranged to apply two or more input signals to the multi-tanh cell. A second multi-tanh cell with an extra transistor may be arranged in a feedback loop where the outputs of the first and second multi-tanh cells are coupled together at an integrating node. A buffer drives the final output and feedback cell to cancel nonlinearities in the multiplier cells.

Abstract: An AC-coupled differential drive circuit for an optical modulator is utilized, where a common “node” is defined between top (or bottom) plates of the modulator arms themselves (the “arms” of a modulator taking the form of MOS capacitors). A low pass filter is disposed between the differential driver output and the modulator's common node to provide the desired AC coupling by filtering out the DC bias voltage of the driver circuit itself without the need for a separate, external AC coupling capacitor. An independent, adjustable DC potential can then be applied to the common node, and will appear in a balanced manner across each arm of the modulator to provide the desired DC bias for the modulator independent of the DC bias of the driver circuit.

Abstract: One embodiment relates to a mixer for providing a mixed output signal. The mixer includes a radio-frequency (RF) stage, first and second power dividers, and first and second frequency-conversion stages. The RF stage includes a first differential pair. The first power divider is coupled to a first transistor of the first differential pair, and the second power divider is coupled to a second transistor of the first differential pair. The first frequency-conversion stage, which is adapted to provide a first converted-frequency signal, includes a second differential pair coupled to the second power divider and a third differential pair coupled to the first power divider. The second frequency-conversion stage, which is adapted to provide a second converted-frequency signal, includes a fourth differential pair coupled to the second power divider and a fifth differential pair coupled to the first power divider. Other techniques are also provided.

Abstract: A first mixer circuit mixes a first center frequency signal with a first local oscillation signal to generate a second mixed signal, and mixes the first center frequency signal with a second local oscillation signal to generate a first mixed signal, and a second mixer circuit mixes a second center frequency signal with the first local oscillation signal to generate a fourth mixed signal, and mixes the second center frequency signal with the second local oscillation signal to generate a third mixed signal. An adder and subtracter circuit subtracts the third mixed signal from the second mixed signal to output a signal of subtraction result as a first upper side band signal, and adds the first mixed signal to the fourth mixed signal to output a signal of addition result as a second upper side band signal different in phase from the first upper side band signal by 90 degrees.

Abstract: An interference rejection unit for at least partially rejecting a narrowband interferer from an input signal, the unit comprising: an interferer detector for detecting the phase of an interferer in the input signal; a signal generator for generating a cancellation signal in dependence on the phase detected by the interferer detector; and a signal combiner for combining the input signal with the tone cancellation signal to generate an output signal in which the interferer is at least partially cancelled from the input signal.

Abstract: A signal transformation arrangement comprises a first input tap (1) to receive a first input signal (IN_P), a first output terminal (3) to provide a first output signal (OUT_P) and a first coupling circuit (10) which couples the first input tap (1) to a first energy storing device (11) depending on a first clock signal (CLK—1) and which couples the first energy storing device (11) to the first output terminal (3) depending on a first inverted clock signal (XCLK—1). The signal transformation arrangement further comprises a second coupling circuit (20) which couples the first input tap (1) to a second energy storing device (21) depending on a second clock signal (CLK—2) and which couples the second energy storing device (21) to the first output terminal (3) depending on a second inverted clock signal (XCLK—2).

Abstract: A device and method for generation of a dynamic focus correction signal for use with a CRT that includes an analog scanning processor for generating a dynamic focus correction signal that is proportional to Kx2+(1?K)x4, where x is the distance from a mid point of a viewing surface of the CRT, and K is a real number in the range 0.00 to 1.00. Embodiments of the invention find particular use in CRTs having generally flatter, squarer configurations.

Abstract: A main driver amplifier generates first differential signals (Vdp/Vdn) based on pattern data (PAT). A replica driver amplifier generates second differential signals (Vcp/Vcn) based on the pattern data (PAT). Two subtractors generate electric potential difference signals (HP=RP?Vep) and (HN=RN?Ven), respectively. Two sample hold circuits sample the electric potential difference signals (HP and HN), and hold them thereafter, respectively. A comparison unit compares a differential amplitude signal (DA=HHP?HHN) with a predetermined threshold value (VOH). A latch circuit latches an output from the comparison unit. Sampling timings of the two sample hold circuits and a latch timing of the latch circuit, can be adjusted independently.

Abstract: A noise generator for generating band-limited noise from a plurality of sinusoidal signals at the same level and equidistant frequency position in the noise spectrum is provided. A noise signal has a low crest factor and for this purpose the phase position of each individual sinusoidal signal is determined.

Abstract: In a bridge adder circuit, a first and a second complementary pair of current mirrors is connected between the input terminals and a positive and a negative supply voltage bus, respectively, to control a first and a second push-pull output stage. The outputs of the push-pull output stages are connected to the respective inputs through first resistors and to a common output node through second resistors. As a result, a universal circuit element for a multivalued logic element, such as ternary logic or 5-valued logic is provided.

Abstract: A mixer has a controllable load, a signal mixing module, and a controller. The controllable load is controlled by a control signal to change an equivalent load value thereof. The signal mixing module has an output port coupled to the controllable load and an input port coupled to an input signal, and is used for mixing the input signal with a local oscillation signal. The controller is coupled to the controllable load, and is used for generating the control signal to reduce the equivalent load value of the controllable load during switching transients of the local oscillation signal.

Abstract: A double-balanced mixer is provided having a shorting switch connecting the signal inputs to the mixer core. A timer circuit provides pulses to close the switch, thereby shorting those inputs at times when the switches of the mixer core are switching. This is done because non-linear components in the output are produced at those times and therefore they can be removed if the signal input is shorted at those times.

Abstract: The present invention relates to a mixer circuit and method of frequency transformation, wherein an input signal is switched in accordance with a first local oscillator signal and in accordance with at least one second local oscillator signal having a smaller duty cycle than said first local oscillator signal, or having a respective predetermined phase shift with respect to said first local oscillator signal. Output signals obtained by the switching in accordance with the first and at least one second local oscillator signals are summed and the polarity of one of said first local oscillator signal and said at least one second local oscillator signal is switched in response to a control input, to thereby switch between a harmonic-rejection mode and a sub-harmonic mixing mode.

Abstract: In a driver circuit 10 for outputting a simulated signal simulating an input signal subjected to transmission loss, corresponding to the input signal, the driver circuit 10 comprises: a main driver 18 which receives the input signal and outputs an output signal corresponding to the input signal; a sub driver 20 which receives the input signal and outputs an output signal given by inverting the input signal; a high frequency emphasizing circuit 22 which receives the input signal of the sub driver 20 and outputs an output signal having the high frequency of the input signal of the sub driver 20 emphasized; and an addition unit 24 which outputs the simulated signal given by adding the output signal of the main driver 18 and the output signal of the high frequency emphasizing circuit 22.

Abstract: An averaging circuit apparatus comprises a rectifier having an input for receiving a high-speed error signal having, for example, a data rate of 10 Gbps. An integrator is coupled to the rectifier and has an error output for providing an averaged representation of the error signal. The averaged representation of the error signal is supplied to a Digital Signal Processor in a channel equalizer loop for equalizing a fiber-optic channel. The Digital Signal Processor executes an algorithm that sets tap coefficients of an analogue filter in response to the averaged representation of the error signal.

Abstract: Provided is a power voltage forming device which can correct an offset voltage of a high-frequency power amplifier without degrading distortion characteristic of a high-frequency power amplifier. The power voltage forming device (100) includes: a level adjusting unit (103) which adjusts the level of input data subjected to analog conversion, according to an output level control value for controlling the output level of the high-frequency power amplifier (200); an analog adder (104) which performs analog addition of the offset data subjected to the analog conversion, to the signal after the level adjustment; a digital adder (101) which performs digital addition of the offset data to the input data before the analog conversion; and a selection unit (106) which selects whether to perform addition by the analog adder (104) or addition by the digital adder (101) according to the output level control value.

Abstract: An orthogonal signal output circuit having an error correction function for correcting an orthogonal error, including: first and second differential circuits; and first to fourth variable resistors, wherein the first variable resistor is connected to a positive output of the first differential circuit and a positive output of the second differential circuit; the second variable resistor is connected to the positive output of the first differential circuit and a negative output of the second differential circuit; the third variable resistor is connected to a negative output of the first differential circuit and the positive output of the second differential circuit; and the fourth variable resistor is connected to the negative output of the first differential circuit and the negative output of the second differential circuit.

Abstract: An assembly involves an integrated circuit die that is bonded, e.g., flip-chip bonded, to a non-semiconductor substrate by a plurality of low-resistance microbumps. In one novel aspect, at least a part of a novel high-frequency transformer is disposed in the non-semiconductor substrate where the non-semiconductor substrate is the substrate of a ball grid array (BGA) integrated circuit package. At least one of the low-resistance microbumps connects the part of the transformer in the substrate to a circuit in the integrated circuit die. At two gigahertz, the novel transformer has a coupling coefficient k of at least at least 0.4 and also has a transformer quality factor Q of at least ten. The novel transformer structure sees use in coupling differential outputs of a mixer to a single-ended input of a driver amplifier in a transmit chain of an RF transceiver within a cellular telephone.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: A mixer is disclosed. In one embodiment, the mixer includes a polyphase filter that generates linear quadrature signals. The mixer also includes a potentiometric mixer that performs a frequency-conversion operation on the quadrature signal. According to the embodiments disclosed herein, the output of the potentiometric mixer has high linearity.

Abstract: An orthogonal signal output circuit having an error correction function for correcting an orthogonal error, including: first and second differential circuits; and first to fourth variable resistors, wherein the first variable resistor is connected to a positive output of the first differential circuit and a positive output of the second differential circuit; the second variable resistor is connected to the positive output of the first differential circuit and a negative output of the second differential circuit; the third variable resistor is connected to a negative output of the first differential circuit and the positive output of the second differential circuit; and the fourth variable resistor is connected to the negative output of the first differential circuit and the negative output of the second differential circuit.

Abstract: A filter circuit is constructed of a passive mixer and a frequency response device. The passive mixer generates a frequency-converted signal by mixing an input signal transmitted through a transmission line and a local oscillation signal, and outputs the frequency-converted signal to the frequency response device, thus shifting a frequency characteristic of the frequency response device to high frequency by a local oscillation frequency of the local oscillation signal and applying the frequency characteristic shifted to high frequency on the input signal.

Abstract: A frequency mixing apparatus with improved voltage gain and linearity is provided. The frequency mixing apparatus includes a transconductor, a separator, and a switching unit. A voltage gain of the transconductor is controllable, and the transconductor converts a Radio Frequency (RF) signal into a current signal under control of a self bias. The separator transfers the current signal to the switching unit. The switching unit outputs a signal having a frequency corresponding to one of a sum and a difference of a frequency of the RF signal and a frequency of a Local Oscillation (LO) signal by performing a switching operation according to the LO signal.

Abstract: Provided is an adder in which all of circuits can be constituted by CMOS transistors, a process is simplified, and a chip size can be reduced as compared with a conventional art. The adder according to the present invention includes: a first VI converter and a second VI converter that allow a current corresponding to an input voltage to flow therein; and a current addition resistor having one end commonly connected to output terminals of the first VI converter and the second VI converter and another end grounded, which is adjustable in a resistance value.

Abstract: Disclosed herein is a subtractor circuit for outputting an output voltage as a difference between a first input voltage and a second input voltage. The subtractor circuit may include a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element, and a sixth semiconductor element configured to each invert a voltage input to an input terminal and output the inverted voltage from an output terminal; an input terminal of the first semiconductor element; an input terminal of the second semiconductor element; an output terminal of the first semiconductor element; and an output terminal of the third semiconductor element.

Abstract: An apparatus configured as a compandor to achieve a defined dynamic range for an output signal in response to an input signal. In particular, the apparatus comprises a first circuit adapted to generate a first signal from the input signal, wherein the first signal includes a first dynamic range (e.g., a first sensitivity and first compression point); and a second circuit adapted to generate a second signal from the input signal, wherein the second signal includes a second dynamic range (e.g., a second sensitivity and second compression point) that is different from the first dynamic range of the first signal. The apparatus may further include a third circuit adapted to generate an output signal related to a sum of the first and second signals. By adjusting the first and second dynamic ranges, an overall dynamic range for the output signal of the companding apparatus may be achieved.

Abstract: A mixer circuit designed for low voltage operation with rail-to-rail local signals. First and second transistors form a first input section to produce a first signal. Third and fourth transistors form a second input section to produce a second signal. Fifth and sixth transistors form a third input section to produce a third signal. Seventh and eighth transistors form a fourth input section to produce a fourth signal. A differential RF input signal drives the first, third, fifth, and seventh transistors, while a differential local signal drives the second, fourth, sixth, and eighth transistors. Ninth and tenth transistors form a positive output section to produce a non-inverted output signal. Eleventh and twelfth transistors form a negative output section to produce an inverted output signal. The ninth to twelfth transistors are driven by the first to fourth signals, respectively.

Abstract: An amplified stepped gain mixer portion improves the signal-to-noise ratio of a receiver by using multiple gain states to improve linearity. The mixer portion includes an amplifier, a switch and two transistors. The amplifier output is coupled to the sources of the two transistors. An oscillating signal is present on the transistor gates. The transistor drains are coupled to one another through the switch when the switch is closed. The mixer portion operates in two modes. In a 1/2 mode, the mixer portion output current flows only through the first transistor and not through the second transistor because the switch is open. In a 2/2 mode, the mixer portion output current flows through both transistors. The mixer portion is configured such that the switch is closed when a switching signal is asserted. The switching signal is asserted when a bit of a mixer control register is written to.

Abstract: A voltage adder includes a first amplifier, a feedback resistor, and a control current source. The first amplifier includes a first input terminal to which a first voltage is input, a second input terminal connected to a feedback node, and an output terminal connected to an output node. The feedback resistor is connected between the output node and the feedback node. The control current source allows an addition current corresponding to a second voltage to flow through the feedback resistor.

Abstract: A clock regeneration circuit includes a half-bit delay device that outputs a half-bit delayed signal B of a multi-level input signal A, a one-bit delay device that outputs a one-bit delayed signal C of the signal A, an adder, an attenuator that forms an threshold signal, an XOR circuit, and a BPF that outputs a clock signal with a frequency corresponding to a bit rate of the XOR signal. The XOR signal is calculated as an XOR of a two-level input signal F, which is a logical zero when a level of the signal A is no more than a level of the threshold signal and otherwise is a logical one, and a two-level input signal G, which is a logical zero when a level of the signal B is no more than the level of the threshold signal and otherwise is a logical one.

Abstract: Method of driving an acoustic piezoelectric transducer (6) characterized in that a signal (8), resulting from the time multiplexing of at least two rectangular periodic signals (12a, 12b) of different frequencies and having pulses of fixed duration and whose duty cycle is less than 0.5, is applied to the terminals of the transducer (6). This signal may result from the time sum of at least two undulating logic signals of different durations.

Abstract: An electronic device includes a first mixer portion having a first stage and a second stage, and a second mixer portion having a first stage and a second stage. A first electrical path is coupled to the first mixer portion and the second mixer portion, and a second electrical path is coupled to the first mixer portion and the second mixer portion. The first mixer portion is adapted to receive a first input signal on the first stage and a second input signal on the second stage. The second mixer portion is adapted to receive the second input signal on the first stage and the first input signal on the second stage.

Abstract: The sampling circuit of the present invention includes a latch circuit 12 which latches the digital signal S1 at a constant period, an addition register 13 which adds the sampled data for the same input code, a divider 15 which divides the added value by a predetermined divisor, a digital memory which stores the divided value and outputs it at an arbitrary timing for a predetermined reading out number, an operator which operates the output data from the digital memory 16 in accordance with an algorism that is previously set, and a judgment circuit 13 which judges the operation result with a predetermined judgment criterion, and a control logic part 11 which controls such that the addition and outputting processing by the addition register 13 and the division and outputting processing by the divider 15 are carried out concurrently with the sampling processing that is performed by the latch circuit 12. Thereby, a sampling circuit in an AD converter or a DA converter that can reduce the inspection cost.

Abstract: Embodiments of a reduced noise reduction system (“RNFDS”) include a frequency divider and a resampler in signal communication with the frequency divider. The frequency divider receives an input signal and, in response, produces a divided signal. The input signal has a first frequency and the divided signal has a second frequency, different from the first frequency. The resampler receives the input signal and the divided signal, and resamples the divided signal using the input signal as a sampling clock signal to produce a resampled output signal. The frequency divider imposes edge jitter on the divided signal. Resampling the divided signal produces the resampled output signal with an edge jitter comparable with that of the input signal.

Abstract: A frequency converting circuit that outputs an output signal obtained by mixing a first input signal and a second input signal, has: a first input terminal to which the first input signal is input; a second input terminal to which the second input signal is input; an output terminal from which the output signal is output; a frequency converting element that has a first input part connected to the first input terminal and an output part connected to the output terminal, restricts the signal input to the first input part according to a signal input to a second input part and outputs the restricted signal to the output part; and a pulse controlling circuit that receives the second input signal via the second input terminal and outputs a pulse signal obtained by restricting the pulses of the second input signal to the second input part of the frequency converting element.

Abstract: By inputting differential signals to transistors Tr21a to Tr21d and Tr22a to Tr21d, an addition operation is performed on the four differential signals, and a filter operation is performed by a capacitor C21 and resistors R21 and R22. An offset of a signal obtained as a result of an addition operation performed on the four differential signals is removed by transistors Tr1 and Tr2.

Abstract: Provided are a mixer and a transceiver having the mixer. The mixer includes: an local oscillation (LO) differential signal generator converting an input LO signal into a differential signal; and a mixing unit receiving the LO differential signal as a first input and a first signal having a first frequency as a second input and performing differential amplification on the LO differential signal and the first signal to output a second signal having a second frequency.

Abstract: There are provided a wideband electric signal mixer capable of mixing two inputted electric signals having a wideband frequency spectrum. The wideband electric signal mixer includes an input terminal controlling an input interface and a phase of a differential signal of a first electric signal and a second electric signal, having a wideband spectrum; a signal mixing terminal comprising a transmission gate switch receiving and outputting the second electric signal and mixing the first electric signal with the second electric signal by turning the transmission gate switch on and off using the differential signal of the first electric signal passing through the input terminal; and an output terminal providing an output interface between a mixing signal outputted from the signal mixing terminal and an external circuit unit and amplification function of the mixing signal.

Abstract: The invention relates to a procedure and a circuit device for the subtraction of electrical signals, with at least two regulating loops each comprising at least one amplifier unit. Advantageously, the circuit device comprises a device for subtracting a signal, made available by the circuit device and representing the difference between the electrical signals, from one of the electrical signals. In a preferred embodiment of the invention, the potentials on lines carrying the electrical signals are maintained at the same value with the help of a first one or of the regulating loops.

Abstract: Provided is an adder in which all of circuits can be constituted by CMOS transistors, a process is simplified, and a chip size can be reduced as compared with a conventional art. The adder according to the present invention includes: a first VI converter and a second VI converter that allow a current corresponding to an input voltage to flow therein; and a current addition resistor having one end commonly connected to output terminals of the first VI converter and the second VI converter and another end grounded, which is adjustable in a resistance value.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: A signal processing method and apparatus reducing distortion using divided signals differing in only amplitude by weighting an input signal by first weights ki (i=1 to 4) to obtain divided signals, performing the same signal processing f(x) on the divided signals, weighting the signal processed divided signals by second weights l1 (i=1 to 4), and adding the divided signals Vout1 to Vout4 weighted by the second weights. The first weights are k1=t, k2=?t, k3=1, k4=?1, while the second weights are l1=?1, l2=1, l3=t3, l4=?t3. Here, t=b/a (where a and b are different positive integers).

Abstract: A current summing FIR filter can be implemented with multiple differential input stages and variable tail currents. The variable tail currents can be used to appropriately weight the present and previous digital input signals. The weighted outputs of the differential transistor pairs can be summed to provide a filtered output signal. The tail currents can be advantageously varied with variable current sources or by adjustment of the relative widths of the differential transistor pairs. In other embodiments, additional differential pairs can be added to adjust for systematic offset voltages caused by process-induced variations in the structure of circuit devices or to induce a desired offset.

Abstract: The calculating unit includes a dual rail input stage, a switching stage for a bit to be calculated and an output stage for an output bit, wherein the output stage provides a dual rail output. The switching stage is not implemented in dual rail technology but according to a “one-hot” realization. The switching stage includes at least one internal node which is, in the preparation mode according to a control signal on a control line from a control means, connected to a reference potential, while the node potential circuit for handling the internal node in the data mode is not active. Thus, an area-efficient, cross-current-reduced and reliable calculating unit is obtained, which may additionally be clocked at high speed, as a transition form a preparation mode to a data mode takes place without time-consuming discharge processes.

Abstract: The present invention relates to the field of electronics. More particularly, forms of the present invention relate to systems, methods and circuits for generating a signal. A system, method and circuit for generating a signal are described. Forms of this system, method and circuit provide clock duty cycle improvement with no frequency reduction. Some such forms provide a clock signal approaching or achieving 50 percent with no significant frequency departure, reduction, etc. from a generated clock. One form of the present invention uses two similar clock signals that oscillate at the same frequency, but effectively inverted one from another. In one such form, the inverted signals are generated with a voltage controlled oscillator having differential stages.

Abstract: A voltage source droop compensated clock modulation for microprocessors is described. Specifically, the circuit reduces the clock frequency if a voltage source droop is detected.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: Fine tuned signal phase adjustments are provided by multiple cascaded phase mixers. Each phase mixer outputs a signal having a phase between the phases of its two input signals. With each subsequent stage of phase mixers, the signals generated by the phase mixers have a smaller phase difference, thereby providing finer delay adjustments. Multiple stages of phase mixers can be provided in digital delay-locked loop circuitry to provide additional hierarchical delay adjustment.

Abstract: A reference voltage generator uses a conventional forward junction voltage generating device and a conventional thermal generator to generate a thermal voltage. The forward junction voltage and the thermal voltages have respective thermal sensitivities that act oppositely to each other so that, when the forward junction voltage is combined with the thermal voltage to produce a reference voltage, the reference voltage is substantially insensitive to temperature. The forward junction voltage and the thermal voltage are combined to produce the reference voltage in a manner that avoids generating any voltage having a magnitude that is greater than the magnitude of the sum of the forward voltage and the thermal voltage.

Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.