Abstract: The collector of the first transistor having the base to which the first signal input is supplied, is connected to the collector of the second transistor having the base to which the second signal input is supplied. The diode-connected third transistor is connected between the emitter of the first transistor and the output node, and the diode-connected fourth transistor is connected between the emitter of the second transistor and the output node. The first current mirror circuit supplies the current flowing in the constant current source to the emitters of the first and third transistors when the fifth transistor is in the ON state. The second current mirror circuit supplies the current flowing in the constant current source to the emitters of the second and fourth transistors when the sixth transistor is in the ON state.

Abstract: A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment.

Abstract: A switching circuit is made by serially connecting two field effect transistors in series in a small-signal transmission path, each of the transistors being applied with a substantially equal voltage, so as to lower a voltage applied to each of the FETs in the OFF state by voltage division, with the result that a high withstand voltage of the transmission path can be attained and a linear output can be obtained even when a large electric power is transmitted.

Abstract: A six-input multiplexer is disclosed using only two transistors in the signal path from an input port to the output port. The multiplexer uses control signals that are not decoded. The multiplexer uses three control signals and requires that the control signal combinations 000 and 111 not be used. The other six control signal combinations 001, 010, 011, 100, 101, and 110 can be used to select between six input signals by placing only two transistors in the signal path, taking advantage of the fact that two of the three control signals are the same and the third is different from the other two. A compact layout results when two multiplexers use common input signals.

Abstract: A temperature compensated logarithmic detector biased with a proportional to absolute temperature (PTAT) voltage produced in accordance with an area ratio of biasing transistors is disclosed. According to one implementation of the invention, the temperature compensated logarithmic detector includes biasing circuitry and a logarithmic detector cell. The biasing circuitry receives an input signal and produces a PTAT bias voltage from the input signal. The PTAT characteristic of the PTAT bias voltage is produced by an area ratio. The logarithmic detector cell converts the input signal to a logarithmic output signal in accordance with a logarithmic transfer function over a narrow range.

Abstract: A digital operand formatting stage that includes a first inverting means, a second inverting means having an input that is connected to the input of the first inverting means, and a third inverting means having an input that is connected to the output of the second inverting means, and an output that is connected to the output of the first inverting means. A first and third switching means are controlled by a first control signal and provide electrical connections between a positive voltage supply and the respective supply side of the first and third inverting means. A second and fourth switching means are controlled by a second control signal and provide electrical connections between a negative voltage supply and the respective ground sides of the first and third inverting means.

Abstract: A switching arrangement for establishing a signal path between any one of a plurality of first ports and a common port and for varying the attenuation of at least one of the ports comprises in the signal path of each attenuatable port a first switching element and attenuating circuitry connectable by further switching circuitry across the first switching element, the first switching element constituting the sole series element in that path. The attenuating circuitry comprises a resistive network and the further switching circuitry comprises second switching elements connected to respective ends of the first switching element and to respective points of the resistive network for introducing one of a number of resistive states into the signal path.

Abstract: A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.

Abstract: A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.

Abstract: An analog type multistage switching circuit with a small circuit size and a small consumed electric power to having a plurality of thresholding circuits arranged in parallel to which an input voltage and a reference voltage are impressed through capacitive couplings which add the input voltage and reference voltage with weighting.

Abstract: A redundancy passgate circuit is implemented in NMOS technology in order to provide a more rapid transmission of the transmitted signals. The circuit provides for the more rapid signal transmission by reducing the capacitance experienced by the input signals. The reduced capacitance loading is achieved at the expense of a greater layout area and a requirement for an on-chip power supply.

Abstract: A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: A multiplexer includes three switching divisions each of which has one terminal connected to each of the signal terminals and the other terminal connected to a fourth switching division. A signal inputted through the selected signal terminal is outputted from the other signal terminal to the exterior by operating the fourth switching division.

Abstract: A selector circuit is disclosed for a semiconductor memory circuit having a power circuit producing an internal power voltage lower than an external power voltage and including a reference voltage generator generating a reference voltage and a voltage source circuit responding to the reference voltage and supplying the internal power voltage to a memory cell array. The selector circuit includes a first input node connected to receive the reference voltage, a second input node connected to a terminal pad and an output line connected to the voltage source circuit, the terminal pad being supplied with a test voltage in a test mode of the memory circuit and brought into an open state in a normal operation mode of the memory circuit. The selector circuit responds the voltage at the second input node and forms an electrical path between the first input node and the output line in the test mode and between the second input node and the output line in the normal operation mode.

Abstract: A high frequency power amplifier is implemented by a GaAs FET and is supplied with a positive and a negative power supply. The amplifier amplifies the power of an input signal and delivers the amplified signal to a high frequency switch. The high frequency switch is supplied switch control voltages in the form of the positive and negative voltages. Since the switch control voltages are implemented as the positive and negative voltages, a great difference in level between the switch control voltages is achievable which improves insertion loss. While the high frequency switch may also be implemented by GaAs FETs, the insertion loss will be further reduced if the negative voltage is applied to the high frequency switch only during transmission. In this case, current consumption will also be reduced if the generation of the negative voltage is controlled at the negative voltage source side.

Abstract: Output signals from a plurality of self reset CMOS a logic circuits are multiplexed by means of the plurality of input multiplex circuits and an output circuit. The multiplex circuits are individually enabled by means of a select lead and true and complement input signals to the multiplex circuits are supplied to input terminals of an output circuit in which the state of the true or complement input is latched to provide a static output. The inputs to the output circuits simultaneously provide an output and initiate the setting of the latch by means of a separate latch setting gate. An inverter tree within the output circuit maintains the state of the output on the output terminal of the output circuit after the latch has been reset. A test access to the output circuit allows a test signal to be gated into a test latch and subsequently gated into the primary latch of the output circuit to provide a test output.

Abstract: A power supply circuit selectively provides various voltage signals to memory devices, such as EPROM or EEPROM for example. The power supply circuit receives voltage signals at input terminals and selectively outputs a voltage signal, in accordance with the requirement for reading, writing and erasing operations, while preventing leakage current between voltage signals. Among other things, the power supply circuit provides a relatively low impedance and does not require high voltage levels for performing the above memory operations. The selection of voltage signals at an output terminal is effected by control means for controlling conductivity and non-conductivity of MOS transistors based on a control signal supplied from a control signal input terminal.

Abstract: An interchip high speed I/O circuit having a low voltage swing and on-chip transmission line terminations. The present invention provides a high speed I/O circuit that uses a small voltage swing to keep power dissipation in the overall system to a minimum and particularly in the transmission line termination loads. A differential receiver circuit compares a data signal input to a reference signal, both sent from a driver chip, to determine the appropriate output response. Both the data signal and the reference signal are current controlled which reduces the di/dt noise generated by parasitic inductances.

Abstract: A mixer circuit (10) combines a buffered RF signal with the LO signal at the gate of a mixing transistor (20) for providing sum and difference product terms as the IF output signal. An inductor (46) provides a DC signal path between the source of the mixing transistor and the drain of the buffering transistor (14) to share the same operating current and thereby reduce power consumption in the mixer. The DC path inductor provides a high impedance to block the RF signal and LO signal. A bias circuit (26, 28) sets the bias point at the gate of the mixing transistor to a mid-point value between V.sub.DD and ground potential. In disable mode, the bias point of the mixing transistor is sufficiently low that the LO signal does not have sufficient power to turn on buffering and mixing transistors that could generate mixing products at the IF output.

Abstract: A radio receiver-transmitter apparatus equipped with a signal changeover switch which is capable of properly dealing with a high-power radio frequency signal and ensuring a desired insertion loss and superior isolation characteristic. The switch has a signal input terminal, a signal output terminal and a signal input-output terminal, and comprises a 1st FET unit connected to the input terminal and the input-output terminal, a 2nd FET unit connected to the input terminal and the ground, a 3rd FET unit connected to the output terminal and the input-output terminal, and a 4th FET unit connected to the output terminal and the ground.

Abstract: A latch circuit. The circuit includes a static digital logic circuit, comprising a multiplexer having a plurality of static input data lines and one or more select lines for selecting data from one of the input lines as multiplexer output data; latching means for latching output data from the multiplexer; wherein the multiplexer is not a static circuit.

Abstract: A supply voltage detect circuit is described which generates a control signal indicating the status of VCC to be at 5.0 or 3.3 volts. This control signal is used to generate analog reference signals used by A/D and/or D/A circuitry in an audio processing integrated circuit and by other circuitry to control clock frequencies or current drive.

Abstract: A programmable logic circuit having a routing matrix capable of providing 100% connectability and routability of a plurality of input signals to their appropriate configuration function blocks. In the present invention, input signals are first routed through the routing matrix before being processed by the input buffers. Thus, a slow user signal is processed by the relatively slow routing matrix before being provided with increased drive by the input buffers and passed on to the faster logical blocks. A number of programmable control bits are stored in SRAM. These control bits are decoded to determine which of the transmission gates of the routing matrix should be enabled. In this manner the input signal is routed to the appropriate configuration function block. Following the routing matrix is the input buffer. The highly driven output signal from the buffer is then passed to the configuration function block which performs the programmed logic functions on the signal.

Abstract: A small high speed averaging circuit includes a plurality of CMOS transistor pairs with substantially equal characteristics. Their voltage follower outputs are connected to a common output. A mean value is generated at the common output of the CMOS transistor pairs.

Abstract: An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Abstract: A power supply isolation and switching circuit formed in a semiconductor structure which eliminates a parasitic diode effect. The switching circuit receives a first power source and a second power source, and selects between the two sources to provide the selected power source to a load device. The switching circuit includes a first transistor, and second and third transistors. The first transistor is connected to the first power source for selecting the first power source as the supply voltage of the load device. The second and third transistors are connected in series to the second power source for selecting the second power source. The second and third transistors are formed in two separate wells of a first conductivity type that are spaced apart and isolated from each other by a semiconductor region of a second conductivity type different from the first conductivity type.

Abstract: An electronic circuit is provided with a first field effect transistor and a second field effect transistor, in which a drain of the first field effect transistor connected to a source of the second field effect transistor. This electronic circuit inputs a first signal to a gate electrode of the first field effect transistor, inputs a second signal to a gate electrode of the second field effect transistor and outputs a signal from a drain of the second field effect transistor. This electronic circuit is a cascode circuit related to the current drivability of the second field effect transistor is set to be larger than the current drivability of the first field effect transistor, and there is an effect that third-order or higher order distortion characteristics of a cascode type or dual-gate circuit can be reduced.

Abstract: The present invention relates mainly to distribution and/or processing devices for RF signals, in particular devices of the following types: signal combiner, signal splitter or divider, time multiplexer, time demultiplexer, frequency multiplexer, amplifier, attenuator, variable delay lines, and a vector modulator type circuit for signal shaping. A device of the invention comprises switching cells based on respective dual gate FETs, and a control signal generator that controls switching to enable the desired functions to be established.

Abstract: A data output circuit includes a P-channel transistor having a source connected to a supply voltage terminal V.sub.DD and a gate coupled to receive a drive signal from an internal circuit, and an N-channel transistor having its drain connected to the drain of the P-channel transistor and its source connected to an output terminal D.sub.out. The threshold voltage of the N-channel transistor is fixed to be lower than the thresholds of other N-channel transistors formed on the same substrate. A high level signal is output from the output terminal D.sub.out when a voltage output by the supply voltage terminal V.sub.DD is supplied to the output terminal D.sub.out through the P-channel transistor and the N-channel transistor. In this configuration; the output terminal charges quickly using the high driving capability of the N-channel transistor.

Abstract: An integrated circuit may have a mode to be switched over if a predetermined signal voltage is input through a mode switching terminal when the predetermined voltage is applied to one or more signal input terminals. The integrated circuit is provided with a voltage setting circuit disposed between the signal input terminal and the logic circuit, for setting the signal input terminal to receive any voltage in the range of a ground voltage to a power source voltage in response to a signal voltage input through the mode switching terminal.

Abstract: An antenna switching circuit comprises a first amplifier including a first FET receiving a first receive signal from a first antenna at a gate of the first FET, and amplifying the first receive signal, and outputting the amplified signal via a drain of the first FET to an output terminal, and a second amplifier including a second FET receiving a second receive signal from a second antenna at a gate of the second FET, and amplifying the second receive signal and outputting the amplified signal via a drain of the second FET to the output terminal. The first and second FETs are coupled to receive, at their sources, first and second control signals complementary to each other so that one of the FETs is made active while the other is made inactive, depending on values of the first and second control signals. The consumption current is reduced, and in addition, an amplifier in a receiver provided to receive the output of the antenna switching circuit may be omitted.

Abstract: A frequency conversion circuit for mixing first and second frequency signals to supply an output frequency signal comprises: first and second FETs having first and second gates for receiving the first and second frequency signals respectively; and a third FET having a third gate ac-grounded, the first to third FETs being connected in series such that a current flowing through the current circuit between the source and drain is controlled by the first to third gates, the third FET being provided between the first and second FETs. The third FET may also be provided between connection an end of the series connector and the second FET in accordance with frequency differences between the first and second frequency signals and between the second frequency signal and the output frequency signal. A triple gate FET can be used in place of these three FETs connected in series. A quad gate FET can be used also. A mixing circuit including the frequency conversion circuit mentioned above is also disclosed.

Abstract: A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

Abstract: A threshold circuit that uses capacitors to form a weighted sum of its inputs uses a two stage capacitor structure. The two stages form a compact structure that increases the number of input signals that can be handled and increases the flexibility in assigning the weights to the input signals. Capacitor electrodes for the input signals are arranged in two sets and the electrodes of each set are electrostatically coupled to first and second electrodes. Third and fourth electrodes, which extend from the first and second electrodes respectively, are electrostatically coupled to a unitary structure of fifth and sixth electrodes where their voltages are summed. The fifth and sixth electrodes are conductively connected to the gate of an FET threshold circuit that responds to the weighted and summed input signals.

Abstract: A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

Abstract: A design approach for a tree structure multiplexer produces a compact circuit layout by reducing the required number of transistors. The multiplexer is used to perform a binary decode of the input signals to generate a single selection of one of a number of potential outputs. since the inputs undergo a binary decode, the number of outputs is equal to 2.sup.x, where x is the number of inputs.

Abstract: A multiplexer circuit includes pairs of control elements such as CMOS transistors serially connected between common circuit nodes to conduct current therebetween in response to one of each pair of control elements being selectively biased to conductive or non-conductive states by an applied control signal. The current enabled to flow between circuit nodes through a pair of control elements biased to conductive state is determined by the magnitude of an applied signal, and a current-difference circuit compares the current flowing between circuit nodes with a reference current to produce an output signal representative of the applied signal which is selected in response to an applied control signal.

Abstract: A current steering switch circuit responsive to a CMOS signal. In an specific embodiment the switch is incorporated in a hybrid BiCMOS multiplexer circuit using combined CMOS and CML/ECL signal types. The high speed CML/ECL logic signals are multiplexed under the control of a lower speed CMOS signal. A particular aspect of the circuit is that a CMOS to CML/ECL converter is not used. Additionally, a differential, logic commutation signal is not required.

Abstract: A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs. Each output is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs and the other transistor of each pair having its gate connected to the inverse of the same input.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract: An apparatus includes a plurality of multiplication circuits for accurately performing small scale multiplication of analog signals with digital signals. The multiplication circuits (M0-M7) are arranged in parallel, receiving an analog signal (X) and bits of a digital signal B. Each circuit generates an output corresponding to a multiplication of the analog signal (X) with a digital bit (B0-B7), that output being based on a weight of the digital signal bit. The outputs generated by each respective multiplication circuit are capacitively coupled to produce an output indicative of multiplication between the digital signal and the analog signal. Each multiplication circuit includes a pair of transistors which receive a common digital signal, and which combine to have switching characteristics of a mutual toggle, alternatively opening and closing.

Abstract: There is provided a potential data selection circuit suitable for use, e.g., in a device for driving a liquid crystal pane adapted for selecting an arbitrary one of a plurality of potential data to output the selected one. This potential data selection circuit comprises: a sample-hold circuit adapted for sampling and holding selection data of at least 2 bits to output them, and a decoder adapted to receive the selection data from the sample-hold circuit to decode them to output control signals. The potential data selection circuit further comprises a multiplexer including analog switches adapted to respectively receive at least two potential data, and responsive to the control signals from the decoder to control the operations of the analog switches to select any one of the potential data to output the selected one, and an output circuit adapted to receive the selected potential data to output a signal of a voltage of the selected potential data to the exterior.

Abstract: In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.

Abstract: A multiplex system wherein each of the multiplex circuits includes a hold switch and hold capacitor, a standard class A differential amplifier with constant feeding current source, a multiplex switch to selectively isolate each multiplex circuit from the common multiplex line and a second current source supplying much larger current than the constant feeding current source selectively couplable in parallel with the constant feeding current source to the differential amplifier during periods when the differential amplifier is coupled to the common multiplex line.

Abstract: The complementary multiplexer includes a first pass-gate, formed from a single PMOS transistor, and a second pass-gate formed from a single NMOS transistor. The gates of the PMOS and NMOS transistors are connected directly to a select input line. No inversion of the select input signal is required. A compensation circuit is connected to outputs of the pass-gates for compensating any voltage differences between signals received through the first pass-gate as opposed to those received through the second pass-gate. Full CMOS and bi-CMOS implementations are described herein. An exclusive OR-gate circuit, incorporating a bi-CMOS implementation of the multiplexer, is also described herein.