Abstract: An apparatus and method permits quick response to a transition at an input port and subsequent propagation of the transition to the output port while being able to process a wide variety of input signal properties. A receiver apparatus comprises at least first and second receivers, each receiver accepting an input signal and tuned for optimal response to a set of known input signal properties. Either first and second primary transition propagation elements or secondary transition propagation element propagates a first transition from one of the receivers. A universal transition propagation element propagates the first transition to an output. A pass gate receives a signal based upon the output and inhibits transmission of the signal based upon the output until the first and second intermediate signals are equivalent whereupon the pass gate is placed in low impedance state permitting the signal based upon the output to be held in a storage node as the preset signal.

Abstract: A circuit to power multiple load elements is presented. Fewer discrete components and fewer output terminals are required to power multiple devices. A single high-power DC boost circuit powers multiple AC devices. An end-user can selectively power a subset of the AC devices electrically connected to the present invention. The circuit includes a first and second reference voltage terminal, and a first, second, and third switch. The circuit also includes a first control switch and a second control switch in electrical communication with the first switch and the second switch, respectively. The first control switch provides either a first control signal or a second control signal to a control terminal of the first switch. Similarly, the second control switch provides either the first control signal or the second control signal to a control terminal of the third switch.

Abstract: A power supply circuit receiving several supply voltages on respective switches, at least one of the switches being a first PMOS transistor connected between one of the supply voltages and a common output terminal, this switch being associated with a second PMOS transistor connected between the gate of the first transistor and a power supply node maintained at the highest of the other supply voltages, with a third NMOS transistor, which is less conductive in the on state than the second transistor, connected between the gate of the first transistor and the ground, and with a fourth PMOS transistor having its source connected to the power supply line of the switch and its drain connected to ground via a current source, and to the gates of the second, third, and fourth transistors.

Abstract: A novel RF switch circuit and method for switching RF signals is described. The RF switch circuit is fabricated in a silicon-on-insulator (SOI) technology. The RF switch includes pairs of switching and shunting transistor groupings used to alternatively couple RF input signals to a common RF node. The switching and shunting transistor grouping pairs are controlled by a switching control voltage (SW) and its inverse (SW_). The switching and shunting transistor groupings comprise one or more MOSFET transistors connected together in a “stacked” or serial configuration. The stacking of transistor grouping devices, and associated gate resistors, increase the breakdown voltage across the series connected switch transistors and operate to improve RF switch compression. A fully integrated RF switch is described including digital control logic and a negative voltage generator integrated together with the RF switch elements.

Abstract: At an integrated analog multiplexer with several multiplexer inputs, a multiplexer output, a switch device and a difference amplifier with an inverting and a non-inverting amplifier input as well as an amplifier output the amplifier output forms the multiplexer output, the difference amplifier is connected as inverting amplifier by means of a feedback branch from the amplifier output to the inverting amplifier input and the switch device selectively connects one of the multiplexer inputs with the inverting amplifier input.

Abstract: In one embodiment, N transmission gates having N outputs transfer one of N pattern inputs to a first output based on an active signal from N select signals. The N outputs are connected together to form the first output and has an output capacitance. An amplifier circuit having a gain is coupled to the N transmission gates at the first output to reduce the output capacitance by an amount approximately equal to the gain. The amplifier circuit generates an output signal.

Abstract: A dynamic logic multiplexer has pull-ups on its input signals that pull-up the input signals when not selected. This reduces leakage current that may contribute to incorrect switching of the output. The output stage of the multiplexer includes a latched dynamic node followed by two gain stages, and an open-drain output.

Abstract: Timing difference division circuit with a high operating speed and a small area, assuring broadband operation. The circuit includes a logic circuit L1 generating a first gate signal and a second gate signal based on a first input signal and a second input signal, a first switch element connected across a first power source and an inner node and having a control terminal to which is fed the first gate signal, a first series circuit made up of a second switch element and a first constant current source and a second series circuit made up of a third switch element and a second constant current source. The first and second series circuits are connected in parallel across the inner node and the second power source. The first and second gate signals are connected to control terminals of the second and third switches, respectively.

Abstract: An apparatus and method provide an apparatus and method for reducing noise production and power consumption in a logic device that uses monotonic logic encoded signals. In particular, the apparatus is accomplished by a recode circuitry that receives and recodes a monotonic logic encoded signal received from a first logic circuit in the logic device, into a reduced switching signal. The recode circuitry sends the reduced switching signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching signal back into a monotonic logic encoded signal. The decode circuitry then sends the monotonic logic encoded signal to a second logic circuit in the logic device. The method is accomplished by receiving a monotonic logic encoded signal from a first logic circuit. The monotonic logic encoded signal is converted into a reduced switching signal and transmitted. The reduced switching signal is received and converted back into the monotonic logic encoded signal.

Abstract: The present invention provides a highly efficient power supply with redundant multiple input voltage sources. The power supply uses switching transistors, specifically MOSFET's, to create paths for current from one of the voltage sources to the load. The switching transistors are switched either “on” or “off” by comparators which compare the output from the voltage sources. These comparators allow the highest voltage source to provide power to the load, and keep the other switching transistors “off” that connect the common load to other voltage sources. Because the switching transistors have lower conduction losses than diodes in conventional power supplies, the power supply in accordance with the present invention is more efficient.

Abstract: A high-speed bank select multiplexer latch may be coupled to a pair of differential output nodes and configured to capture and retain an output on the pair of differential output nodes responsive to two or more pairs of differential data inputs being active. A first subcircuit including a first N-channel transistor and a second N-channel transistor is configured to receive at least a first input signal and a second input signal and to drive a first output on a first output node responsive to either of the first input signal or the second input signal being active. Additionally, a second subcircuit including a third N-channel transistor and a fourth N-channel transistor is configured to receive at least a third input signal and a fourth input signal and to drive a second output on a second output node responsive to either of the third input signal or the fourth input signal being active.

Abstract: A signal from a crystal resonator or an external clock signal are input from terminals xta1 or exta1, and the signal from the crystal resonator or external clock signal are selected by mode terminal mod8 and input to an oscillator OSC. An input clock signal ckl1 is frequency-divided to desired values by a divider DIV1. A divided clock signal clk2 is input as the reference clock of a phase-locked loop PLL1 or delay-locked loop DLL1, and a clock signal output by a circuit selected by a selector SEL3 passes via a divider DIV2 to be distributed to an LSI. The phase-locked loop PLL1 has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL1 is 2-3 periods.

Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.

Abstract: A high-speed multiplexer that includes a reduced number of components in the pull-up and/or the pull-down circuits operates faster than conventional multiplexers and can process higher frequency input signals. The pull-up circuit may be a singe p-type MOSFET transistor and the pull-down circuit may be a single n-type MOSFET transistor. The switching circuits may include transistor-based NOR gates. The multiplexer may have numerous channels, for example 2 to 256 or more channels.

Abstract: A switched current steering device includes a switch activation unit coupled to a set of actual switches and an associated set of dummy switches. Based upon current actual switch states, next actual switch states as specified by a data stream, and current dummy switch states, the switch activation unit selectively generates dummy signals that indicate or specify next dummy switch states. The switch activation unit generates the dummy signals such that the total number of actual switches and dummy switches experiencing state transitions remains constant from one switching cycle to another.

Abstract: Disclosed is a low-power data transfer circuit having a high data transfer rate. This data transfer circuit of the invention includes a first selection circuit for selecting two signal lines out of three signal lines and precharging the remaining signal line to a first potential; and a second selection circuit for selecting and connecting the two data signal lines selected by the first selection circuit to a reception side circuit. With the configuration, a period of precharging a signal line is included in a data transfer period. Thus, there is no need to provide a specific precharge period after data transfer, and data can be transferred effectively.

Abstract: A high-speed multiplexer that includes a reduced number of components in the pull-up and/or the pull-down circuits operates faster than conventional multiplexers and can process higher frequency input signals. The pull-up circuit may be a singe p-type MOSFET transistor and the pull-down circuit may be a single n-type MOSFET transistor. The switching circuits may include transistor-based NOR gates. The multiplexer may have numerous channels, for example 2 to 256 or more channels.

Abstract: A programmable switch includes at least one or more pass transistors having a control voltage that is greater than the data path reference voltage that is selected by a corresponding pass transistor. The control voltage is provided by a higher voltage power supply than the power supply that provides the data path reference voltage. In one embodiment, the higher voltage supply is a quiet supply that is not loaded with devices that switch during normal operation of the programmable switch such as CMOS devices. In another embodiment, the power supply that provides a voltage to an I/O circuit of the probable switch is the power supply that is utilized to provide the control voltage to the pass transistors. In a particular embodiment, the pass transistors comprise higher voltage tolerant devices than other devices in the programmable device. In a particular embodiment, the higher voltage supply is at least the data path reference voltage plus the threshold voltage of the pass transistors.

Abstract: A plurality of the P-channel transistors of Group A and a plurality of P-channel transistors of Group B are connected between the power-supply-voltage VCC and the ground, and an output signal SUBUP is obtained from the node C via two inverters. Each terminal of. Transistors of Group B is connected to the ground via N-channel first, second and third transistors. The first signals &phgr;1 and &phgr;2 are inputted to the gates of the first and second transistors and the output of the NOR logical circuit is inputted to the gate of the third transistor. Current performance of the P-channel transistors of Group B is adjusted to control the substrate voltage and to make the substrate voltage both higher and lower than that of normal operation by the use of the test modes. So, the substrate voltage can be changed during hold tests in a selection process to accelerate the tests and shorten the selection time.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes a same-gate symmetrical design and reverse polarity control signals to overcome disadvantages of prior circuits while accommodating increasing circuit speeds. The circuit employs all NAND gates on the select lines controlling multiplexer transmission gates rather than NAND gates and a NOR gate. The design may also be implemented using AND gates. In addition to using a NAND gate where prior designs use a NOR gate, the polarity of the flip-flop output which drives the additional NAND gate is inverted, and the polarity of the input to the transmission gate driven by the additional NAND gate is also inverted. The circuit thus provides a symmetric design using the same NAND logic gates on all select lines while preserving functionality of the n-to-1 multiplexer.

Abstract: A multiplexor circuit for performing time-division-multiplexing comprises two or more input signal pairs comprising individual signal lines for providing timed data input into the multiplexor circuit, the pairs alternately selectable for operation, two or more select lines for selecting alternate ones of the input signal pairs during operation, one or more output lines comprising signal output of the circuit and two or more resistive output loads and associated electronic gates. When a specific input pair is not selected for output, the not-selected input pair is not directly connected to the output lines of the circuit but is instead connected to individual ones of the resistive output loads enabled by the associated gates.

Abstract: A multiplexor circuit for performing time-division-multiplexing comprises two or more input signal pairs comprising individual signal lines for providing timed data input into the multiplexor circuit, the pairs alternately selectable for operation, two or more select lines for selecting alternate ones of the input signal pairs during operation, one or more output lines comprising signal output of the circuit and two or more resistive output loads and associated electronic gates. When a specific input pair is not selected for output, the not-selected input pair is not directly connected to the output lines of the circuit but is instead connected to individual ones of the resistive output loads enabled by the associated gates.

Abstract: A multiple voltage supply switch is disclosed. The multiple voltage supply switch includes a plurality of switching device pairs. Each switching device pair is connectable between an associated one of a plurality of voltage supplies and an output of the switch. Each switching device pair includes a first switching device connected to the associated one of the plurality of voltage supplies and a second switching device connected in series between the first switching device and the output of the switch. Both the first and second switching devices are activated to connect the associated one of the voltage supplies to the output of the switch and at least one of the first or the second switching devices of each of the other switching device pairs are inactivated to disconnect the voltage supply associated with the other switching device pairs from the output of the switch.

Abstract: A semiconductor device that operates at high speed using a low voltage power source, in which the output of each gate in the standby state is stable, and which has a delay time that is not affected by the frequency of the input signal. TrQ1 to TrQ8, which form multiple stages of the inverters are designed to have a low threshold voltage in order to accomplish low voltage operation. When input node A is at “L” in the standby state, TrQ2, Q3, Q6, and Q8 which cut-off are connected to high threshold voltage TrQn1 and Qp1. In the standby state, power cutting TrQn1 and Qp1 cut off in accordance with chip selecting signals CS, /CS, thereby blocking the flow of sub-threshold current to TrQ1˜Q8. Since TrQ1, Q4, Q5 and Q8 are not cut off at this time, the output potential of each inverter is stable.

Abstract: An apparatus and method for boosting a transmission gate by charging a pair of capacitors and using the coupling effect of that pair of capacitors to overdrive the gate inputs of NMOS and PMOS transistors of a transmission gate to turn on the transistors more strongly and speed the passage of data signals.

Abstract: A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit.

Abstract: A MOSFET operating as a mixer has its drain biased at the knee of the ID vs VDS characteristic. A local oscillator voltage is applied to the gate and a RF signal voltage is applied to the drain through a singled-ended source follower. The nonlinear curvature at the knee produces a beat frequency current. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Conversely, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: A circuit for selectively enabling one circuit from among a plurality of circuit alternatives of an integrated circuit, comprising selection circuit means for selecting one among said circuit alternatives. The selection means are controlled by bistable circuit means having a preferred state. Disactivatable forcing means associated to said bistable means are provided for forcing said bistable means in a state opposite than said preferred state, so that when said forcing means are disactivated the bistable circuit means automatically switch to said preferred state.

Abstract: An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (VPP) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of VCC. The VPP voltage and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up.

Abstract: A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.

Abstract: Presented is a low-voltage automatic lock-up biasing circuit with input terminals that accept input voltages, and with an internal node coupled to both input terminals an which takes take the highest of the voltage values applied to the input terminals. This circuit uses a comparator having respective inputs connected to the input terminals and with an output connected to a level shifter. Outputs of the level shifter are coupled to respective enable elements connected between each input terminal and the internal node. The enable elements are driven each by a respective output of the level shifter.

Abstract: An integrated circuit may include matched cells each having an active transconductor, wherein the matched cells are coupled together through respective active transconductor circuits to average the effect of comparator input-referred offsets. Each cell of the matched cells may have a first differential gain stage coupled to a second differential gain stage that is coupled to an output buffer stage, and an associated active transconductor circuit. The active transconductor of each cell is coupled to the gain stage of other cells to average the effect of cell mismatches.

Abstract: A high performance interconnect that utilizes dynamic driver technology is capable of reduced power operation during periods of low data switching activity. Circuitry is provided that limits the performance of an evaluation operation in the dynamic driver circuitry to clock cycles during which a present input bit of the interconnect differs from a previous input bit. Thus, the evaluation operation and subsequent precharge of the driver output is performed sparingly during periods of low data switching activity. An output circuit is also provided for decoding the data stream flowing through the interconnect at the receiver end thereof. Using the principles of the present invention, it is possible to achieve the performance advantages of dynamic drivers with the switching activity of interconnects that use static CMOS technology.

Abstract: A look-up table circuit implemented with MOS transistors that uses combinational logic to generate signals that enable the transistors. A circuit using 16 inputs and 4 select lines is disclosed. Two of the select lines are used as inputs to combinational logic including four NOR gates to generate enable signals for transistors in a third stage of the circuit. This produces a reduction in the propagation delay of a signal from the input to the output of the look-up table circuit.

Abstract: A semiconductor device comprises an analog switch and digital circuitry, both of which are formed on a single integrated circuit chip and share a node coupled to external circuitry. A first power source, provided in the device, is coupled to an input terminal of the analog switch whose output is operatively coupled to the node, and a second power source is also provided so as to supply electric power to the digital circuitry whose input or output is operatively coupled to the node. A back gate voltage controller, coupled to a back gate of the analog switch, is provided in order to control a voltage applied to the back gate in response to an operation mode control signal for determining whether the analog switch or the digital circuitry is to be enabled.

Abstract: The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.

Abstract: This application proposes a new logic circuit including the 1st selector (S1) in which the control input S is controlled by the first input signal (IN1), the input I1 or I0 is controlled by the second input signal (IN2), and the output O is connected to the first node (N1), and the 3rd selector (S3) in which the control input S is controlled by the first node (N1), the input I1 is controlled by the third input signal (IN3), the input I0 is controlled by the first input signal (IN1), and the output is connected to the first output signal (OUT1).

Abstract: A circuit for switching digital signals on a plurality of signal lines where signals on different signals line may have different signal rates includes a controller that prevents a switch from being turned off until after another switch is stably turned ON. This allows more than one switch at a time to supply a correspondingly received digital signal to an output. Substantially identical digital signals may be supplied to two inputs of such a circuit while the circuit is switched between the respective inputs. The circuit may be driven by an encoder that supplies encoded signals without recursion but that conforms to encoding conventionally supplied by recursion. The encoder may be implemented in parallel configuration for rapid encoding of a signal, and may be implanted to perform a data strobe signal encoding conforming to IEEE standard 1394.

Abstract: The invention relates to a fast signal selector having a plurality of transfer gates which are connected in parallel. The input signals are applied to the signal inputs of the transfer gates and a selection signal is applied to control inputs of the transfer gates. Due to the switching properties of the transfer gates, the input signals can be switched through onto a common output line essentially without any power loss and with a very short time delay of approximately 20 ps.

Abstract: A digital electronic circuit having first and second sections. The first section is adapted to transmit one of N input signals. The second section is adapted to receive the signal transmitted by the first section and one or more control signals. The second section is configured to output either an inverse of the signal transmitted by the first section or a logical 0, or to output either an inverse of the signal transmitted by the first section or a logical 1. The second section also may be selectively configurable.

Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

Abstract: An integrated circuit chip having formed thereon a voltage control circuit supply adapted to provide one of a pair of voltages selectively in accordance with an operating mode of the circuit. The circuit includes a comparator circuit fed by the pair of voltage sources. A first switch is controlled by the comparator circuit. A first one of the pair of voltage sources is fed through a second switch which may be a transistor or a diode. An input of the first switch is fed to a second one of the pair of voltage sources.

Abstract: A parallel multiplier includes m multiplexers and a plurality of adders. The multiplexers receive an n-bit multiplicand and n-bit zero (0) through two input terminals, respectively, and one (1) bit of a m-bit multiplier through a select terminal to selectively output the n-bit multiplicand when the one bit of the m-bit multiplier is “1 ” and the n-bit zero (0) when the one bit of the m-bit multiplier is “0”. The adders receive two of the n-bit output data from the multiplexers to output an n+2 bit partial product or an n+m bit product by adding two neighboring output data from the multiplexers after 1 bit downshifting the (less significant) neighboring output data corresponding to the less significant bit of the m-bit multiplier. A final adder can output an n+m bit product by adding two (n+x bit) partial products after downshifting a selected one.

Abstract: A real-time standby voltage adjustment circuit includes a switch control circuit controlled by a power saving control signal provided by a personal computer for generating a switch signal. A switch device is controlled by the switch signal for receiving a working voltage provided by a power supply of the personal computer and selectively outputting the same. A converting control circuit receives an adjust voltage signal generated by an adjustment and switch circuit. The converting control circuit is controlled by the power saving control signal for applying the adjust voltage signal back to the adjustment and switch circuit thereby controlling the adjustment and switch circuit to adjust a standby voltage provided by the power supply and output an adjusted standby voltage.

Abstract: To provide an antenna unit that can always provide good broadcast transmission reception and a signal switching circuit to be used therein. A first antenna element for receiving satellite broadcast transmissions, a second antenna element for receiving VHF terrestrial broadcast transmissions, and a switching means for selectively switching output of either a reception signal of the satellite broadcast transmissions received by the first antenna element or a reception signal of the VHF terrestrial broadcast transmissions received by the second antenna element and supplying that output to the receiver unit via the signal supply cable in response to a direct-current bias level supplied from a receiver unit via a signal supply cable are provided inside a single identical casing.

Abstract: Circuit for discharging to ground, supplied by a supply voltage, comprising a reference voltage, a negative potential node, first circuitry adapted to couple the negative potential node to the reference voltage in response to a control signal. Second circuitry is provided adapted to determine in the first circuitry the passage of a controlled current for the discharge of the negative potential node.

Abstract: A circuit arrangement for generating an output signal at an output by combining at least a first and a second input signal, includes controllable switches for applying a respective one of the input signals to the output, in which, for the purpose of switching the output from one of the input signals to the other, a first one of the controllable switches is gradually switched from the blocked to the conducting state and a second one of the controllable switches is switched complementarily thereto from the conducting to the blocked state. To implement such a circuit arrangement in such a way that distortions produced by tolerances and inaccuracies in matching the characteristics of the components used for switching can be avoided, while using a small number of components, the controllable switches are switched oppositely to each other between their completely conducting and their completely blocked state with a mutually complementary, gradually changed duty cycle.

Abstract: A circuit comprising a plurality of input devices, a plurality of select devices and a selector device. The plurality of inputs may each be configured to receive an input. The plurality of select devices may each be configured to present an output in response (i) one of said plurality of inputs and (ii) one of a plurality of select signals. The selector device may be configured to present the plurality of select signals, where only one of the select signals is active at a time.