Abstract: A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.

Abstract: A frequency coincidence detection circuit for detecting frequency edges for each of a plurality of periodic digital signals. The circuit generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The circuit determines a signal coincidence of the coincidence windows. In another embodiment, a frequency coincidence detection method is provided. The method detects frequency edges for each of a plurality of periodic digital signals, generates count indicators for each of the periodic digital signals and compares each of the count indicators to a programmable sensitivity input to determine a coincidence window for the corresponding one of each of the periodic digital signals. The method determines a signal coincidence of the coincidence windows.

Abstract: A comparator circuit for reducing current consumption in a low consumption mode while suppressing the generation of glitches during a transitional period. The comparator circuit includes a comparison core circuit unit, a monitor circuit unit formed by a first transistor, and a nonlinear amplification circuit. The comparison core circuit includes second and third transistors connected to a constant current source. The source terminal and gate terminal of the first transistor have the same connection as the source terminal and gate terminal of the third transistor. The current flowing to the first transistor is supplied to the nonlinear amplification circuit. The nonlinear amplification circuit amplifies the supplied current with an incorporated constant current source and supplies the amplified current to the source terminals of the second and third transistors of the comparison core circuit.

Abstract: An integrated circuit includes a first switched capacitor element and a second switched capacitor element, which are coupled to form a bridge circuit, the first switched capacitor element being located in a first branch of the bridge circuit and the second switched capacitor element being located in a second branch of the bridge circuit. A detector circuit is coupled to the first branch and to the second branch of the bridge circuit. Switching signals of the first switched capacitor element and of the second switched capacitor element are generated on the basis of an input clock signal of the integrated circuit.

Abstract: Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal.

Abstract: A phase/frequency comparator is described which includes two edge-triggered storage elements, each set by an edge of a reference frequency signal of a phase—or frequency-locked loop (PLL) and by an edge of an output frequency signal of the PLL. The storage elements are each reset by an output signal of a resetting logic unit, which is activated when both output signals of the storage elements are activated and then deactivated when the output signals are deactivated.

Abstract: A transmission circuit, which transmits a differential signal having pulse time larger than a predetermined minimum pulse time, includes: a driving unit for feeding the differential signal as a potential difference between two transmission lines; a driven unit for operating on the basis of the differential signal by receiving the differential signal by the potential difference between the two transmission lines; and a connecting resistor for electrically connecting the two transmission lines. Further, a connecting MOS transistor may be provided near a receiving end of the driven unit.

Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: A phase-controlled current source for phase-locked loop is provided. The phase-locked loop includes a voltage-controlled oscillator to associate a charging path or discharging path in order to generate an output signal and the output signal is further sensed so as to generate a loop signal. The phase-controlled current source includes a status memory receiving the loop signal and the reference signal so as to output an energy-triggering/energy-removing signal; and a controllable current source, under the control by energy-triggering/energy-removing signal so as to decide whether a charging and discharging action should be performed, wherein after the charging action or discharging action is decided, the charging path or the discharging path is generated through the reference signal and the loop signal.

Abstract: Disclosed are a digital phase-frequency detector and a method of operating a digital phase-frequency detector. The detector includes an input circuit, an output circuit and a reset circuit. In use, the input circuit receives first and second input signals during a plurality of cycles, and during a given one of the cycles, generates a first intermediate signal or a second intermediate signal depending on which of the first and second input signals was received first during that given one of said cycles. The output circuit receives these intermediate signals, and outputs, during said one cycle, a first output signal or a second output signal depending on which one of intermediate signals was received by the output circuit during said one cycle. The reset circuit applies a reset signal to the input circuit under defined conditions to begin a new one of said plurality of cycles.

Abstract: A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sensing devices, and a reset control circuit. The sensing devices control the pulse generators based on signals received at corresponding first ends of the sensing devices. The inverting circuits generate signals to the first and second output ends of the phase-frequency detector based on signals received at corresponding first ends of the inverting circuits. The reset control circuit generates reset signals based on signals received at the first and second output ends of the phase-frequency detector.

Abstract: The phase-frequency detector may include a first flip-flop configured to generate a first signal, the first signal transitioning to a first logic level in response to a first edge of a first input signal and transitioning to a second logic level in response to a delayed reset signal and a second flip-flop configured to generate a second signal, the second signal transitioning to the first logic level in response to a second edge of a second input signal and transitioning to the second logic level in response to the delayed reset signal. The phase-frequency detector may further include a first delay unit configured to delay a reset signal to generate the delayed reset signal and a second delay unit configured to delay the reset signal to generate an output control signal for adjusting at least one of the first and second signals.

Abstract: A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detector.

Abstract: A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a clock counter, operative to count all pulses, in any one of the clocks, that occur within the duration of the reference window and to output a corresponding pulse count. The FMC further includes two or more comparators, each operative to compare the pulse count with a respective given threshold value and to output a corresponding indication of frequency deviation. In one configuration, in which the clock is generated on the chip by a frequency multiplier, the reference window generator and the clock counter are shared between the frequency monitor circuit and the frequency multiplier.

Abstract: Additional information on the phase of an external clock signal is obtained by using clock signals to determine if a phase difference between an external clock signal and a first internal sampling clock signal is less than a pre-selected value. If the system determines that the phase difference is less than a pre-selected value, one embodiment samples the incoming data with a second internal sampling clock signal, having a selected phase relationship to the first internal sampling clock signal, such as ½ a clock period out of phase. By maintaining sufficient phase difference between the active edge of the external clock and the active edge of the internal sampling clock, the embodiment provides a sufficient setup/hold margin to avoid a metastability or other problem in a subsystem receiving data across an asynchronous boundary.

Abstract: A testing circuit includes m block test units and a first logical processing unit. The block test unit compares a first data outputted from a test object with a reference data, and outputs a result as a test circuit output signal based on a output control signal. The first logical processing unit judges whether the all of the m test circuit output signals indicate that the first data is coincident with the reference data, and outputs a result as a total judgment result signal based on the m test circuit output signals. The block test unit includes a block judging unit and a block output selecting unit. The block judging unit compares the first data with the reference data to judge whether the first data is coincident with the reference data, and outputs a result as a block judgment result signal.

Abstract: The comparator circuit includes an amplifier amplifying a voltage signal inputted from outside, a voltage dividing circuit dividing down a power supply voltage supplied from outside, thereby producing a reference voltage, a waveform dull circuit dulling the reference voltage, and a comparator comparing a voltage of the input voltage signal amplified by the amplifier with the reference voltage dulled by the waveform dull circuit.

Abstract: A method which provides a very simple way of forming a control signal if the frequencies differ too greatly from one another between a useful signal and a reference signal. A control signal is produced which indicates that the frequency error between the frequencies of a useful signal and the frequency of a reference signal exceeds a prescribed error limit value, where the useful signal and the reference signal are used to produce a pulsed signal whose pulse length is proportional to the frequency difference between the useful signal and the reference signal. The pulse length is then compared with a prescribed maximum pulse length, and the control signal is produced if the pulse length exceeds the prescribed maximum pulse length.

Abstract: A differential-to-single-ended (DSE) converter receives a positive differential input and a negative differential input and generates a single-ended output. The DSE converter comprises: 1) a first comparator having a non-inverting input coupled to the positive differential input and an inverting input coupled to the negative differential input; 2) a second comparator having an inverting input coupled to the positive differential input and a non-inverting input coupled to the negative differential input; 3) a first D flip-flop having a Logic 1 input and clocked by a rising edge on the first comparator output; 4) a second D flip-flop having a Logic 1 input and clocked by a rising edge on the second comparator output; and 5) a latch circuit having a first input coupled to the first D flip-flop output and a second input coupled to the second D flip-flop output. Rising edges on the first and second D flip-flop outputs cause the latch output to change state.

Abstract: In a phase sync circuit (40) which extracts a clock signal CK from a data signal D in a random NRZ format, particularly in a phase sync circuit (40) of a dual loop configuration including both a phase comparison circuit (81) and a frequency comparison circuit (10), a phase sync circuit (40) capable of achieving both broadening of the capture range and extraction of a high-quality clock signal without requiring any reference clock signal is provided. A clock signal Ca, another clock signal Cb having a phase delayed by an approximately ¼ period from the clock signal Ca and the data signal D are input to the frequency comparison circuit (10) to output a logical value according to the high-low relationship between the frequency of the clock signal and the bit rate of the data signal D.

Abstract: A fully differential phase and frequency detector utilizes a multi-function differential logic gate to implement a differential AND gate operation and provides a fully differential D-flip-flop. The multi-function differential logic gate has four inputs, which can be grouped into two pairs of true and complement signals. By selectively re-assigning the inputs to different signal pairs, the differential logic gate can be made to provide one of either simultaneous AND/NAND logic operations or simultaneous OR/NOR logic operations. The differential D-flip-flop is implemented following a master/slave configuration and is response to the true and complement forms of an input clock signal, an input reset input, and input data signal, and also provides true and complement forms of an output signal. All components within the phase and frequency detector are exemplified in CML circuit configuration.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A frequency discriminators (FD) and frequency modulation (FM) demodulators, utilizing single sideband (SSB) complex conversion directly to zero IF, suitable for direct demodulation at high frequencies of analog FM or digital FSK modulated signals, as well as for high speed frequency discrimination (or frequency comparison) in applications such as frequency acquisition in frequency synthesizers. The complex SSB down-converter consists of a quad of mixers and quadrature splitters in both the signal path and local oscillator (LO) path. Each mixer receives both the signal and the LO, each either in-phase or quadrature. The outputs of mixers are combined in pairs, to produce the SSB in-phase (I) baseband signal and the SSB quadrature (Q) baseband signal. Both I and Q signals are then delayed, each multiplied by un-delayed version of the other one. The multiplication products are summed together, to produce an FD error signal, or an FM demodulated signal at the output.

Abstract: An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequency divider divides the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal. A frequency comparator compares frequencies of the beat waveform signal and the divided reference-clock signal, and generates a step out alarm signal which is a binary signal depending upon a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal.

Abstract: A system and method for utilizing a feedback-based delay stabilization and power optimization circuit. One embodiment of the present invention is directed to an electronic circuit comprising an indicator operable to generate an indicator signal that is proportional to an actual operating speed of an integrated circuit that includes the indicator; and a comparator operable to compare the indicator signal to a reference signal and to generate from the comparison an error signal that is proportional to a difference between the operating speed and a desired operating speed. A signal combining circuit may then generate a feedback signal for a power supply based upon the error signal and an output signal of the power supply.

Abstract: An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequency divider divides the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal. A frequency comparator compares frequencies of the beat waveform signal and the divided reference-clock signal, and generates a step out alarm signal which is a binary signal depending upon a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal.

Abstract: An integrated circuit according to the present invention includes application-specific circuitry and an embedded counter assembly capable of measuring the frequency of one or more clock signals, which may be generated internally by the integrated circuit or externally by one or more sources external to the integrated circuit. The embedded counter assembly utilizes a reference clock signal having known characteristics, and measures the frequency of an unknown clock signal based upon the reference clock signal. The embedded counter assembly is capable of measuring the frequency of internal clock signals that are otherwise inaccessible via external output pins.

Abstract: A frequency detector circuit is arranged to detect a frequency difference between a clock signal and a reference clock signal. The frequency detector circuit includes four flip-flop circuits and a clear logic circuit. The clear logic circuit is arranged to clear selected flip-flop circuits. Two of the flip-flop circuits are arranged to detect two consecutive transitions in the clock signal without a clearing signal to provide a DOWN signal. The other two flip-flop circuits are arranged to detect two consecutive transitions in the reference clock signal without a clearing signal to provide an UP signal. The average of the UP and DOWN signals over a time interval corresponds to the difference in frequency between the clock signal and the reference clock signal. The UP and DOWN signals provide signals that may be employed by a charge pump circuit in a phase-locked-loop system to adjust the frequency of a VCO.

Abstract: Frequency multiplying circuitry includes a couple of integrator circuits. The one integrator circuit charges a capacitor with a larger time constant via a resistor when an input clock signal is in its high level and then discharges it with a smaller time constant when the clock signal is in its low level. The other integrator circuit charges and discharges its capacitor in the opposite manner to the one integrator circuit as to the level of the clock signal. An output circuit compares the output voltages of both integrator circuits with a reference voltage and raises the level of its output signal when either one of the output voltages drops below the reference voltage. The duty ratio of the circuitry is therefore little susceptible to the frequency of the input signal and power supply voltage.

Abstract: The objective of the invention is to provide technology to give high-speed DVD RF signal reading. Frequency comparison circuit 1 of the present invention has edge spacing detection circuit 3, maximum spacing detection circuit 4, and minimum spacing detection circuit 5. The number of reference clock pulses in response to an RF signal pulse width (edge spacing) is detected by edge spacing detection circuit 3. The maximum value of the edge spacing in one frame, that is, the maximum edge spacing, is detected by maximum spacing detection circuit 4. The minimum value of the maximum edge spacing in multiple frames is detected by minimum spacing detection circuit 5. The maximum edge spacing minimum value is compared with a number that indicates the frame synchronizing signal period to perform frequency comparison. Edge spacing detection circuit 3, maximum spacing detection circuit 4, and minimum spacing detection circuit 5 are each constituted with registers.

Abstract: A mixer circuit contains a first terminal and a second terminal to which a first differential input signal is applied, and an active element switching a short-circuit between the first terminal and the second terminal. By driving the active element by a second differential input signal having a predetermined frequency, the first terminal and the second terminal are intermittently short-circuited at twice the frequency of a predetermined frequency.

Abstract: A method and circuit for comparing the frequencies of two clocks (clock—1 and clock—2), without taking into account their phase, is disclosed. Each clock is associated to a circular counter (100-1 and 100-2) which are initialized to different values, and the contents of the circular counters are compared. When the frequencies of the two clocks (clock—1 and clock—2) are equal, both counters (100-1 and 100-2) are incremented at a common frequency and thus, due to the initialization conditions, the contents of both counters can never be equal. Conversely, when the frequencies of the two clocks are different, the counters (100-1 and 100-2) are not increased at a common frequency and thus, after several clock pulses, the contents of the counters are equal, indicating different clock frequencies. In a preferred embodiment, the circular counters (100-1 and 100-2) are 2-bit circular counters.

Abstract: An apparatus for detecting a difference between frequencies includes a beat waveform generator which generates a beat waveform signal having a frequency which is equal to a difference between frequencies of a reference clock signal and a target clock signal. A frequency divider divides the reference clock signal by N, where N is an integer, to generate a divided reference-clock signal. A frequency comparator compares frequencies of the beat waveform signal and the divided reference-clock signal, and generates a step out alarm signal which is a binary signal depending upon a polarity of a difference between the frequencies of the beat waveform signal and the divided reference-clock signal.

Abstract: A digital frequency comparator for clock-pulse recovery with “non-return-to-zero data transmission” includes a first double-edge triggered D flip-flop, a second double-edge triggered D flip-flop, and a combination logic. Firstly, the first double-edge triggered D flip-flop receives a data signal and a first reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the first reference clock signal. Secondly, the second double-edge triggered D flip-flop receives a data signal and a second reference clock signal, then makes use of the positive-and-negative triggering to output a first state signal and a second state signal of the second reference clock signal. The phase angle of the second reference clock signal is 90-degree lagging behind the phase angle of the first reference clock signal.

Abstract: A phase frequency detector (PFD) circuit (516) compares two clock signals and generates a number of outputs to indicate a phase difference between these two clock signals (513, 519). The phase frequency detector has more than three states. The PFD circuit may be used in phase locked loop (PLL) or delay locked loop (DLL) circuit in order to maintain or lock a phase relationship between the two clock signals. The PFD circuitry will allow for a fast lock acquisition time, even when there is a relatively wide frequency range between the two clock signals.

Abstract: The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref.

Abstract: A three-state phase detector, including two latches and one NAND gate, is provided with two additional latches. To detect a phase difference between first and second input clock signals R and V, the phase detector alternates among three states responsive to a rising edge of the input R or V signal. Each of the two additional latches and an associated latch in the phase detector together constitute one shift register. When the phase detector gets back to its neutral state, the NAND gate generates a reset signal, thereby resetting all of these four latches. Two isolated pulse generators are further provided. Each of the pulse generators makes the pulse width of a frequency difference pulse signal, output from associated one of the additional latches, constant and then outputs the pulse signal with the constant width.

Abstract: An improved phase-locked loop circuit includes a variable-frequency oscillator that generates a first oscillator signal, a reference signal source that generates a second oscillator signal, a control block that generates a select signal, and a frequency divider that receives as an input signal one of the first and second oscillator signals. The frequency divider also receives the select signal from the control block. The frequency divider generates a plurality of frequency-divided signals in response to the input signal, and passes through a selected one of the plurality of frequency-divided signals as an output signal in response to the select signal. The frequency divider also synchronizes its output signal to its input signal. The phase-locked loop also includes a frequency comparator that receives the output signal of the frequency divider and a signal derived from one of the first and second oscillator signals.

Abstract: Frequencies of clocks CLK1 and CLK2 are divided in frequency divider circuits (11 to 14), frequency-divided clocks CLK1A and CLK1B are input into clock comparators (15) and (16). Frequency-divided clocks CLK2A and CLK2B are input into clock comparators (15) and (16). The clock comparator (15) counts the number of pulses of the clock CLK1A based on the clock CLK2B and outputs an error signal ERR1. The clock comparator (16) counts the number of pulses of the clock CLK2B based on the clock CLK1B and outputs an error signal ERR2. An abnormal clock is detected by examining states of the error signals ERR1 and ERR2.

Abstract: In a frequency detection method for adjusting a clock signal frequency to the data rate of a received data signal, the clock signal which is predivided by a factor of 4. The predivided clock signal and the received data signal are each frequency-divided by the same division factor. The frequencies of the two frequency-divided signals are then determined counting processes and are compared by a subtractor. The frequency difference that is determined is then converted into an analog output signal for controlling the clock signal frequency. This method can be applied in the transmission of data.

Abstract: A delay-locked loop (DLL), including frequency detection logic and a phase detector, is described having an operating range as wide as a conventional charge pump phase locked loop. The frequency detector logic counts the number of rising edges of the multi-phase clocks generated from a reference clock during one period of the reference clock. A loop filter is used to adjust the frequency of each multi-phase clock until frequency lock is obtained by comparing the number of rising edges. After frequency lock, phase detection logic is used to finely tune out the remaining phase error.

Abstract: A digital differential analyzer data synchronizer receives data at a first clock rate and synchronizes the data to a second clock rate. The two clock rates are related by a ratio of two integers, but have a variable phase relationship. The synchronizer places incoming data into a series of registers at the first clock rate. A digital differential analyzer functions to generate a synchronization signal having a frequency proportional to a ratio of the first clock rate and the second clock rate. A multiplexer is utilized for sequentially reading the plurality of registers at a rate corresponding to the frequency of the synchronization signal.

Abstract: A front-end circuit which receives a first input signal and a second input signal, and outputs an output signal having a differential frequency between the first input signal and the second input signal includes: a first amplifier having an input terminal, a power supply terminal and a virtual ground; a second amplifier having an input terminal, a power supply terminal and a ground; and a mixer having a first and a second input terminals, a power supply terminal and a virtual ground.

Abstract: A magnetic detection device including at least one oscillator circuit having a magnetoresistance element which converts a change of magnetism detected into a digital signal and a comparator for comparing the digitalized oscillating frequency of the oscillator circuit with another digitalized oscillating frequency generated from another oscillating circuit by taking a ratio thereof or by detecting a phase difference between the pulse signals. Utilizing the magnetic detection device, the amount of change of magnetism can be stably detected with a high accuracy within a wide range of ambient usage temperatures. The physical quantity detection device includes a magnetic detection device which can detect any physical quantity with a high accuracy.

Abstract: An inherent-security signal comparator (COMP) is driven by two or more input signals (V1, *V2) coming from a control system (.mu.P1, .mu.P2) and generates an alternate output signal (C) of a predetermined frequency whenever both its input signals are identical and terminates its output signal when its input signals wander off from identity, or any of the circuit components of the comparator break down, or its d.c. supply is interrupted. An amplifier (AMP) driven by the comparator drives an isolating transformer (TR) coupled to a voltage rectifier/regulator device (REG) for the supply to the control system. Preferably an oscillator (OSC), whose output is connected to the input of the amplifier (AMP) in common with the output of the comparator, is supplied by a voltage pulse generated by a monostable circuit (T3-R7-R8-R9-C5-C6-D1-D2) which is momentarily enabled at the start-up of the supply circuit.

Abstract: A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The phase-and-frequency detector generates UP and DOWN signals representative of a difference in phase between a pair of digital input signals. The charge pump varies an amount of charge carried within the capacitor in accordance with the UP and DOWN signals. The voltage controlled oscillator generates an output signal having a frequency controlled by both a voltage provided by the capacitor and by the UP and DOWN signals directly received from the phase-and-frequency detector. No analog damping resistor is required. Rather, the damping circuit is an digital circuit which generates adequate phase and frequency damping without a damping resistor. Damping is achieved which is substantially unaffected by process parameters and operating and ambient parameters. Method embodiments of the invention are also described.

Abstract: A harmonic filter for active or adaptive noise attenuation control systems for obtaining the complex amplitude of a single harmonic component from a signal which contains one or more harmonic components.

Abstract: A clock generator system for producing a number of multiple frequency digital clock signals for distribution to a number of synchronous, clocked devices, include two separate, substantially identically structured clock generator units that operate in lock-step unison. The digital clock signal outputs of one of the generator units are distributed to the synchronous, clocked devices and to an error detection circuit, that also receives the digital clock signals from other clock generator unit for comparison with one another. In the event an error is detected, the error detection circuit will produce an error signal to halt operation of the system with which the clock generator system is used, and reset the clock generator.

Abstract: A method and apparatus for a "self-calibration timing circuit" is utilized to dynamically compensate for inherent performance differences between individual semiconductor dice, and for a wide range of different operating temperature and voltage parameters. The present invention accomplishes this by utilizing circuits which are deposed on the semiconductor die. These circuits consist of a relaxation oscillator running at the natural frequency of the silicon die, a gated counter counting the number of cycles of the relaxation oscillator frequency during a reference clock period to produce a ratio thereof, and a decision circuit that utilizes this ratio to optimize a system clock frequency for best system operation.